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Prepare v2021.10-rc4

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Merge tag 'v2021.10-rc4' into next

Prepare v2021.10-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>

# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	board/Arcturus/ucp1020/spl.c
#	cmd/mvebu/Kconfig
#	common/Kconfig.boot
#	common/image-fit.c
#	configs/UCP1020_defconfig
#	configs/sifive_unmatched_defconfig
#	drivers/pci/Kconfig
#	include/configs/UCP1020.h
#	include/configs/sifive-unmatched.h
#	lib/Makefile
#	scripts/config_whitelist.txt
This commit is contained in:
Tom Rini 2021-09-16 10:29:40 -04:00
commit 6674edaabf
215 changed files with 1075 additions and 3314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -490,7 +490,7 @@ F: arch/arm/mach-tegra/
F: arch/arm/include/asm/arch-tegra*/
ARM TI
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-ti.git
F: arch/arm/mach-davinci/

2
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*

3
README
View File

@ -2631,9 +2631,6 @@ Low Level (hardware related) configuration options:
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
- CONFIG_PCI_INDIRECT_BRIDGE:
Enable support for indirect PCI bridges.
- CONFIG_SYS_SRIO:
Chip has SRIO or not

1
arch/Kconfig
View File

@ -206,7 +206,6 @@ config X86
select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select DM
select DM_PCI
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select OF_CONTROL

2
arch/arm/Kconfig
View File

@ -1696,7 +1696,7 @@ config TARGET_SL28
select DM_SPI_FLASH
select DM_ETH
select DM_MDIO
select DM_PCI
select PCI
select DM_RNG
select DM_RTC
select DM_SCSI

6
arch/arm/dts/am33xx.dtsi
View File

@ -380,28 +380,24 @@
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "usb_otg_hs";
status = "disabled";
usb_ctrl_mod: control@44e10620 {
compatible = "ti,am335x-usb-ctrl-module";
reg = <0x44e10620 0x10
0x44e10648 0x4>;
reg-names = "phy_ctrl", "wakeup";
status = "disabled";
};
usb0_phy: usb-phy@47401300 {
compatible = "ti,am335x-usb-phy";
reg = <0x47401300 0x100>;
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
compatible = "ti,musb-am33xx";
status = "disabled";
reg = <0x47401400 0x400
0x47401000 0x200>;
reg-names = "mc", "control";
@ -443,14 +439,12 @@
compatible = "ti,am335x-usb-phy";
reg = <0x47401b00 0x100>;
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb1: usb@47401800 {
compatible = "ti,musb-am33xx";
status = "disabled";
reg = <0x47401c00 0x400
0x47401800 0x200>;
reg-names = "mc", "control";

4
arch/arm/dts/am3517-evm-ui.dtsi
View File

@ -186,14 +186,14 @@
};
&mcbsp1 {
status = "ok";
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
};
&mcbsp2 {
status = "ok";
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;

2
arch/arm/dts/am3517-evm.dts
View File

@ -193,7 +193,7 @@
};
&dss {
status = "ok";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;

2
arch/arm/dts/am437x-gp-evm.dts
View File

@ -742,7 +742,7 @@
};
&dss {
status = "ok";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pins>;

2
arch/arm/dts/am43x-epos-evm.dts
View File

@ -752,7 +752,7 @@
};
&dss {
status = "ok";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pins>;

6
arch/arm/dts/am57xx-beagle-x15-common.dtsi
View File

@ -528,13 +528,13 @@
};
&dss {
status = "ok";
status = "okay";
vdda_video-supply = <&ldoln_reg>;
};
&hdmi {
status = "ok";
status = "okay";
vdda-supply = <&ldo4_reg>;
port {
@ -545,7 +545,7 @@
};
&pcie1_rc {
status = "ok";
status = "okay";
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};

1
arch/arm/dts/armada-7040-db.dts
View File

@ -175,6 +175,7 @@
};
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};

1
arch/arm/dts/armada-8040-clearfog-gt-8k.dts
View File

@ -295,6 +295,7 @@
};
&cp1_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};

1
arch/arm/dts/armada-8040-db.dts
View File

@ -270,6 +270,7 @@
};
&cp0_mdio {
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};

1
arch/arm/dts/armada-8040-mcbin.dts
View File

@ -155,6 +155,7 @@
};
&cp0_mdio {
status = "okay";
ge_phy: ethernet-phy@0 {
reg = <0>;
};

23
arch/arm/dts/beacon-renesom-som.dtsi
View File

@ -7,6 +7,10 @@
#include <dt-bindings/clk/versaclock.h>
/ {
aliases {
spi0 = &rpc;
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -275,6 +279,25 @@
};
};
&rpc {
compatible = "renesas,rcar-gen3-rpc";
num-cs = <1>;
spi-max-frequency = <40000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "spi-flash", "jedec,spi-nor";
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&scif_clk {
clock-frequency = <14745600>;
};

2
arch/arm/dts/da850-evm.dts
View File

@ -405,7 +405,7 @@
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
status = "ok";
status = "okay";
cs3 {
#address-cells = <2>;
#size-cells = <1>;

2
arch/arm/dts/dra7-evm.dts
View File

@ -501,7 +501,7 @@
};
&dcan1 {
status = "ok";
status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;

6
arch/arm/dts/dra72-evm-common.dtsi
View File

@ -430,7 +430,7 @@
};
&dcan1 {
status = "ok";
status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
@ -499,11 +499,11 @@
};
&dss {
status = "ok";
status = "okay";
};
&hdmi {
status = "ok";
status = "okay";
port {
hdmi_out: endpoint {

4
arch/arm/dts/k3-am642-evm-u-boot.dtsi
View File

@ -59,6 +59,10 @@
u-boot,dm-spl;
};
&main_mmc1_pins_default {
u-boot,dm-spl;
};
&main_usb0_pins_default {
u-boot,dm-spl;
};

2
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
View File

@ -280,7 +280,7 @@
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clocks = <&clk_19_2mhz>;
clock-names = "usb2_refclk";
clock-names = "ref";
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;

2
arch/arm/dts/keystone-k2e-evm.dts
View File

@ -142,7 +142,7 @@
};
&mdio {
status = "ok";
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;

2
arch/arm/dts/keystone-k2hk-evm.dts
View File

@ -170,7 +170,7 @@
};
&mdio {
status = "ok";
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <0>;

2
arch/arm/dts/keystone-k2l-evm.dts
View File

@ -119,7 +119,7 @@
};
&mdio {
status = "ok";
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;

4
arch/arm/dts/omap3-beagle-xm.dts
View File

@ -379,7 +379,7 @@
};
&dss {
status = "ok";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
@ -396,7 +396,7 @@
};
&venc {
status = "ok";
status = "okay";
vdda-supply = <&vdac>;

6
arch/arm/dts/omap3-beagle.dts
View File

@ -353,7 +353,7 @@
};
&dss {
status = "ok";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
@ -367,7 +367,7 @@
};
&venc {
status = "ok";
status = "okay";
vdda-supply = <&vdac>;
@ -380,7 +380,7 @@
};
&gpmc {
status = "ok";
status = "okay";
ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
/* Chip select 0 */

2
arch/arm/dts/omap3-igep0020-common.dtsi
View File

@ -248,7 +248,7 @@
};
&dss {
status = "ok";
status = "okay";
port {
dpi_out: endpoint {

2
arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi
View File

@ -46,7 +46,7 @@
};
&dss {
status = "ok";
status = "okay";
port {
dpi_out: endpoint {
remote-endpoint = <&lcd_in>;

2
arch/arm/dts/omap34xx.dtsi
View File

@ -69,7 +69,7 @@
};
&ssi {
status = "ok";
status = "okay";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,

2
arch/arm/dts/omap36xx.dtsi
View File

@ -153,7 +153,7 @@
};
&ssi {
status = "ok";
status = "okay";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,

6
arch/arm/dts/omap4-panda-common.dtsi
View File

@ -546,7 +546,7 @@
};
&dss {
status = "ok";
status = "okay";
port {
dpi_out: endpoint {
@ -557,12 +557,12 @@
};
&dsi2 {
status = "ok";
status = "okay";
vdd-supply = <&vcxio>;
};
&hdmi {
status = "ok";
status = "okay";
vdda-supply = <&vdac>;
port {

8
arch/arm/dts/omap4-sdp.dts
View File

@ -648,11 +648,11 @@
};
&dss {
status = "ok";
status = "okay";
};
&dsi1 {
status = "ok";
status = "okay";
vdd-supply = <&vcxio>;
port {
@ -677,7 +677,7 @@
};
&dsi2 {
status = "ok";
status = "okay";
vdd-supply = <&vcxio>;
port {
@ -702,7 +702,7 @@
};
&hdmi {
status = "ok";
status = "okay";
vdda-supply = <&vdac>;
port {

4
arch/arm/dts/omap5-board-common.dtsi
View File

@ -743,11 +743,11 @@
};
&dss {
status = "ok";
status = "okay";
};
&hdmi {
status = "ok";
status = "okay";
/* vdda-supply populated in board specific dts file */

2
arch/arm/mach-imx/mx6/Kconfig
View File

@ -236,7 +236,7 @@ config TARGET_KOSAGI_NOVENA
select DM_ETH
select DM_GPIO
select DM_MMC
select DM_PCI
select PCI
select DM_SCSI
select DM_VIDEO
select OF_CONTROL

60
arch/arm/mach-mvebu/cpu.c
View File

@ -14,6 +14,7 @@
#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/spl.h>
#include <sdhci.h>
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
@ -80,6 +81,65 @@ int mvebu_soc_family(void)
return MVEBU_SOC_UNKNOWN;
}
u32 get_boot_device(void)
{
u32 val;
u32 boot_device;
/*
* First check, if UART boot-mode is active. This can only
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)
return BOOT_DEVICE_UART;
#ifdef CONFIG_ARMADA_38X
/*
* If the bootrom error code contains any other than zeros it's an
* error condition and the bootROM has fallen back to UART boot
*/
boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
if (boot_device)
return BOOT_DEVICE_UART;
#endif
/*
* Now check the SAR register for the strapped boot-device
*/
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
#ifdef BOOT_FROM_NAND
case BOOT_FROM_NAND:
return BOOT_DEVICE_NAND;
#endif
#ifdef BOOT_FROM_MMC
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
return BOOT_DEVICE_MMC1;
#endif
case BOOT_FROM_UART:
#ifdef BOOT_FROM_UART_ALT
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
#ifdef BOOT_FROM_SATA
case BOOT_FROM_SATA:
case BOOT_FROM_SATA_ALT:
return BOOT_DEVICE_SATA;
#endif
case BOOT_FROM_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_BOOTROM;
};
}
#if defined(CONFIG_DISPLAY_CPUINFO)
#if defined(CONFIG_ARMADA_375)

2
arch/arm/mach-mvebu/include/mach/cpu.h
View File

@ -148,6 +148,8 @@ void __noreturn return_to_bootrom(void);
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
#endif
u32 get_boot_device(void);
void get_sar_freq(struct sar_freq_modes *sar_freq);
/*

2
arch/arm/mach-mvebu/include/mach/soc.h
View File

@ -189,7 +189,7 @@
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#else
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))

77
arch/arm/mach-mvebu/spl.c
View File

@ -172,74 +172,6 @@ int spl_parse_board_header(struct spl_image_info *spl_image,
return 0;
}
static u32 get_boot_device(void)
{
u32 val;
u32 boot_device;
/*
* First check, if UART boot-mode is active. This can only
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)
return BOOT_DEVICE_UART;
#ifdef CONFIG_ARMADA_38X
/*
* If the bootrom error code contains any other than zeros it's an
* error condition and the bootROM has fallen back to UART boot
*/
boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
if (boot_device)
return BOOT_DEVICE_UART;
#endif
/*
* Now check the SAR register for the strapped boot-device
*/
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
#ifdef BOOT_FROM_NAND
case BOOT_FROM_NAND:
return BOOT_DEVICE_NAND;
#endif
#ifdef BOOT_FROM_MMC
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
return BOOT_DEVICE_MMC1;
#endif
case BOOT_FROM_UART:
#ifdef BOOT_FROM_UART_ALT
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
#ifdef BOOT_FROM_SATA
case BOOT_FROM_SATA:
case BOOT_FROM_SATA_ALT:
return BOOT_DEVICE_SATA;
#endif
case BOOT_FROM_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_BOOTROM;
};
}
#else
static u32 get_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
#endif
u32 spl_boot_device(void)
{
u32 boot_device = get_boot_device();
@ -286,6 +218,15 @@ u32 spl_boot_device(void)
}
}
#else
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
#endif
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{

2
arch/arm/mach-socfpga/Kconfig
View File

@ -11,7 +11,7 @@ config SOCFPGA_SECURE_VAB_AUTH
depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
select SHA512
select SPL_FIT_IMAGE_POST_PROCESS
help
All images loaded from FIT will be authenticated by Secure Device

2
arch/arm/mach-stm32mp/dram_init.c
View File

@ -47,7 +47,7 @@ ulong board_get_usable_ram_top(ulong total_size)
struct lmb lmb;
if (!total_size)
return gd->ram_base + gd->ram_size;
return gd->ram_top;
/* found enough not-reserved memory to relocated U-Boot */
lmb_init(&lmb);

2
arch/mips/Kconfig
View File

@ -17,7 +17,7 @@ config TARGET_MALTA
select BOARD_EARLY_INIT_R
select DM
select DM_SERIAL
select DM_PCI
select PCI
select DM_ETH
select DYNAMIC_IO_PORT_BASE
select MIPS_CM

7
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -179,12 +179,6 @@ config TARGET_KMCENT2
bool "Support kmcent2"
select VENDOR_KM
config TARGET_UCP1020
bool "Support uCP1020"
select ARCH_P1020
imply CMD_SATA
imply PANIC_HANG
endchoice
config ARCH_B4420
@ -1163,6 +1157,5 @@ source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
source "board/socrates/Kconfig"
source "board/Arcturus/ucp1020/Kconfig"
endmenu

5
arch/riscv/Kconfig
View File

@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config SIFIVE_CACHE
bool
help
This enables the operations to configure SiFive cache
config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE

2
arch/riscv/cpu/fu540/Kconfig
View File

@ -19,6 +19,8 @@ config SIFIVE_FU540
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII

1
arch/riscv/cpu/fu540/Makefile
View File

@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif

55
arch/riscv/cpu/fu540/cache.c
View File

@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu540-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}

2
arch/riscv/cpu/fu740/Kconfig
View File

@ -19,6 +19,8 @@ config SIFIVE_FU740
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_PRCI
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SIFIVE_SERIAL
imply MACB
imply MII

1
arch/riscv/cpu/fu740/Makefile
View File

@ -8,5 +8,4 @@ obj-y += spl.o
else
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o
endif

55
arch/riscv/cpu/fu740/cache.c
View File

@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020-2021 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/global_data.h>
/* Register offsets */
#define L2_CACHE_CONFIG 0x000
#define L2_CACHE_ENABLE 0x008
#define MASK_NUM_WAYS GENMASK(15, 8)
#define NUM_WAYS_SHIFT 8
DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node;
fdt_addr_t base;
u32 config;
u32 ways;
volatile u32 *enable;
node = fdt_node_offset_by_compatible(blob, -1,
"sifive,fu740-c000-ccache");
if (node < 0)
return node;
base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
NULL, false);
if (base == FDT_ADDR_T_NONE)
return FDT_ADDR_T_NONE;
config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
/* memory barrier */
mb();
(*enable) = ways - 1;
/* memory barrier */
mb();
return 0;
}

14
arch/riscv/include/asm/arch-fu540/cache.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */

14
arch/riscv/include/asm/arch-fu740/cache.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020-2021 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */

2
arch/riscv/include/asm/cache.h
View File

@ -8,7 +8,7 @@
#define _ASM_RISCV_CACHE_H
/* cache */
void cache_flush(void);
void cache_flush(void);
/*
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.

1
arch/riscv/lib/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o

4
arch/riscv/lib/cache.c
View File

@ -70,3 +70,7 @@ __weak int dcache_status(void)
{
return 0;
}
__weak void enable_caches(void)
{
}

33
arch/riscv/lib/interrupts.c
View File

@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs)
#endif
}
/**
* instr_len() - get instruction length
*
* @i: low 16 bits of the instruction
* Return: number of u16 in instruction
*/
static int instr_len(u16 i)
{
if ((i & 0x03) != 0x03)
return 1;
/* Instructions with more than 32 bits are not yet specified */
return 2;
}
/**
* show_code() - display code leading to exception
*
* @epc: program counter
*/
static void show_code(ulong epc)
{
u16 *pos = (u16 *)(epc & ~1UL);
int i, len = instr_len(*pos);
printf("\nCode: ");
for (i = -8; i; ++i)
printf("%04x ", pos[i]);
printf("(");
for (i = 0; i < len; ++i)
printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " ");
}
static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
{
static const char * const exception_code[] = {
@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
epc - gd->reloc_off, regs->ra - gd->reloc_off);
show_regs(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
}

27
arch/riscv/lib/sifive_cache.c Normal file
View File

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 SiFive, Inc
*/
#include <common.h>
#include <cache.h>
#include <cpu_func.h>
#include <dm.h>
void enable_caches(void)
{
struct udevice *dev;
int ret;
/* Enable ways of ccache */
ret = uclass_get_device_by_driver(UCLASS_CACHE,
DM_DRIVER_GET(sifive_ccache),
&dev);
if (ret) {
log_debug("Cannot enable cache ways");
} else {
ret = cache_enable(dev);
if (ret)
log_debug("ccache enable failed");
}
}

36
board/Arcturus/ucp1020/Kconfig
View File

@ -1,36 +0,0 @@
if TARGET_UCP1020
config SYS_BOARD
string
default "ucp1020"
config SYS_VENDOR
string
default "Arcturus"
config SYS_CONFIG_NAME
string
default "UCP1020"
choice
prompt "Target image select"
config TARGET_UCP1020_NOR
bool "NOR flash u-boot image"
config TARGET_UCP1020_SPIFLASH
bool "SPI flash u-boot image"
endchoice
if TARGET_UCP1020_SPIFLASH
config UCBOOT
bool
default y
config SPIFLASH
bool
default y
endif
endif

7
board/Arcturus/ucp1020/MAINTAINERS
View File

@ -1,7 +0,0 @@
UCP1020 BOARD
M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
S: Maintained
F: board/Arcturus/ucp1020/
F: include/configs/UCP1020.h
F: configs/UCP1020_defconfig
F: configs/UCP1020_SPIFLASH_defconfig

31
board/Arcturus/ucp1020/Makefile
View File

@ -1,31 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013-2015 Arcturus Networks, Inc.
# based on board/freescale/p1_p2_rdb_pc/Makefile
# original copyright follows:
# Copyright 2010-2011 Freescale Semiconductor, Inc.
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o tlb.o law.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
obj-y += ucp1020.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
obj-y += cmd_arc.o
endif

54
board/Arcturus/ucp1020/README
View File

@ -1,54 +0,0 @@
The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
Information on the generic product family can be found here:
http://www.arcturusnetworks.com/products/ucp1020
The UCP1020 several configurable options
========================================
- the selection of populated phy(s):
KSZ9031 (current default for eTSEC 1 and 3)
- the selection of boot location:
SPI Flash or NOR flash
The UCP1020 includes 2 default configurations
=============================================
NOR boot image:
configs/UCP1020_defconfig
SPI boot image:
configs/UCP1020_SPIFLASH_defconfig
The UCP1020 adds an additional command in cmd_arc.c to access and program
SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
HW Addresses.
Build example
=============
make distclean
make UCP1020_defconfig
make
Default Scripts
===============
A default upgrade scripts is included in the default environment variable example:
B$ run tftpflash
Dual Environment
================
This build enables dual / failover environment environment.
NOR Flash Partition declarations and scripts
============================================
Several scripts are available to allow TFTP of images and programming directly
into defined NOR flash partitions. Examples:
B$ run program0
B$ run program1
B$ run program2

408
board/Arcturus/ucp1020/cmd_arc.c
View File

@ -1,408 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Command for accessing Arcturus factory environment.
*
* Copyright 2013-2019 Arcturus Networks Inc.
* https://www.arcturusnetworks.com/products/
* by Oleksandr G Zhadan et al.
*
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <div64.h>
#include <env.h>
#include <flash.h>
#include <malloc.h>
#include <spi_flash.h>
#include <mmc.h>
#include <version.h>
#include <asm/io.h>
#include <linux/stringify.h>
static ulong fwenv_addr[MAX_FWENV_ADDR];
const char mystrerr[] = "ERROR: Failed to save factory info";
static int ishwaddr(char *hwaddr)
{
if (strlen(hwaddr) == MAX_HWADDR_SIZE)
if (hwaddr[2] == ':' &&
hwaddr[5] == ':' &&
hwaddr[8] == ':' &&
hwaddr[11] == ':' &&
hwaddr[14] == ':')
return 0;
return -1;
}
#if (FWENV_TYPE == FWENV_MMC)
static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */
int set_mmc_arc_product(int argc, char *const argv[])
{
struct mmc *mmc;
u32 blk, cnt, n;
int i, err = 1;
void *addr;
const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
mmc = find_mmc_device(mmc_dev_num);
if (!mmc) {
printf("No SD/MMC/eMMC card found\n");
return 0;
}
if (mmc_init(mmc)) {
printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
mmc_dev_num);
return 0;
}
if (mmc_getwp(mmc) == 1) {
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
/* Save factory defaults */
addr = (void *)smac;
cnt = 1; /* One 512 bytes block */
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1) {
blk = fwenv_addr[i] / 512;
n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
if (n != cnt)
printf("%s: %s [%d]\n", __func__, mystrerr, i);
else
err = 0;
}
if (err)
return -2;
return err;
}
static int read_mmc_arc_info(void)
{
struct mmc *mmc;
u32 blk, cnt, n;
int i;
void *addr;
const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
mmc = find_mmc_device(mmc_dev_num);
if (!mmc) {
printf("No SD/MMC/eMMC card found\n");
return 0;
}
if (mmc_init(mmc)) {
printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
mmc_dev_num);
return 0;
}
addr = (void *)smac;
cnt = 1; /* One 512 bytes block */
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1) {
blk = fwenv_addr[i] / 512;
n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
flush_cache((ulong) addr, 512);
if (n == cnt)
return (i + 1);
}
return 0;
}
#endif
#if (FWENV_TYPE == FWENV_SPI_FLASH)
static struct spi_flash *flash;
static char smac[4][18];
int set_spi_arc_product(int argc, char *const argv[])
{
int i, err = 1;
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!flash) {
printf("Failed to initialize SPI flash at %u:%u\n",
CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
return -1;
}
/* Save factory defaults */
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1)
if (spi_flash_write
(flash, fwenv_addr[i], sizeof(smac), smac))
printf("%s: %s [%d]\n", __func__, mystrerr, i);
else
err = 0;
if (err)
return -2;
return err;
}
static int read_spi_arc_info(void)
{
int i;
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!flash) {
printf("Failed to initialize SPI flash at %u:%u\n",
CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
return 0;
}
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1)
if (!spi_flash_read
(flash, fwenv_addr[i], sizeof(smac), smac))
return (i + 1);
return 0;
}
#endif
#if (FWENV_TYPE == FWENV_NOR_FLASH)
static char smac[4][18];
int set_nor_arc_product(int argc, char *const argv[])
{
int i, err = 1;
/* Save factory defaults */
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1) {
ulong fwenv_end = fwenv_addr[i] + 4;
flash_sect_roundb(&fwenv_end);
flash_sect_protect(0, fwenv_addr[i], fwenv_end);
if (flash_write
((char *)smac, fwenv_addr[i], sizeof(smac)))
printf("%s: %s [%d]\n", __func__, mystrerr, i);
else
err = 0;
flash_sect_protect(1, fwenv_addr[i], fwenv_end);
}
if (err)
return -2;
return err;
}
static int read_nor_arc_info(void)
{
int i;
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1) {
memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
return (i + 1);
}
return 0;
}
#endif
int set_arc_product(int argc, char *const argv[])
{
if (argc != 5)
return -1;
/* Check serial number */
if (strlen(argv[1]) != MAX_SERIAL_SIZE)
return -1;
/* Check HWaddrs */
if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
return -1;
strcpy(smac[0], argv[1]);
strcpy(smac[1], argv[2]);
strcpy(smac[2], argv[3]);
strcpy(smac[3], argv[4]);
#if (FWENV_TYPE == FWENV_NOR_FLASH)
return set_nor_arc_product(argc, argv);
#endif
#if (FWENV_TYPE == FWENV_SPI_FLASH)
return set_spi_arc_product(argc, argv);
#endif
#if (FWENV_TYPE == FWENV_MMC)
return set_mmc_arc_product(argc, argv);
#endif
return -2;
}
static int read_arc_info(void)
{
#if (FWENV_TYPE == FWENV_NOR_FLASH)
return read_nor_arc_info();
#endif
#if (FWENV_TYPE == FWENV_SPI_FLASH)
return read_spi_arc_info();
#endif
#if (FWENV_TYPE == FWENV_MMC)
return read_mmc_arc_info();
#endif
return 0;
}
static int do_get_arc_info(void)
{
int l = read_arc_info();
char *oldserial = env_get("SERIAL");
char *oldversion = env_get("VERSION");
if (oldversion != NULL)
if (strcmp(oldversion, U_BOOT_VERSION) != 0)
oldversion = NULL;
if (l == 0) {
printf("%s: failed to read factory info\n", __func__);
return -2;
}
printf("\rSERIAL: ");
if (smac[0][0] == EMPY_CHAR) {
printf("<not found>\n");
} else {
printf("%s\n", smac[0]);
env_set("SERIAL", smac[0]);
}
if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
env_set("ethaddr", NULL);
env_set("eth1addr", NULL);
env_set("eth2addr", NULL);
goto done;
}
printf("HWADDR0: ");
if (smac[1][0] == EMPY_CHAR) {
printf("<not found>\n");
} else {
char *ret = env_get("ethaddr");
if (ret == NULL) {
env_set("ethaddr", smac[1]);
printf("%s\n", smac[1]);
} else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
env_set("ethaddr", smac[1]);
printf("%s (factory)\n", smac[1]);
} else {
printf("%s\n", ret);
}
}
if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
env_set("eth1addr", NULL);
env_set("eth2addr", NULL);
goto done;
}
printf("HWADDR1: ");
if (smac[2][0] == EMPY_CHAR) {
printf("<not found>\n");
} else {
char *ret = env_get("eth1addr");
if (ret == NULL) {
env_set("ethaddr", smac[2]);
printf("%s\n", smac[2]);
} else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
env_set("eth1addr", smac[2]);
printf("%s (factory)\n", smac[2]);
} else {
printf("%s\n", ret);
}
}
if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
env_set("eth2addr", NULL);
goto done;
}
printf("HWADDR2: ");
if (smac[3][0] == EMPY_CHAR) {
printf("<not found>\n");
} else {
char *ret = env_get("eth2addr");
if (ret == NULL) {
env_set("ethaddr", smac[3]);
printf("%s\n", smac[3]);
} else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
env_set("eth2addr", smac[3]);
printf("%s (factory)\n", smac[3]);
} else {
printf("%s\n", ret);
}
}
done:
if (oldserial == NULL || oldversion == NULL) {
if (oldversion == NULL)
env_set("VERSION", U_BOOT_VERSION);
env_save();
}
return 0;
}
static int init_fwenv(void)
{
int i, ret = -1;
fwenv_addr[0] = FWENV_ADDR1;
fwenv_addr[1] = FWENV_ADDR2;
fwenv_addr[2] = FWENV_ADDR3;
fwenv_addr[3] = FWENV_ADDR4;
for (i = 0; i < MAX_FWENV_ADDR; i++)
if (fwenv_addr[i] != -1)
ret = 0;
if (ret)
printf("%s: No firmfare info storage address is defined\n",
__func__);
return ret;
}
void get_arc_info(void)
{
if (!init_fwenv())
do_get_arc_info();
}
static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
const char *cmd;
int ret = -1;
cmd = argv[1];
--argc;
++argv;
if (init_fwenv())
return ret;
if (strcmp(cmd, "product") == 0)
ret = set_arc_product(argc, argv);
else if (strcmp(cmd, "info") == 0)
ret = do_get_arc_info();
if (ret == -1)
return CMD_RET_USAGE;
return ret;
}
U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
"Arcturus product command sub-system",
"product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
"info - show Arcturus factory env\n\n");

161
board/Arcturus/ucp1020/ddr.c
View File

@ -1,161 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Arcturus Networks, Inc.
* http://www.arcturusnetworks.com/products/ucp1020/
* based on board/freescale/p1_p2_rdb_pc/spl.c
* original copyright follows:
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <vsprintf.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
/*
* Micron MT41J128M16HA-15E
* */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 536870912u,
.capacity = 536870912u,
.primary_sdram_width = 32,
.ec_sdram_width = 8,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 14,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1650,
.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
.taa_ps = 14050,
.twr_ps = 15000,
.trcd_ps = 13500,
.trrd_ps = 75000,
.trp_ps = 13500,
.tras_ps = 40000,
.trc_ps = 49500,
.trfc_ps = 160000,
.twtr_ps = 75000,
.trtp_ps = 75000,
.refresh_rate_ps = 7800000,
.tfaw_ps = 30000,
};
#else
#error Missing raw timing data for this board
#endif
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
#ifdef CONFIG_SYS_DDR_CS0_BNDS
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
sys_info_t sysinfo;
char buf[32];
size_t ddr_size;
fsl_ddr_cfg_regs_t ddr_cfg_regs = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
return ddr_size;
}
#endif
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
if (pdimm->primary_sdram_width == 64)
popts->data_bus_width = 0;
else if (pdimm->primary_sdram_width == 32)
popts->data_bus_width = 1;
else
printf("Error in DDR bus width configuration!\n");
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}

24
board/Arcturus/ucp1020/law.c
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@ -1,24 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Arcturus Networks, Inc.
* http://www.arcturusnetworks.com/products/ucp1020/
* based on board/freescale/p1_p2_rdb_pc/spl.c
* original copyright follows:
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

127
board/Arcturus/ucp1020/spl.c
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@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Arcturus Networks, Inc.
* http://www.arcturusnetworks.com/products/ucp1020/
* based on board/freescale/p1_p2_rdb_pc/spl.c
* original copyright follows:
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <console.h>
#include <env.h>
#include <env_internal.h>
#include <init.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
#include <nand.h>
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static const u32 sysclk_tbl[] = {
66666000, 7499900, 83332500, 8999900,
99999000, 11111000, 12499800, 13333200
};
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
#ifdef CONFIG_SPL_SPI_BOOT
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
#endif
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = bus_clk;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI Flash boot...\n");
#endif
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
#else
env_relocate();
#endif
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
puts("Second program loader running in sram...\n");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

67
board/Arcturus/ucp1020/spl_minimal.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Arcturus Networks, Inc.
* http://www.arcturusnetworks.com/products/ucp1020/
* based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
* original copyright follows:
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("\nSecond program loader running in sram...");
nand_boot();
}
void putc(char c)
{
if (c == '\n')
ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

100
board/Arcturus/ucp1020/tlb.c
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@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2015 Arcturus Networks, Inc
* http://www.arcturusnetworks.com/products/ucp1020/
* based on board/freescale/p1_p2_rdb_pc/tlb.c
* original copyright follows:
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
#ifdef CONFIG_PCI
/* *I*G* - PCI memory 1.5G */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O effective: 192K */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
#endif
#ifdef CONFIG_VSC7385_ENET
/* *I*G - VSC7385 Switch */
SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
#endif
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif /* RAMBOOT/SPL */
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#if CONFIG_SYS_L2_SIZE >= (256 << 10)
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1)
#endif
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

372
board/Arcturus/ucp1020/ucp1020.c
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@ -1,372 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2019 Arcturus Networks, Inc.
* https://www.arcturusnetworks.com/products/ucp1020/
* by Oleksandr G Zhadan et al.
* based on board/freescale/p1_p2_rdb_pc/spl.c
* original copyright follows:
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <hwconfig.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <ioports.h>
#include <netdev.h>
#include <micrel.h>
#include <spi_flash.h>
#include <mmc.h>
#include <linux/ctype.h>
#include <asm/fsl_serdes.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <asm/mp.h>
#include "ucp1020.h"
void spi_set_speed(struct spi_slave *slave, uint hz)
{
/* TO DO: It's actially have to be in spi/ */
}
/*
* To be compatible with cmd_gpio
*/
int name_to_gpio(const char *name)
{
int gpio = 31 - dectoul(name, NULL);
if (gpio < 16)
gpio = -1;
return gpio;
}
void board_gpio_init(void)
{
int i;
char envname[8], *val;
for (i = 0; i < GPIO_MAX_NUM; i++) {
sprintf(envname, "GPIO%d", i);
val = env_get(envname);
if (val) {
char direction = toupper(val[0]);
char level = toupper(val[1]);
if (direction == 'I') {
gpio_direction_input(i);
} else {
if (direction == 'O') {
if (level == '1')
gpio_direction_output(i, 1);
else
gpio_direction_output(i, 0);
}
}
}
}
val = env_get("PCIE_OFF");
if (val) {
gpio_direction_input(GPIO_PCIE1_EN);
gpio_direction_input(GPIO_PCIE2_EN);
} else {
gpio_direction_output(GPIO_PCIE1_EN, 1);
gpio_direction_output(GPIO_PCIE2_EN, 1);
}
val = env_get("SDHC_CDWP_OFF");
if (!val) {
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
}
}
int board_early_init_f(void)
{
return 0; /* Just in case. Could be disable in config file */
}
int checkboard(void)
{
printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
board_gpio_init();
#ifdef CONFIG_MMC
printf("SD/MMC: 4-bit Mode\n");
#endif
return 0;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
#if defined(CONFIG_PHY_MICREL_KSZ9021)
int regval;
static int cnt;
if (cnt++ == 0)
printf("PHYs address [");
if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
regval =
ksz9021_phy_extended_read(phydev,
MII_KSZ9021_EXT_STRAP_STATUS);
/*
* min rx data delay
*/
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x6666);
/*
* max rx/tx clock delay, min rx/tx control
*/
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf6f6);
printf("0x%x", (regval & 0x1f));
} else {
printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
}
if (cnt == 3)
printf("] ");
else
printf(",");
#endif
#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
if (regval >= 0)
printf(" (ADDR 0x%x) ", regval & 0x1f);
#endif
return 0;
}
int last_stage_init(void)
{
static char newkernelargs[256];
static u8 id1[16];
static u8 id2;
#ifdef CONFIG_MMC
struct mmc *mmc;
#endif
char *sval, *kval;
if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
printf("Error reading i2c IDT6V49205B information!\n");
} else {
printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
if (!(id1[1] & 0x02)) {
id1[1] |= 0x02;
i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
asm("nop; nop");
}
}
if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
printf("Error reading i2c NCT72 information!\n");
else
printf("NCT72(0x%x): ready\n", id2);
kval = env_get("kernelargs");
#ifdef CONFIG_MMC
mmc = find_mmc_device(0);
if (mmc)
if (!mmc_init(mmc)) {
printf("MMC/SD card detected\n");
if (kval) {
int n = strlen(defkargs);
char *tmp = strstr(kval, defkargs);
*tmp = 0;
strcpy(newkernelargs, kval);
strcat(newkernelargs, " ");
strcat(newkernelargs, mmckargs);
strcat(newkernelargs, " ");
strcat(newkernelargs, &tmp[n]);
env_set("kernelargs", newkernelargs);
} else {
env_set("kernelargs", mmckargs);
}
}
#endif
get_arc_info();
if (kval) {
sval = env_get("SERIAL");
if (sval) {
strcpy(newkernelargs, "SN=");
strcat(newkernelargs, sval);
strcat(newkernelargs, " ");
strcat(newkernelargs, kval);
env_set("kernelargs", newkernelargs);
}
} else {
printf("Error reading kernelargs env variable!\n");
}
return 0;
}
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
#ifdef CONFIG_TSEC2
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
puts("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
}
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
return pci_eth_init(bis);
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
phys_addr_t base;
phys_size_t size;
const char *soc_usb_compat = "fsl-usb2-dr";
int err, usb1_off, usb2_off;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
FT_FSL_PCI_SETUP;
#if defined(CONFIG_HAS_FSL_DR_USB)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
const char *soc_elbc_compat = "fsl,p1020-elbc";
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
printf
("WARNING: could not find compatible node %s: %s\n",
soc_elbc_compat, fdt_strerror(off));
return off;
}
err = fdt_del_node(blob, off);
if (err < 0) {
printf("WARNING: could not remove %s: %s\n",
soc_elbc_compat, fdt_strerror(err));
}
return err;
}
#endif
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
if (usb1_off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
soc_usb_compat, fdt_strerror(usb1_off));
return usb1_off;
}
usb2_off =
fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
if (usb2_off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
soc_usb_compat, fdt_strerror(usb2_off));
return usb2_off;
}
err = fdt_del_node(blob, usb2_off);
if (err < 0) {
printf("WARNING: could not remove %s: %s.\n",
soc_usb_compat, fdt_strerror(err));
}
return 0;
}
#endif

45
board/Arcturus/ucp1020/ucp1020.h
View File

@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013-2019 Arcturus Networks, Inc.
* https://www.arcturusnetworks.com/products/ucp1020/
* by Oleksandr G Zhadan et al.
*/
#ifndef __UCP1020_H__
#define __UCP1020_H__
#define GPIO0 31
#define GPIO1 30
#define GPIO2 29
#define GPIO3 28
#define GPIO4 27
#define GPIO5 26
#define GPIO6 25
#define GPIO7 24
#define GPIO8 23
#define GPIO9 22
#define GPIO10 21
#define GPIO11 20
#define GPIO12 19
#define GPIO13 18
#define GPIO14 17
#define GPIO15 16
#define GPIO_MAX_NUM 16
#define GPIO_SDHC_CD GPIO8
#define GPIO_SDHC_WP GPIO9
#define GPIO_USB_PCTL0 GPIO10
#define GPIO_PCIE1_EN GPIO11
#define GPIO_PCIE2_EN GPIO10
#define GPIO_USB_PCTL1 GPIO11
#define GPIO_WD GPIO15
#ifdef CONFIG_MMC
static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
#endif
int get_arc_info(void);
#endif

27
board/CZ.NIC/turris_omnia/turris_omnia.c
View File

@ -129,7 +129,6 @@ static int omnia_mcu_read(u8 cmd, void *buf, int len)
return dm_i2c_read(chip, cmd, buf, len);
}
#ifndef CONFIG_SPL_BUILD
static int omnia_mcu_write(u8 cmd, const void *buf, int len)
{
struct udevice *chip;
@ -158,7 +157,6 @@ static bool disable_mcu_watchdog(void)
return true;
}
#endif
static bool omnia_detect_sata(void)
{
@ -325,7 +323,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
return &board_topology_map_1g;
}
#ifndef CONFIG_SPL_BUILD
static int set_regdomain(void)
{
struct omnia_eeprom oep;
@ -394,7 +391,6 @@ static void handle_reset_button(void)
}
}
}
#endif
int board_early_init_f(void)
{
@ -423,24 +419,35 @@ int board_early_init_f(void)
return 0;
}
void spl_board_init(void)
{
/*
* If booting from UART, disable MCU watchdog in SPL, since uploading
* U-Boot proper can take too much time and trigger it.
*/
if (get_boot_device() == BOOT_DEVICE_UART)
disable_mcu_watchdog();
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
#ifndef CONFIG_SPL_BUILD
disable_mcu_watchdog();
#endif
return 0;
}
int board_late_init(void)
{
#ifndef CONFIG_SPL_BUILD
/*
* If not booting from UART, MCU watchdog was not disabled in SPL,
* disable it now.
*/
if (get_boot_device() != BOOT_DEVICE_UART)
disable_mcu_watchdog();
set_regdomain();
handle_reset_button();
#endif
pci_init();
return 0;

2
board/Marvell/dreamplug/dreamplug.c
View File

@ -163,7 +163,7 @@ void reset_phy(void)
char *eth0_name = "ethernet-controller@72000";
char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
char *eth1_name = "ethernet-controller@76000";
char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0";
char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
/* configure and initialize both PHY's */
mv_phy_88e1116_init(eth0_name, eth0_path);

2
board/Marvell/sheevaplug/MAINTAINERS
View File

@ -1,5 +1,5 @@
SHEEVAPLUG BOARD
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Tony Dinh <mibodhi@gmail.com>
S: Maintained
F: board/Marvell/sheevaplug/
F: include/configs/sheevaplug.h

2
board/davinci/da8xxevm/MAINTAINERS
View File

@ -8,7 +8,7 @@ F: configs/da850evm_nand_defconfig
F: configs/da850evm_direct_nor_defconfig
OMAPL138_LCDK BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: include/configs/omap1l38_lcdk.h
F: configs/omapl138_lcdk_defconfig

1
board/emulation/qemu-riscv/Kconfig
View File

@ -51,7 +51,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply E1000
imply NVME
imply PCI
imply DM_PCI
imply PCIE_ECAM_GENERIC
imply SCSI
imply DM_SCSI

1
board/freescale/common/Kconfig
View File

@ -4,6 +4,7 @@ config CHAIN_OF_TRUST
imply CMD_HASH if ARM
select FSL_CAAM
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE

10
board/sifive/unleashed/unleashed.c
View File

@ -6,6 +6,7 @@
* Anup Patel <anup.patel@wdc.com>
*/
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
@ -15,7 +16,6 @@
#include <linux/delay.h>
#include <misc.h>
#include <spl.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
/*
@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}

11
board/sifive/unmatched/unmatched.c
View File

@ -7,8 +7,8 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <asm/arch/cache.h>
#include <asm/sections.h>
void *board_fdt_blob_setup(void)
@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void)
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
enable_caches();
return 0;
}

1
board/socionext/developerbox/Kconfig
View File

@ -7,7 +7,6 @@ choice
config TARGET_DEVELOPERBOX
bool "Socionext DeveloperBox"
select PCI
select DM_PCI
select PCIE_ECAM_SYNQUACER
select SYS_DISABLE_DCACHE_OPS
select OF_BOARD_SETUP

2
board/ti/am43xx/MAINTAINERS
View File

@ -1,5 +1,5 @@
AM43XX BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am43xx/
F: include/configs/am43xx_evm.h

2
board/ti/am57xx/MAINTAINERS
View File

@ -1,5 +1,5 @@
AM57XX EVM
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am57xx/
F: include/configs/am57xx_evm.h

2
board/ti/am64x/MAINTAINERS
View File

@ -1,6 +1,6 @@
AM64x BOARD
M: Dave Gerlach <d-gerlach@ti.com>
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am64x/
F: include/configs/am64x_evm.h

32
board/ti/am64x/evm.c
View File

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
#include <spl.h>
#include <fdt_support.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <env.h>
@ -60,6 +61,37 @@ int board_fit_config_name_match(const char *name)
}
#endif
#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USB_STORAGE)
static int fixup_usb_boot(const void *fdt_blob)
{
int ret = 0;
switch (spl_boot_device()) {
case BOOT_DEVICE_USB:
/*
* If the boot mode is host, fixup the dr_mode to host
* before cdns3 bind takes place
*/
ret = fdt_find_and_setprop((void *)fdt_blob,
"/bus@f4000/cdns-usb@f900000/usb@f400000",
"dr_mode", "host", 5, 0);
if (ret)
printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__, ret);
fallthrough;
default:
break;
}
return ret;
}
void spl_perform_fixups(struct spl_image_info *spl_image)
{
fixup_usb_boot(spl_image->fdt_addr);
}
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
int do_board_detect(void)
{

2
board/ti/am65x/MAINTAINERS
View File

@ -1,5 +1,5 @@
AM65x BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am65x/
F: include/configs/am65x_evm.h

2
board/ti/dra7xx/MAINTAINERS
View File

@ -1,5 +1,5 @@
DRA7XX BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/dra7xx/
F: include/configs/dra7xx_evm.h

2
board/ti/j721e/MAINTAINERS
View File

@ -1,5 +1,5 @@
J721E BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/j721e
F: include/configs/j721e_evm.h

2
board/ti/omap5_uevm/MAINTAINERS
View File

@ -1,5 +1,5 @@
OMAP5_UEVM BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/omap5_uevm/
F: include/configs/omap5_uevm.h

2
board/ti/panda/MAINTAINERS
View File

@ -1,5 +1,5 @@
PANDA BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/panda/
F: include/configs/omap4_panda.h

2
board/ti/sdp4430/MAINTAINERS
View File

@ -1,5 +1,5 @@
SDP4430 BOARD
M: Lokesh Vutla <lokeshvutla@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/sdp4430/
F: include/configs/omap4_sdp4430.h

2
board/toradex/apalis-imx8/MAINTAINERS
View File

@ -6,5 +6,5 @@ F: arch/arm/dts/fsl-imx8-apalis.dts
F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
F: board/toradex/apalis-imx8/
F: configs/apalis-imx8_defconfig
F: doc/board/toradex/apalix-imx8.rst
F: doc/board/toradex/apalis-imx8.rst
F: include/configs/apalis-imx8.h

10
cmd/Kconfig
View File

@ -2411,4 +2411,14 @@ config CMD_UBIFS
help
UBIFS is a file system for flash devices which works on top of UBI.
config MMC_SPEED_MODE_SET
bool "set speed mode using mmc command"
depends on CMD_MMC
default n
help
Enable setting speed mode using mmc rescan and mmc dev commands.
The speed mode is provided as the last argument in these commands
and is indicated using the index from enum bus_mode in
include/mmc.h. A speed mode can be set only if it has already
been enabled in the device tree.
endmenu

52
cmd/mmc.c
View File

@ -120,7 +120,9 @@ static void print_mmcinfo(struct mmc *mmc)
}
}
}
static struct mmc *init_mmc_device(int dev, bool force_init)
static struct mmc *__init_mmc_device(int dev, bool force_init,
enum bus_mode speed_mode)
{
struct mmc *mmc;
mmc = find_mmc_device(dev);
@ -134,6 +136,10 @@ static struct mmc *init_mmc_device(int dev, bool force_init)
if (force_init)
mmc->has_init = 0;
if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET))
mmc->user_speed_mode = speed_mode;
if (mmc_init(mmc))
return NULL;
@ -145,6 +151,11 @@ static struct mmc *init_mmc_device(int dev, bool force_init)
return mmc;
}
static struct mmc *init_mmc_device(int dev, bool force_init)
{
return __init_mmc_device(dev, force_init, MMC_MODES_END);
}
static int do_mmcinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@ -482,8 +493,17 @@ static int do_mmc_rescan(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct mmc *mmc;
enum bus_mode speed_mode = MMC_MODES_END;
if (argc == 1) {
mmc = init_mmc_device(curr_device, true);
} else if (argc == 2) {
speed_mode = (int)dectoul(argv[1], NULL);
mmc = __init_mmc_device(curr_device, true, speed_mode);
} else {
return CMD_RET_USAGE;
}
mmc = init_mmc_device(curr_device, true);
if (!mmc)
return CMD_RET_FAILURE;
@ -515,11 +535,14 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag,
{
int dev, part = 0, ret;
struct mmc *mmc;
enum bus_mode speed_mode = MMC_MODES_END;
if (argc == 1) {
dev = curr_device;
mmc = init_mmc_device(dev, true);
} else if (argc == 2) {
dev = dectoul(argv[1], NULL);
dev = (int)dectoul(argv[1], NULL);
mmc = init_mmc_device(dev, true);
} else if (argc == 3) {
dev = (int)dectoul(argv[1], NULL);
part = (int)dectoul(argv[2], NULL);
@ -528,11 +551,21 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag,
PART_ACCESS_MASK);
return CMD_RET_FAILURE;
}
mmc = init_mmc_device(dev, true);
} else if (argc == 4) {
dev = (int)dectoul(argv[1], NULL);
part = (int)dectoul(argv[2], NULL);
if (part > PART_ACCESS_MASK) {
printf("#part_num shouldn't be larger than %d\n",
PART_ACCESS_MASK);
return CMD_RET_FAILURE;
}
speed_mode = (int)dectoul(argv[3], NULL);
mmc = __init_mmc_device(dev, true, speed_mode);
} else {
return CMD_RET_USAGE;
}
mmc = init_mmc_device(dev, true);
if (!mmc)
return CMD_RET_FAILURE;
@ -983,9 +1016,9 @@ static struct cmd_tbl cmd_mmc[] = {
#if CONFIG_IS_ENABLED(CMD_MMC_SWRITE)
U_BOOT_CMD_MKENT(swrite, 3, 0, do_mmc_sparse_write, "", ""),
#endif
U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""),
U_BOOT_CMD_MKENT(rescan, 2, 1, do_mmc_rescan, "", ""),
U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""),
U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""),
U_BOOT_CMD_MKENT(dev, 4, 0, do_mmc_dev, "", ""),
U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""),
@ -1042,9 +1075,12 @@ U_BOOT_CMD(
"mmc swrite addr blk#\n"
#endif
"mmc erase blk# cnt\n"
"mmc rescan\n"
"mmc rescan [mode]\n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc dev [dev] [part] [mode] - show or set current mmc device [partition] and set mode\n"
" - the required speed mode is passed as the index from the following list\n"
" [MMC_LEGACY, MMC_HS, SD_HS, MMC_HS_52, MMC_DDR_52, UHS_SDR12, UHS_SDR25,\n"
" UHS_SDR50, UHS_DDR50, UHS_SDR104, MMC_HS_200, MMC_HS_400, MMC_HS_400_ES]\n"
"mmc list - lists available devices\n"
"mmc wp - power on write protect boot partitions\n"
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)

1
cmd/mvebu/Kconfig
View File

@ -3,6 +3,7 @@ depends on ARCH_MVEBU
config CMD_MVEBU_BUBT
bool "bubt"
select SHA256 if ARMADA_3700
help
bubt - Burn a u-boot image to flash
For details about bubt command please see the documentation

9
cmd/nvedit_efi.c
View File

@ -187,8 +187,8 @@ static int efi_dump_var_all(int argc, char *const argv[],
var_name16[0] = 0;
for (;;) {
size = buf_size;
ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16,
&guid));
ret = efi_get_next_variable_name_int(&size, var_name16,
&guid);
if (ret == EFI_NOT_FOUND)
break;
if (ret == EFI_BUFFER_TOO_SMALL) {
@ -199,9 +199,8 @@ static int efi_dump_var_all(int argc, char *const argv[],
return CMD_RET_FAILURE;
}
var_name16 = p;
ret = EFI_CALL(efi_get_next_variable_name(&size,
var_name16,
&guid));
ret = efi_get_next_variable_name_int(&size, var_name16,
&guid);
}
if (ret != EFI_SUCCESS) {
free(var_name16);

1
common/Kconfig
View File

@ -557,7 +557,6 @@ config ID_EEPROM
config PCI_INIT_R
bool "Enumerate PCI buses during init"
depends on PCI
default y if !DM_PCI
help
With this option U-Boot will call pci_init() soon after relocation,
which will enumerate PCI buses. This is needed, for instance, in the

31
common/Kconfig.boot
View File

@ -11,8 +11,10 @@ config ANDROID_BOOT_IMAGE
config FIT
bool "Support Flattened Image Tree"
select HASH
select MD5
select SHA1
imply SHA256
help
This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
@ -35,32 +37,6 @@ config FIT_EXTERNAL_OFFSET
could be put in the hole between data payload and fit image
header, such as CSF data on i.MX platform.
config FIT_SHA256
bool "Support SHA256 checksum of FIT image contents"
default y
select SHA256
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
the image contents have not been corrupted.
config FIT_SHA384
bool "Support SHA384 checksum of FIT image contents"
select SHA384
help
Enable this to support SHA384 checksum of FIT image contents. A
SHA384 checksum is a 384-bit (48-byte) hash value used to check that
the image contents have not been corrupted. Use this for the highest
security.
config FIT_SHA512
bool "Support SHA512 checksum of FIT image contents"
select SHA512
help
Enable this to support SHA512 checksum of FIT image contents. A
SHA512 checksum is a 512-bit (64-byte) hash value used to check that
the image contents have not been corrupted.
config FIT_FULL_CHECK
bool "Do a full check of the FIT before using it"
default y
@ -158,6 +134,7 @@ if SPL
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
depends on SPL
select SPL_HASH
select SPL_OF_LIBFDT
config SPL_FIT_PRINT
@ -182,7 +159,7 @@ config SPL_FIT_SIGNATURE
select FIT_SIGNATURE
select SPL_FIT
select SPL_CRYPTO
select SPL_HASH_SUPPORT
select SPL_HASH
imply SPL_RSA
imply SPL_RSA_VERIFY
select SPL_IMAGE_SIGN_INFO

4
common/Makefile
View File

@ -8,7 +8,6 @@ ifndef CONFIG_SPL_BUILD
obj-y += init/
obj-y += main.o
obj-y += exports.o
obj-$(CONFIG_HASH) += hash.o
obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
@ -66,8 +65,6 @@ ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_DFU
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
endif
obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o
obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
obj-$(CONFIG_SPL_NET) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
@ -105,6 +102,7 @@ endif
endif
obj-y += image.o
obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o
obj-$(CONFIG_ANDROID_AB) += android_ab.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o

4
common/board_r.c
View File

@ -114,7 +114,7 @@ static int initr_reloc(void)
return 0;
}
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
/*
* Some of these functions are needed purely because the functions they
* call return void. If we change them to return 0, these stubs can go away.
@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
initr_caches,
/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
* A temporary mapping of IFC high region is since removed,

13
common/hash.c
View File

@ -207,12 +207,25 @@ static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf,
return 0;
}
#ifdef USE_HOSTCC
# define I_WANT_MD5 1
#else
# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5)
#endif
/*
* These are the hash algorithms we support. If we have hardware acceleration
* is enable we will use that, otherwise a software version of the algorithm.
* Note that algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
#if I_WANT_MD5
{
.name = "md5",
.digest_size = MD5_SUM_LEN,
.chunk_size = CHUNKSZ_MD5,
.hash_func_ws = md5_wd,
},
#endif
#ifdef CONFIG_SHA1
{
.name = "sha1",

36
common/image-fit.c
View File

@ -1215,7 +1215,7 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
* 0, on success
* -1, when algo is unsupported
*/
int calculate_hash(const void *data, int data_len, const char *algo,
int calculate_hash(const void *data, int data_len, const char *name,
uint8_t *value, int *value_len)
{
#if !defined(USE_HOSTCC) && defined(CONFIG_DM_HASH)
@ -1243,35 +1243,19 @@ int calculate_hash(const void *data, int data_len, const char *algo,
*value_len = hash_algo_digest_size(hash_algo);
#else
if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
*((uint32_t *)value) = crc32_wd(0, data, data_len,
CHUNKSZ_CRC32);
*((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
*value_len = 4;
} else if (CONFIG_IS_ENABLED(SHA1) && strcmp(algo, "sha1") == 0) {
sha1_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA1);
*value_len = 20;
} else if (CONFIG_IS_ENABLED(SHA256) && strcmp(algo, "sha256") == 0) {
sha256_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA256);
*value_len = SHA256_SUM_LEN;
} else if (CONFIG_IS_ENABLED(SHA384) && strcmp(algo, "sha384") == 0) {
sha384_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA384);
*value_len = SHA384_SUM_LEN;
} else if (CONFIG_IS_ENABLED(SHA512) && strcmp(algo, "sha512") == 0) {
sha512_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA512);
*value_len = SHA512_SUM_LEN;
} else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
*value_len = 16;
} else {
struct hash_algo *algo;
int ret;
ret = hash_lookup_algo(name, &algo);
if (ret < 0) {
debug("Unsupported hash alogrithm\n");
return -1;
}
algo->hash_func_ws(data, data_len, value, algo->chunk_size);
*value_len = algo->digest_size;
#endif
return 0;
}

23
common/image-sig.c
View File

@ -51,19 +51,6 @@ struct checksum_algo checksum_algos[] = {
};
struct padding_algo padding_algos[] = {
{
.name = "pkcs-1.5",
.verify = padding_pkcs_15_verify,
},
#ifdef CONFIG_FIT_RSASSA_PSS
{
.name = "pss",
.verify = padding_pss_verify,
}
#endif /* CONFIG_FIT_RSASSA_PSS */
};
struct checksum_algo *image_get_checksum_algo(const char *full_name)
{
int i;
@ -129,14 +116,16 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name)
struct padding_algo *image_get_padding_algo(const char *name)
{
int i;
struct padding_algo *padding, *end;
if (!name)
return NULL;
for (i = 0; i < ARRAY_SIZE(padding_algos); i++) {
if (!strcmp(padding_algos[i].name, name))
return &padding_algos[i];
padding = ll_entry_start(struct padding_algo, paddings);
end = ll_entry_end(struct padding_algo, paddings);
for (; padding < end; padding++) {
if (!strcmp(padding->name, name))
return padding;
}
return NULL;

65
common/spl/Kconfig
View File

@ -439,48 +439,6 @@ config SPL_MD5
applications where images may be changed maliciously, you should
consider SHA256 or SHA384.
config SPL_FIT_SHA1
bool "Support SHA1"
depends on SPL_FIT
select SHA1
help
Enable this to support SHA1 in FIT images within SPL. A SHA1
checksum is a 160-bit (20-byte) hash value used to check that the
image contents have not been corrupted or maliciously altered.
While SHA1 is fairly secure it is coming to the end of its life
due to the expanding computing power available to brute-force
attacks. For more security, consider SHA256 or SHA384.
config SPL_FIT_SHA256
bool "Support SHA256"
depends on SPL_FIT
select SHA256
help
Enable this to support SHA256 in FIT images within SPL. A SHA256
checksum is a 256-bit (32-byte) hash value used to check that the
image contents have not been corrupted.
config SPL_FIT_SHA384
bool "Support SHA384"
depends on SPL_FIT
select SHA384
select SHA512_ALGO
help
Enable this to support SHA384 in FIT images within SPL. A SHA384
checksum is a 384-bit (48-byte) hash value used to check that the
image contents have not been corrupted. Use this for the highest
security.
config SPL_FIT_SHA512
bool "Support SHA512"
depends on SPL_FIT
select SHA512
select SHA512_ALGO
help
Enable this to support SHA512 in FIT images within SPL. A SHA512
checksum is a 512-bit (64-byte) hash value used to check that the
image contents have not been corrupted.
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
@ -519,27 +477,6 @@ config SPL_CRYPTO
this option to build the drivers in drivers/crypto as part of an
SPL build.
config SPL_HASH_SUPPORT
bool "Support hashing drivers"
select SHA1
select SHA256
help
Enable hashing drivers in SPL. These drivers can be used to
accelerate secure boot processing in secure applications. Enable
this option to build system-specific drivers for hash acceleration
as part of an SPL build.
config TPL_HASH_SUPPORT
bool "Support hashing drivers in TPL"
depends on TPL
select SHA1
select SHA256
help
Enable hashing drivers in SPL. These drivers can be used to
accelerate secure boot processing in secure applications. Enable
this option to build system-specific drivers for hash acceleration
as part of an SPL build.
config SPL_DMA
bool "Support DMA drivers"
help
@ -1228,7 +1165,7 @@ config SPL_USB_ETHER
config SPL_DFU
bool "Support DFU (Device Firmware Upgrade)"
select SPL_HASH_SUPPORT
select SPL_HASH
select SPL_DFU_NO_RESET
depends on SPL_RAM_SUPPORT
help

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