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global: Move remaining CONFIG_SYS_* to CFG_SYS_*

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The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
2022-11-16 13:10:41 -05:00
parent a322afc9f9
commit 65cc0e2a65
744 changed files with 5915 additions and 5914 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@@ -77,10 +77,10 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
SCCR_TSECCM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
SCCR_TSEC1CM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
SCCR_TSEC2CM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
@@ -92,10 +92,10 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
SCCR_USBMPHCM |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
SCCR_USBDRCM |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
SCCR_SATACM |
#endif
0;
@@ -115,11 +115,11 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
(CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
@@ -130,11 +130,11 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
(CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
@@ -175,26 +175,26 @@ void cpu_init_f (volatile immap_t * im)
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
#ifdef CFG_SYS_SICRH
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
&im->sysconf.sicrh);
#else
__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
__raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
#endif
#endif
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#ifdef CFG_SYS_SICRL
__raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
#endif
#ifdef CONFIG_SYS_GPR1
__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
#ifdef CFG_SYS_GPR1
__raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#ifdef CFG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#ifdef CFG_SYS_OBIR /* Output buffer impedance register */
__raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
#endif
#if !defined(CONFIG_PINCTRL)

14
arch/powerpc/cpu/mpc83xx/spd_sdram.c
View File

@@ -59,9 +59,9 @@ void board_add_ram_info(int use_default)
printf(", %s MHz)", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
#endif
}
@@ -204,12 +204,12 @@ long int spd_sdram()
return 0;
}
#ifdef CONFIG_SYS_DDRCDR_VALUE
#ifdef CFG_SYS_DDRCDR_VALUE
/*
* Adjust DDR II IO voltage biasing. It just makes it work.
*/
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
}
udelay(50000);
#endif
@@ -693,7 +693,7 @@ long int spd_sdram()
ddr->sdram_mode =
(0
| (1 << (16 + 10)) /* DQS Differential disable */
#ifdef CONFIG_SYS_DDR_MODE_WEAK
#ifdef CFG_SYS_DDR_MODE_WEAK
| (1 << (16 + 1)) /* weak driver (~60%) */
#endif
| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
@@ -767,8 +767,8 @@ long int spd_sdram()
debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
}
#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);

8
arch/powerpc/cpu/mpc83xx/spl_minimal.c
View File

@@ -54,12 +54,12 @@ void cpu_init_f (volatile immap_t * im)
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
#ifdef CONFIG_SYS_DDRCDR
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
#ifdef CFG_SYS_DDRCDR
im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
#ifdef CONFIG_SYS_OBIR
im->sysconf.obir = CONFIG_SYS_OBIR;
#ifdef CFG_SYS_OBIR
im->sysconf.obir = CFG_SYS_OBIR;
#endif
/*

48
arch/powerpc/cpu/mpc83xx/start.S
View File

@@ -246,7 +246,7 @@ in_flash:
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
@@ -486,7 +486,7 @@ init_e300_core: /* time t 10 */
#if defined(CONFIG_WATCHDOG)
/* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
lis r4, CONFIG_SYS_WATCHDOG_VALUE
lis r4, CFG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
@@ -1048,10 +1048,10 @@ trap_init:
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
dcbz r0, r3
@@ -1070,10 +1070,10 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
dcbi r0, r3
@@ -1122,14 +1122,14 @@ map_flash_by_law1:
* LBIU Local Access Widow 0 will not cover this memory space. So, we
* need another window to map in it.
*/
lis r4, (CONFIG_SYS_FLASH_BASE)@h
ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
lis r4, (CFG_SYS_FLASH_BASE)@h
ori r4, r4, (CFG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */
/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
li r5, CONFIG_SYS_FLASH_SIZE
li r5, CFG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
@@ -1150,24 +1150,24 @@ remap_flash_by_law0:
lwz r4, BR0(r3)
li r5, 0x7FFF
and r4, r4, r5
lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h
ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4
stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3)
lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1)
or r4, r4, r5
stw r4, OR0(r3)
lis r4, (CONFIG_SYS_FLASH_BASE)@h
ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
lis r4, (CFG_SYS_FLASH_BASE)@h
ori r4, r4, (CFG_SYS_FLASH_BASE)@l
stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */
/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
li r5, CONFIG_SYS_FLASH_SIZE
li r5, CFG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b

8
arch/powerpc/cpu/mpc83xx/sysio/sysio.h
View File

@@ -1,7 +1,7 @@
#ifdef CONFIG_ARCH_MPC8308
#ifndef CONFIG_SYS_SICRL
#define CONFIG_SYS_SICRL (\
#ifndef CFG_SYS_SICRL
#define CFG_SYS_SICRL (\
CONFIG_SICRL_SPI |\
CONFIG_SICRL_UART |\
CONFIG_SICRL_IRQ |\
@@ -10,8 +10,8 @@
)
#endif
#ifndef CONFIG_SYS_SICRH
#define CONFIG_SYS_SICRH (\
#ifndef CFG_SYS_SICRH
#define CFG_SYS_SICRH (\
CONFIG_SICRH_ESDHC_A |\
CONFIG_SICRH_ESDHC_B |\
CONFIG_SICRH_ESDHC_C |\

2
arch/powerpc/cpu/mpc85xx/b4860_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),

4
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@@ -23,7 +23,7 @@
*/
static void check_erratum_a4849(uint32_t svr)
{
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
@@ -120,7 +120,7 @@ static void check_erratum_a4580(uint32_t svr)
*/
static void check_erratum_a007212(void)
{
u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
if (in_be32(plldgdcr) & 0x1fe) {
/* check if PLL ratio is set by workaround */

18
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@@ -417,7 +417,7 @@ void print_reginfo(void)
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
!defined(CFG_SYS_INIT_L2_ADDR)
int dram_init(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
@@ -486,7 +486,7 @@ int dram_init(void)
#endif /* CONFIG_SYS_RAMBOOT */
#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
#if CONFIG_POST & CFG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
@@ -591,7 +591,7 @@ static void dump_spd_ddr_reg(void)
/* invalid the TLBs for DDR and setup new ones to cover p_addr */
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
{
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
int ddr_esel;
@@ -624,8 +624,8 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
!defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
test_cap = p_size;
#else
test_cap = gd->ram_size;
@@ -635,7 +635,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
if (reset_tlb(p_addr, p_size, phys_offset) == -1)
return -1;
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
*vstart = CFG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size;
printf("Testing 0x%08llx - 0x%08llx\n",
(u64)(*vstart) + (*phys_offset),
@@ -651,13 +651,13 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
*vstart = CFG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
*phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
!defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
puts("Cannot test more than ");
print_size(CONFIG_MAX_MEM_MAPPED,

52
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@@ -165,7 +165,7 @@ void disable_cpc_sram(void)
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
if (law.index == -1) {
printf("\nFatal error happened\n");
@@ -315,15 +315,15 @@ void fsl_erratum_a007212_workaround(void)
{
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
#endif
#endif
/*
@@ -378,7 +378,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#ifdef CFG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
@@ -403,7 +403,7 @@ ulong cpu_init_f(void)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
/* Disable the LAW created for NOR flash by the PBI commands */
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
law = find_law(CFG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
@@ -430,7 +430,7 @@ ulong cpu_init_f(void)
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#ifdef CFG_SYS_DCSRBAR_PHYS
/* set DCSRCR so that DCSR space is 1G */
setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
in_be32(&gur->dcsrcr);
@@ -533,7 +533,7 @@ int l2cache_init(void)
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
if (cache_ctl & MPC85xx_L2CTL_L2E) {
/* Clear L2 SRAM memory-mapped base address */
out_be32(&l2cache->l2srbar0, 0x0);
@@ -590,15 +590,15 @@ int l2cache_init(void)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
u32 l2srbar = l2cache->l2srbar0;
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
&& l2srbar >= CFG_SYS_FLASH_BASE) {
l2srbar = CFG_SYS_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
#endif /* CFG_SYS_INIT_L2_ADDR */
puts("\n");
} else {
asm("msync;isync");
@@ -625,9 +625,9 @@ int l2cache_init(void)
#endif
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
;
print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
@@ -656,7 +656,7 @@ skip_l2:
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
#ifdef CFG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -763,13 +763,13 @@ int cpu_init_r(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
int i;
__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
__be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
for (i = 0; i < 12; i++) {
p += i + (i > 5 ? 11 : 0);
out_be32(p, 0x2);
}
p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
out_be32(p, 0x34);
}
#endif
@@ -799,18 +799,18 @@ int cpu_init_r(void)
{
if (SVR_MAJ(svr) < 3) {
void *p;
p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
p = (void *)CFG_SYS_DCSRBAR + 0x20520;
setbits_be32(p, 1 << (31 - 14));
}
}
#endif
#ifdef CONFIG_SYS_LBC_LCRR
#ifdef CFG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing
* speed for NOR flash.
*/
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
@@ -850,7 +850,7 @@ int cpu_init_r(void)
*/
if (IS_SVR_REV(get_svr(), 1, 0)) {
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
(CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
setbits_be32(&dcfg->ecccr1,
(DCSR_DCFG_ECC_DISABLE_USB1 |
DCSR_DCFG_ECC_DISABLE_USB2));

22
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View File

@@ -17,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_A003399_NOR_WORKAROUND
void setup_ifc(void)
{
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
/*
* Adjust the TLB we were running out of to match the phys addr of the
* chip select we are adjusting and will return to.
*/
flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
@@ -52,7 +52,7 @@ void setup_ifc(void)
*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's physical address is going to change as
* CONFIG_SYS_FLASH_BASE_PHYS.
* CFG_SYS_FLASH_BASE_PHYS.
*/
_mas0 = MAS0_TLBSEL(1) |
MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
@@ -72,9 +72,9 @@ void setup_ifc(void)
#endif
/* Change flash's physical address */
ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0);
ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0);
ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
return;
}
@@ -101,7 +101,7 @@ void cpu_init_early_f(void *fdt)
#ifdef CONFIG_ARCH_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
@@ -109,9 +109,9 @@ void cpu_init_early_f(void *fdt)
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
write_tlb(mas0, mas1, mas2, mas3, mas7);

32
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@@ -144,14 +144,14 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_SPL_MMC_BOOT
off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
CONFIG_SYS_MMC_U_BOOT_SIZE);
off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START,
CFG_SYS_MMC_U_BOOT_SIZE);
if (off < 0)
printf("Failed to reserve memory for SD deep sleep: %s\n",
fdt_strerror(off));
#elif defined(CONFIG_SPL_SPI_BOOT)
off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START,
CFG_SYS_SPI_FLASH_U_BOOT_SIZE);
if (off < 0)
printf("Failed to reserve memory for SPI deep sleep: %s\n",
fdt_strerror(off));
@@ -448,7 +448,7 @@ void fdt_add_enet_stashing(void *fdt)
static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
unsigned long freq)
{
phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS;
int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
@@ -679,17 +679,17 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
ft_fixup_dpaa_clks(blob);
#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
#if defined(CFG_SYS_BMAN_MEM_PHYS)
fdt_portal(blob, "fsl,bman-portal", "bman-portals",
(u64)CONFIG_SYS_BMAN_MEM_PHYS,
CONFIG_SYS_BMAN_MEM_SIZE);
(u64)CFG_SYS_BMAN_MEM_PHYS,
CFG_SYS_BMAN_MEM_SIZE);
fdt_fixup_bportals(blob);
#endif
#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
#if defined(CFG_SYS_QMAN_MEM_PHYS)
fdt_portal(blob, "fsl,qman-portal", "qman-portals",
(u64)CONFIG_SYS_QMAN_MEM_PHYS,
CONFIG_SYS_QMAN_MEM_SIZE);
(u64)CFG_SYS_QMAN_MEM_PHYS,
CFG_SYS_QMAN_MEM_SIZE);
fdt_fixup_qportals(blob);
#endif
@@ -737,7 +737,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
* beginning of CCSR.
*/
#define CCSR_VIRT_TO_PHYS(x) \
(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
(CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
{
@@ -783,8 +783,8 @@ int ft_verify_fdt(void *fdt)
return 0;
}
if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
if (addr != CFG_SYS_CCSRBAR_PHYS) {
msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr);
/* No point in checking anything else */
return 0;
}
@@ -818,12 +818,12 @@ int ft_verify_fdt(void *fdt)
* the 'reg' property to be wrong, so check it here. For now, we
* only check for "fsl,elbc" nodes.
*/
#ifdef CONFIG_SYS_LBC_ADDR
#ifdef CFG_SYS_LBC_ADDR
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
if (off > 0) {
const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
if (reg) {
uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
addr = fdt_translate_address(fdt, off, reg);
if (uaddr != addr) {

2
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
View File

@@ -203,7 +203,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
(struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR);
u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
u32 bc_status, fc_status, dc_status, pll_sr2;
serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;

14
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@@ -264,9 +264,9 @@ void serdes_reset_rx(enum srds_prtcl device)
}
#endif
#ifndef CONFIG_SYS_DCSRBAR_PHYS
#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
#define CONFIG_SYS_DCSRBAR 0x80000000
#ifndef CFG_SYS_DCSRBAR_PHYS
#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
#define CFG_SYS_DCSRBAR 0x80000000
#define __DCSR_NOT_DEFINED_BY_CONFIG
#endif
@@ -315,16 +315,16 @@ static void enable_bank(ccsr_gur_t *gur, int bank)
*/
{
#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS);
int law_index;
if (law.index == -1)
law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
else
set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_DCSR);
#endif
u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
out_be32(p, rcw5);
#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
if (law.index == -1)

2
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),

2
arch/powerpc/cpu/mpc85xx/p3041_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),

2
arch/powerpc/cpu/mpc85xx/p4080_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO( 1, 2, 1, 0),
SET_QP_INFO( 3, 4, 2, 1),

2
arch/powerpc/cpu/mpc85xx/p5040_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),

4
arch/powerpc/cpu/mpc85xx/release.S
View File

@@ -276,8 +276,8 @@ __secondary_start_page:
mtspr SPRN_L2CSR1,r3
#endif
lis r3,CONFIG_SYS_INIT_L2CSR0@h
ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
lis r3,CFG_SYS_INIT_L2CSR0@h
ori r3,r3,CFG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
2:

42
arch/powerpc/cpu/mpc85xx/speed.c
View File

@@ -218,22 +218,22 @@ void get_sys_info(sys_info_t *sys_info)
#ifndef CONFIG_PME_PLAT_CLK_DIV
switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
case 1:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
break;
case 2:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2;
break;
case 3:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3;
break;
case 4:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4;
break;
case 6:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2;
break;
case 7:
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3;
break;
default:
printf("Error: Unknown PME clock select!\n");
@@ -243,7 +243,7 @@ void get_sys_info(sys_info_t *sys_info)
}
#else
sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
#endif
#endif
@@ -380,25 +380,25 @@ void get_sys_info(sys_info_t *sys_info)
#ifndef CONFIG_FM_PLAT_CLK_DIV
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
case 1:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
break;
case 2:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2;
break;
case 3:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3;
break;
case 4:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4;
break;
case 5:
sys_info->freq_fman[0] = sys_info->freq_systembus;
break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2;
break;
case 7:
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3;
break;
default:
printf("Error: Unknown FMan1 clock select!\n");
@@ -407,31 +407,31 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
#if (CFG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#ifdef CFG_SYS_FM2_CLK
#define FM2_CLK_SEL 0x00000038
#define FM2_CLK_SHIFT 3
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
case 1:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1];
break;
case 2:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2;
break;
case 3:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3;
break;
case 4:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4;
break;
case 5:
sys_info->freq_fman[1] = sys_info->freq_systembus;
break;
case 6:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2;
break;
case 7:
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3;
break;
default:
printf("Error: Unknown FMan2 clock select!\n");
@@ -442,7 +442,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#endif /* CFG_SYS_NUM_FMAN == 2 */
#else
sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK;
#endif
#endif

4
arch/powerpc/cpu/mpc85xx/spl_minimal.c
View File

@@ -14,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR;
ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
#ifdef CFG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
/* set MBECCDIS=1, SBECCDIS=1 */
out_be32(&l2cache->l2errdis,

130
arch/powerpc/cpu/mpc85xx/start.S
View File

@@ -128,7 +128,7 @@ bootsect:
.Lconf_pair_start:
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
.long CONFIG_SYS_INIT_L2_ADDR
.long CFG_SYS_INIT_L2_ADDR
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
@@ -428,12 +428,12 @@ l2_disabled:
mtspr SPRN_BUCSR,r0
#endif
#if defined(CONFIG_SYS_INIT_DBCR)
#if defined(CFG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr DBSR,r1 /* Clear all status bits */
lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
ori r0,r0,CONFIG_SYS_INIT_DBCR@l
lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
ori r0,r0,CFG_SYS_INIT_DBCR@l
mtspr DBCR0,r0
#endif
@@ -573,34 +573,34 @@ nexti: mflr r1 /* R1 = our PC */
* As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
* long-term TLBs, so we use TLB0 here.
*/
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS)
#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW)
#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined."
#endif
create_ccsr_new_tlb:
/*
* Create a TLB for the new location of CCSR. Register R8 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
* for the virtual address of this TLB (CFG_SYS_CCSRBAR).
*/
lis r8, CONFIG_SYS_CCSRBAR@h
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
lis r8, CFG_SYS_CCSRBAR@h
ori r8, r8, CFG_SYS_CCSRBAR@l
lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
CFG_SYS_CCSRBAR_PHYS_HIGH, r3
/*
* Create a TLB for the current location of CCSR. Register R9 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
* for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
create_tlb0_entry 1, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
0, r3 /* The default CCSR address is always a 32-bit number */
@@ -634,7 +634,7 @@ infinite_debug_loop:
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
@@ -644,10 +644,10 @@ create_temp_law:
* On CoreNet systems, we create the temporary LAW using a special LAW
* target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
*/
lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRBAR_LAWAR@h
ori r2, r2, CCSRBAR_LAWAR@l
@@ -683,10 +683,10 @@ read_old_ccsrbar:
* instruction.
*/
write_new_ccsrbar:
lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRAR_C@h
ori r2, r2, CCSRAR_C@l
@@ -723,9 +723,9 @@ write_new_ccsrbar:
lwz r0, 0(r9)
isync
/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
(CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */
#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
(CFG_SYS_CCSRBAR_PHYS_LOW >> 12))
/* Write the new value to CCSRBAR. */
lis r0, CCSRBAR_PHYS_RS12@h
@@ -752,10 +752,10 @@ write_new_ccsrbar:
/* Delete the temporary TLBs */
delete_temp_tlbs:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
create_ccsr_l2_tlb:
@@ -765,14 +765,14 @@ create_ccsr_l2_tlb:
*/
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
CFG_SYS_CCSRBAR_PHYS_HIGH, r3
enable_l2_cluster_l2:
/* enable L2 cache */
lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h
ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l
li r4, 33 /* stash id */
stw r4, 4(r3)
lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -813,7 +813,7 @@ enable_l2_cluster_l2:
beq 1b
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
/*
@@ -863,7 +863,7 @@ delete_ccsr_l2_tlb:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
@@ -884,13 +884,13 @@ delete_ccsr_l2_tlb:
rlwimi r0, r8, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
lis r7, CONFIG_SYS_CCSRBAR@h
ori r7, r7, CONFIG_SYS_CCSRBAR@l
lis r7, CFG_SYS_CCSRBAR@h
ori r7, r7, CFG_SYS_CCSRBAR@l
ori r2, r7, MAS2_I|MAS2_G
lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h
ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
@@ -1132,7 +1132,7 @@ create_init_ram_area:
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
/*
@@ -1148,7 +1148,7 @@ create_init_ram_area:
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
@@ -1164,19 +1164,19 @@ create_init_ram_area:
#endif
/* create a temp mapping in AS=1 to the stack */
#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
CONFIG_SYS_INIT_RAM_ADDR, 0, \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
CFG_SYS_INIT_RAM_ADDR, 0, \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
#else
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
CONFIG_SYS_INIT_RAM_ADDR, 0, \
CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
CFG_SYS_INIT_RAM_ADDR, 0, \
CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
@@ -1194,8 +1194,8 @@ switch_as:
/* Allocate Initial RAM in data cache.
*/
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
lis r3,CFG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l
mfspr r2, L1CFG0
andi. r2, r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
@@ -1230,11 +1230,11 @@ switch_as:
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
lis r3,(CFG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
@@ -1243,8 +1243,8 @@ _start_cont:
#endif
/* End of RAM */
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
lis r4,(CFG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l
li r0,0
@@ -1826,8 +1826,8 @@ trap_init:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
@@ -1844,8 +1844,8 @@ unlock_ram_in_cache:
sync
/* Invalidate the TLB entries for the cache */
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
lis r3,CFG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3

2
arch/powerpc/cpu/mpc85xx/t1024_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),

2
arch/powerpc/cpu/mpc85xx/t1040_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),

2
arch/powerpc/cpu/mpc85xx/t2080_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),

2
arch/powerpc/cpu/mpc85xx/t4240_ids.c
View File

@@ -8,7 +8,7 @@
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),

8
arch/powerpc/cpu/mpc85xx/tlb.c
View File

@@ -302,7 +302,7 @@ uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
unsigned int memsize_in_meg)
{
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
u64 size;
@@ -324,13 +324,13 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
return
setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
/* Invalidate the DDR TLBs for the requested size */
void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
@@ -351,7 +351,7 @@ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
void clear_ddr_tlbs(unsigned int memsize_in_meg)
{
clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}

4
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
View File

@@ -64,7 +64,7 @@ SECTIONS
_end = .;
#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
mmc_u_boot_offs = .;
#endif
#endif
@@ -101,7 +101,7 @@ SECTIONS
.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
mmc_u_boot_offs = .;
#endif
#endif

4
arch/powerpc/cpu/mpc8xx/start.S
View File

@@ -141,8 +141,8 @@ in_flash:
mtspr DER, r2
/* set up the stack on top of internal DPRAM */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h
ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l
stw r0, -4(r3)
stw r0, -8(r3)
addi r1, r3, -8

8
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
View File

@@ -230,7 +230,7 @@ static int pamu_config_spaace(uint32_t liodn,
int pamu_init(void)
{
u32 base_addr = CONFIG_SYS_PAMU_ADDR;
u32 base_addr = CFG_SYS_PAMU_ADDR;
struct ccsr_pamu *regs;
u32 i = 0;
u64 ppaact_phys, ppaact_lim, ppaact_size;
@@ -292,7 +292,7 @@ int pamu_init(void)
void pamu_enable(void)
{
u32 i = 0;
u32 base_addr = CONFIG_SYS_PAMU_ADDR;
u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
@@ -304,7 +304,7 @@ void pamu_enable(void)
void pamu_reset(void)
{
u32 i = 0;
u32 base_addr = CONFIG_SYS_PAMU_ADDR;
u32 base_addr = CFG_SYS_PAMU_ADDR;
struct ccsr_pamu *regs;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
@@ -328,7 +328,7 @@ void pamu_reset(void)
void pamu_disable(void)
{
u32 i = 0;
u32 base_addr = CONFIG_SYS_PAMU_ADDR;
u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {

8
arch/powerpc/cpu/mpc8xxx/pamu_table.c
View File

@@ -21,17 +21,17 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
#ifdef CONFIG_SYS_FLASH_BASE_PHYS
#ifdef CFG_SYS_FLASH_BASE_PHYS
tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
(uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS);
tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
#endif
#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
(uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR);
tbl->size[i] = 256 * 1024; /* 256K CPC flash */
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;