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Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.

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All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c.  In a subsequent patch, this will be
utilized by the 85xx ports as well.

Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.

Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.

Fixed a u16 vendor compiler warning in AHCI driver too.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Ed Swarthout
2007-08-02 14:09:49 -05:00
committed by Wolfgang Denk
parent 63e22764d2
commit 63cec5814f
11 changed files with 493 additions and 406 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
cpu/mpc86xx/Makefile
View File

@@ -1,4 +1,5 @@
#
# Copyright 2007 Freescale Semiconductor, Inc.
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,X.Xiao@motorola.com
#
@@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a
START = start.o #resetvec.o
SOBJS = cache.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
pci.o pcie_indirect.o spd_sdram.o
spd_sdram.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

146
cpu/mpc86xx/pci.c
View File

@@ -1,146 +0,0 @@
/*
* Copyright (C) Freescale Semiconductor,Inc.
* 2005, 2006. All rights reserved.
*
* Ed Swarthout (ed.swarthout@freescale.com)
* Jason Jin (Jason.jin@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCIE Configuration space access support for PCIE Bridge
*/
#include <common.h>
#include <pci.h>
#if defined(CONFIG_PCI)
void
pci_mpc86xx_init(struct pci_controller *hose)
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_pex_t *pcie1 = &immap->im_pex1;
u16 temp16;
u32 temp32;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
uint pcie1_host = (host1_agent == 2) || (host1_agent == 3);
uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
io_sel == 7 || io_sel == 0xf)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
printf("PCI-EXPRESS 1: Configured as %s \n",
pcie1_agent ? "Agent" : "Host");
if (pcie1_agent)
return; /*Don't scan bus when configured as agent */
printf(" Scanning PCIE bus");
debug("0x%08x=0x%08x ",
&pcie1->pme_msg_det,
pcie1->pme_msg_det);
if (pcie1->pme_msg_det) {
pcie1->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pcie1->pme_msg_det);
}
debug("\n");
} else {
printf("PCI-EXPRESS 1 disabled!\n");
return;
}
/*
* Set first_bus=0 only skipped B0:D0:F0 which is
* a reserved device in M1575, but make it easy for
* most of the scan process.
*/
hose->first_busno = 0x00;
hose->last_busno = 0xfe;
pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
pci_hose_read_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_hose_write_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
pci_hose_write_config_byte(hose,
PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
&temp32);
temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
temp32);
pcie1->powar1 = 0;
pcie1->powar2 = 0;
pcie1->piwar1 = 0;
pcie1->piwar1 = 0;
pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcie1->powar1 = 0x8004401c; /* 512M MEM space */
pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcie1->potear1 = 0x00000000;
pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcie1->powar2 = 0x80088017; /* 16M IO space */
pcie1->potar2 = 0x00000000;
pcie1->potear2 = 0x00000000;
pcie1->pitar1 = 0x00000000;
pcie1->piwbar1 = 0x00000000;
/* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */
pcie1->piwar1 = 0xa0f5501e;
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
pci_set_region(hose->regions + 1,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 2,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno);
debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno);
printf("....PCIE1 scan & enumeration done\n");
}
#endif /* CONFIG_PCI */

199
cpu/mpc86xx/pcie_indirect.c
View File

@@ -1,199 +0,0 @@
/*
* Support for indirect PCI bridges.
*
* Copyright (c) Freescale Semiconductor, Inc.
* 2006. All rights reserved.
*
* Jason Jin <Jason.jin@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* partly derived from
* arch/powerpc/platforms/86xx/mpc86xx_pcie.c
*/
#include <common.h>
#ifdef CONFIG_PCI
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#define PCI_CFG_OUT out_be32
#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
static int
indirect_read_config_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
int len,
u32 *val)
{
int bus = PCI_BUS(dev);
volatile unsigned char *cfg_data;
u32 temp;
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
cfg_data = hose->cfg_data;
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
switch (len) {
case 1:
*val = (temp >> (((offset & 3)) * 8)) & 0xff;
break;
case 2:
*val = (temp >> (((offset & 3)) * 8)) & 0xffff;
break;
default:
*val = temp;
break;
}
return 0;
}
static int
indirect_write_config_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
int len,
u32 val)
{
int bus = PCI_BUS(dev);
volatile unsigned char *cfg_data;
u32 temp;
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
*/
/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
cfg_data = hose->cfg_data;
switch (len) {
case 1:
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
temp = (temp & ~(0xff << ((offset & 3) * 8))) |
(val << ((offset & 3) * 8));
PEX_FIX;
out_le32((u32 *) cfg_data, temp);
break;
case 2:
PEX_FIX;
temp = in_le32((u32 *) cfg_data);
temp = (temp & ~(0xffff << ((offset & 3) * 8)));
temp |= (val << ((offset & 3) * 8));
PEX_FIX;
out_le32((u32 *) cfg_data, temp);
break;
default:
PEX_FIX;
out_le32((u32 *) cfg_data, val);
break;
}
PEX_FIX;
return 0;
}
static int
indirect_read_config_byte_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u8 *val)
{
u32 val32;
indirect_read_config_pcie(hose, dev, offset, 1, &val32);
*val = (u8) val32;
return 0;
}
static int
indirect_read_config_word_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u16 *val)
{
u32 val32;
indirect_read_config_pcie(hose, dev, offset, 2, &val32);
*val = (u16) val32;
return 0;
}
static int
indirect_read_config_dword_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u32 *val)
{
return indirect_read_config_pcie(hose, dev, offset, 4, val);
}
static int
indirect_write_config_byte_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u8 val)
{
return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
}
static int
indirect_write_config_word_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
unsigned short val)
{
return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
}
static int
indirect_write_config_dword_pcie(struct pci_controller *hose,
pci_dev_t dev,
int offset,
u32 val)
{
return indirect_write_config_pcie(hose, dev, offset, 4, val);
}
void
pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
{
pci_set_ops(hose,
indirect_read_config_byte_pcie,
indirect_read_config_word_pcie,
indirect_read_config_dword_pcie,
indirect_write_config_byte_pcie,
indirect_write_config_word_pcie,
indirect_write_config_dword_pcie);
hose->cfg_addr = (unsigned int *)cfg_addr;
hose->cfg_data = (unsigned char *)cfg_data;
}
#endif /* CONFIG_PCI */