arm: dts: sync am33xx with Linux 5.9-rc7
There have been several changes to the am33xx.dtsi, so this patch re-syncs it with Linux. Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel. With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. The am33xx-clock.dtsi file is the same as that of the Linux kernel, except for the reg property of the node l4-wkup-clkctrl@0. As for the am33xx.dtsi file, all the devices with drivers not yet implemented and those I was able to test with this patch have been moved to am33xx-l4.dtsi. In case of any regressions, problem devices can be reverted by moving them back and removing the related interconnect target module node. Signed-off-by: Dario Binacchi <dariobin@libero.it>
This commit is contained in:
Dario Binacchi
Lokesh Vutla
parent
92cc4e1c21
commit
6337d53fdf
@ -20,11 +20,6 @@
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};
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ocp {
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uart0: serial@44e09000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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i2c0: i2c@44e0b000 {
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pinctrl-names = "default";
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@ -112,6 +107,12 @@
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status = "disabled";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart4 {
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status = "disabled";
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};
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@ -486,7 +486,7 @@
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&epwmss0 {
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status = "okay";
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ecap0: ecap@48300100 {
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ecap0: ecap@100 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&ecap0_pins>;
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@ -531,7 +531,7 @@
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&epwmss2 {
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status = "okay";
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ecap2: ecap@48304100 {
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ecap2: ecap@100 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&ecap2_pins>;
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@ -26,11 +26,6 @@
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u-boot,dm-pre-reloc;
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};
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&rtc {
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clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clock-names = "int-clk";
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};
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&scm {
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u-boot,dm-pre-reloc;
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};
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@ -148,7 +148,7 @@
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&epwmss0 {
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status = "okay";
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ecap0: ecap@48300100 {
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ecap0: ecap@100 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&ecap0_pins>;
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@ -174,7 +174,7 @@
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&epwmss0 {
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status = "okay";
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ecap0: ecap@48300100 {
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ecap0: ecap@100 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&ecap0_pins>;
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@ -136,7 +136,7 @@
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&epwmss1 {
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status = "okay";
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ehrpwm1: pwm@48302200 {
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ehrpwm1: pwm@200 {
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pinctrl-names = "default";
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pinctrl-0 = <&ehrpwm1_pins>;
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status = "okay";
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@ -334,49 +334,49 @@
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timer1_fck: timer1_fck@528 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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reg = <0x0528>;
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};
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timer2_fck: timer2_fck@508 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0508>;
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};
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timer3_fck: timer3_fck@50c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x050c>;
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};
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timer4_fck: timer4_fck@510 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0510>;
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};
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timer5_fck: timer5_fck@518 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0518>;
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};
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timer6_fck: timer6_fck@51c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x051c>;
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};
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timer7_fck: timer7_fck@504 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0504>;
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};
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@ -407,7 +407,7 @@
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wdt1_fck: wdt1_fck@538 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x0538>;
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};
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@ -477,7 +477,7 @@
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gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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reg = <0x053c>;
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};
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@ -539,77 +539,131 @@
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};
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&prcm {
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l4_per_cm: l4_per_cm@0 {
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l4_per_cm: l4_per-cm@0 {
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compatible = "ti,omap4-cm";
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reg = <0x0 0x200>;
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reg = <0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x200>;
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ranges = <0 0x0 0x400>;
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l4_per_clkctrl: clk@14 {
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l4ls_clkctrl: l4ls-clkctrl@38 {
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compatible = "ti,clkctrl";
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reg = <0x14 0x13c>;
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reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
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#clock-cells = <2>;
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};
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l3s_clkctrl: l3s-clkctrl@1c {
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compatible = "ti,clkctrl";
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reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
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#clock-cells = <2>;
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};
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l3_clkctrl: l3-clkctrl@24 {
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compatible = "ti,clkctrl";
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reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
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#clock-cells = <2>;
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};
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l4hs_clkctrl: l4hs-clkctrl@120 {
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compatible = "ti,clkctrl";
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reg = <0x120 0x4>;
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#clock-cells = <2>;
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};
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pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
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compatible = "ti,clkctrl";
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reg = <0xe8 0x4>;
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#clock-cells = <2>;
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};
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cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
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compatible = "ti,clkctrl";
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reg = <0x0 0x18>;
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#clock-cells = <2>;
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};
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lcdc_clkctrl: lcdc-clkctrl@18 {
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compatible = "ti,clkctrl";
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reg = <0x18 0x4>;
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#clock-cells = <2>;
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};
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clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
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compatible = "ti,clkctrl";
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reg = <0x14c 0x4>;
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#clock-cells = <2>;
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};
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};
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l4_wkup_cm: l4_wkup_cm@400 {
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wkup_cm: wkup-cm@400 {
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compatible = "ti,omap4-cm";
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reg = <0x400 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x400 0x100>;
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l4_wkup_clkctrl: clk@4 {
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l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
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compatible = "ti,clkctrl";
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reg = <0x4 0xd4>;
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reg = <0x4 0x10>, <0xb4 0x24>;
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#clock-cells = <2>;
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};
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l3_aon_clkctrl: l3-aon-clkctrl@14 {
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compatible = "ti,clkctrl";
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reg = <0x14 0x4>;
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#clock-cells = <2>;
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};
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l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
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compatible = "ti,clkctrl";
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reg = <0xb0 0x4>;
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#clock-cells = <2>;
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};
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};
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mpu_cm: mpu_cm@600 {
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mpu_cm: mpu-cm@600 {
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compatible = "ti,omap4-cm";
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reg = <0x600 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x600 0x100>;
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mpu_clkctrl: clk@4 {
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mpu_clkctrl: mpu-clkctrl@0 {
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compatible = "ti,clkctrl";
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reg = <0x4 0x4>;
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reg = <0x0 0x8>;
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#clock-cells = <2>;
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};
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};
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l4_rtc_cm: l4_rtc_cm@800 {
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l4_rtc_cm: l4-rtc-cm@800 {
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compatible = "ti,omap4-cm";
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reg = <0x800 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x800 0x100>;
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l4_rtc_clkctrl: clk@0 {
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l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
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compatible = "ti,clkctrl";
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reg = <0x0 0x4>;
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#clock-cells = <2>;
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};
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};
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gfx_l3_cm: gfx_l3_cm@900 {
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gfx_l3_cm: gfx-l3-cm@900 {
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compatible = "ti,omap4-cm";
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reg = <0x900 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x900 0x100>;
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gfx_l3_clkctrl: clk@4 {
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gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
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compatible = "ti,clkctrl";
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reg = <0x4 0x4>;
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reg = <0x0 0x8>;
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#clock-cells = <2>;
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};
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};
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l4_cefuse_cm: l4_cefuse_cm@a00 {
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l4_cefuse_cm: l4-cefuse-cm@a00 {
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compatible = "ti,omap4-cm";
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reg = <0xa00 0x100>;
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#address-cells = <1>;
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1962
arch/arm/dts/am33xx-l4.dtsi
Normal file
1962
arch/arm/dts/am33xx-l4.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@ -8,6 +8,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/am33xx.h>
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#include <dt-bindings/clock/am3.h>
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@ -46,6 +47,7 @@
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a8";
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enable-method = "ti,am3352";
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device_type = "cpu";
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reg = <0>;
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@ -55,6 +57,17 @@
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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cpu-idle-states = <&mpu_gate>;
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};
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idle-states {
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mpu_gate: mpu_gate {
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compatible = "arm,idle-state";
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entry-latency-us = <40>;
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exit-latency-us = <90>;
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min-residency-us = <300>;
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ti,idle-wkup-m3;
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};
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};
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};
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@ -167,11 +180,6 @@
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ti,hwmods = "l3_main";
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l4_wkup: l4_wkup@44c00000 {
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compatible = "ti,am3-l4-wkup", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x44c00000 0x280000>;
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am3352-wkup-m3";
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reg = <0x100000 0x4000>,
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@ -180,73 +188,14 @@
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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prcm: prcm@200000 {
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compatible = "ti,am3-prcm", "simple-bus";
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reg = <0x200000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x200000 0x4000>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prcm_clockdomains: clockdomains {
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};
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};
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scm: scm@210000 {
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compatible = "ti,am3-scm", "simple-bus";
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reg = <0x210000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#pinctrl-cells = <1>;
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ranges = <0 0x210000 0x2000>;
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am33xx_pinmux: pinmux@800 {
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compatible = "pinctrl-single";
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reg = <0x800 0x238>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x7f>;
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};
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scm_conf: scm_conf@0 {
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compatible = "syscon", "simple-bus";
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reg = <0x0 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x800>;
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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wkup_m3_ipc: wkup_m3_ipc@1324 {
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compatible = "ti,am3352-wkup-m3-ipc";
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reg = <0x1324 0x24>;
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interrupts = <78>;
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ti,rproc = <&wkup_m3>;
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mboxes = <&mailbox &mbox_wkupm3>;
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};
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edma_xbar: dma-router@f90 {
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compatible = "ti,am335x-edma-crossbar";
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reg = <0xf90 0x40>;
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#dma-cells = <3>;
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dma-requests = <32>;
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dma-masters = <&edma>;
|
||||
};
|
||||
|
||||
scm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
};
|
||||
l4_per: interconnect@48000000 {
|
||||
};
|
||||
l4_fw: interconnect@47c00000 {
|
||||
};
|
||||
l4_fast: interconnect@4a000000 {
|
||||
};
|
||||
l4_mpuss: interconnect@4b140000 {
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
@ -256,45 +205,100 @@
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
ti,hwmods = "tpcc";
|
||||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
target-module@49000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49000000 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49000000 0x10000>;
|
||||
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
edma: dma@0 {
|
||||
compatible = "ti,edma3-tpcc";
|
||||
reg = <0 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
||||
<&edma_tptc2 0>;
|
||||
|
||||
ti,edma-memcpy-channels = <20 21>;
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc0: tptc@49800000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc0";
|
||||
reg = <0x49800000 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49800000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49800000 0x4>,
|
||||
<0x49800010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49800000 0x100000>;
|
||||
|
||||
edma_tptc0: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <112>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc1: tptc@49900000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc1";
|
||||
reg = <0x49900000 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49900000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49900000 0x4>,
|
||||
<0x49900010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49900000 0x100000>;
|
||||
|
||||
edma_tptc1: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <113>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
edma_tptc2: tptc@49a00000 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
ti,hwmods = "tptc2";
|
||||
reg = <0x49a00000 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
target-module@49a00000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x49a00000 0x4>,
|
||||
<0x49a00010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x49a00000 0x100000>;
|
||||
|
||||
edma_tptc2: dma@0 {
|
||||
compatible = "ti,edma3-tptc";
|
||||
reg = <0 0x100000>;
|
||||
interrupts = <114>;
|
||||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@44e07000 {
|
||||
@ -341,66 +345,6 @@
|
||||
interrupts = <62>;
|
||||
};
|
||||
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 26 0>, <&edma 27 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart1: serial@48022000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 28 0>, <&edma 29 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart2: serial@48024000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 30 0>, <&edma 31 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart3: serial@481a6000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481a8000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481aa000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
@ -466,13 +410,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@480ca000 {
|
||||
compatible = "ti,omap4-hwspinlock";
|
||||
reg = <0x480ca000 0x1000>;
|
||||
ti,hwmods = "spinlock";
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
wdt2: wdt@44e35000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
@ -480,143 +417,6 @@
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
dcan0: can@481cc000 {
|
||||
compatible = "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can0";
|
||||
reg = <0x481cc000 0x2000>;
|
||||
clocks = <&dcan0_fck>;
|
||||
clock-names = "fck";
|
||||
syscon-raminit = <&scm_conf 0x644 0>;
|
||||
interrupts = <52>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcan1: can@481d0000 {
|
||||
compatible = "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can1";
|
||||
reg = <0x481d0000 0x2000>;
|
||||
clocks = <&dcan1_fck>;
|
||||
clock-names = "fck";
|
||||
syscon-raminit = <&scm_conf 0x644 1>;
|
||||
interrupts = <55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480C8000 0x200>;
|
||||
interrupts = <77>;
|
||||
ti,hwmods = "mailbox";
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-send-noirq;
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
compatible = "ti,am335x-timer-1ms";
|
||||
reg = <0x44e31000 0x400>;
|
||||
interrupts = <67>;
|
||||
ti,hwmods = "timer1";
|
||||
ti,timer-alwon;
|
||||
clocks = <&timer1_fck>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48040000 0x400>;
|
||||
interrupts = <68>;
|
||||
ti,hwmods = "timer2";
|
||||
clocks = <&timer2_fck>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48042000 0x400>;
|
||||
interrupts = <69>;
|
||||
ti,hwmods = "timer3";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48044000 0x400>;
|
||||
interrupts = <92>;
|
||||
ti,hwmods = "timer4";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48046000 0x400>;
|
||||
interrupts = <93>;
|
||||
ti,hwmods = "timer5";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48048000 0x400>;
|
||||
interrupts = <94>;
|
||||
ti,hwmods = "timer6";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x4804a000 0x400>;
|
||||
interrupts = <95>;
|
||||
ti,hwmods = "timer7";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
rtc: rtc@44e3e000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0x44e3e000 0x1000>;
|
||||
interrupts = <75
|
||||
76>;
|
||||
ti,hwmods = "rtc";
|
||||
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
|
||||
clock-names = "int-clk";
|
||||
};
|
||||
|
||||
spi0: spi@48030000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x48030000 0x400>;
|
||||
interrupts = <65>;
|
||||
ti,spi-num-cs = <2>;
|
||||
ti,hwmods = "spi0";
|
||||
dmas = <&edma 16 0
|
||||
&edma 17 0
|
||||
&edma 18 0
|
||||
&edma 19 0>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@481a0000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x481a0000 0x400>;
|
||||
interrupts = <125>;
|
||||
ti,spi-num-cs = <2>;
|
||||
ti,hwmods = "spi1";
|
||||
dmas = <&edma 42 0
|
||||
&edma 43 0
|
||||
&edma 44 0
|
||||
&edma 45 0>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@47400000 {
|
||||
compatible = "ti,am33xx-usb";
|
||||
reg = <0x47400000 0x1000>;
|
||||
@ -731,121 +531,18 @@
|
||||
"tx14", "tx15";
|
||||
};
|
||||
|
||||
cppi41dma: dma-controller@47402000 {
|
||||
cppi41dma: dma-controller@2000 {
|
||||
compatible = "ti,am3359-cppi41";
|
||||
reg = <0x47400000 0x1000
|
||||
0x47402000 0x1000
|
||||
0x47403000 0x1000
|
||||
0x47404000 0x4000>;
|
||||
reg = <0x0000 0x1000>,
|
||||
<0x2000 0x1000>,
|
||||
<0x3000 0x1000>,
|
||||
<0x4000 0x4000>;
|
||||
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
||||
interrupts = <17>;
|
||||
interrupt-names = "glue";
|
||||
#dma-cells = <2>;
|
||||
#dma-channels = <30>;
|
||||
#dma-requests = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
||||
0x48300180 0x48300180 0x80 /* EQEP */
|
||||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <31>;
|
||||
interrupt-names = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: pwm@48300200 {
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48302000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48302000 0x10>;
|
||||
ti,hwmods = "epwmss1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
|
||||
0x48302180 0x48302180 0x80 /* EQEP */
|
||||
0x48302200 0x48302200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <47>;
|
||||
interrupt-names = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: pwm@48302200 {
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48304000 0x10>;
|
||||
ti,hwmods = "epwmss2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
|
||||
0x48304180 0x48304180 0x80 /* EQEP */
|
||||
0x48304200 0x48304200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <61>;
|
||||
interrupt-names = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: pwm@48304200 {
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -904,60 +601,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: ocmcram@40300000 {
|
||||
ocmcram: sram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x10000>; /* 64k */
|
||||
ranges = <0x0 0x40300000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pm_sram_code: pm-sram-code@0 {
|
||||
pm_sram_code: pm-code-sram@0 {
|
||||
compatible = "ti,sram";
|
||||
reg = <0x0 0x1000>;
|
||||
protect-exec;
|
||||
};
|
||||
|
||||
pm_sram_data: pm-sram-data@1000 {
|
||||
pm_sram_data: pm-data-sram@1000 {
|
||||
compatible = "ti,sram";
|
||||
reg = <0x1000 0x1000>;
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,am3352-elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
ti,hwmods = "elm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdc: lcdc@4830e000 {
|
||||
compatible = "ti,am33xx-tilcdc";
|
||||
reg = <0x4830e000 0x1000>;
|
||||
interrupts = <36>;
|
||||
ti,hwmods = "lcdc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tscadc: tscadc@44e0d000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x44e0d000 0x1000>;
|
||||
interrupts = <16>;
|
||||
ti,hwmods = "adc_tsc";
|
||||
status = "disabled";
|
||||
dmas = <&edma 53 0>, <&edma 57 0>;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
|
||||
tsc {
|
||||
compatible = "ti,am3359-tsc";
|
||||
};
|
||||
am335x_adc: adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
emif: emif@4c000000 {
|
||||
compatible = "ti,emif-am3352";
|
||||
reg = <0x4c000000 0x1000000>;
|
||||
@ -987,60 +650,116 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap4-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x53100000 0x200>;
|
||||
interrupts = <109>;
|
||||
dmas = <&edma 36 0>;
|
||||
dma-names = "rx";
|
||||
sham_target: target-module@53100000 {
|
||||
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
||||
reg = <0x53100100 0x4>,
|
||||
<0x53100110 0x4>,
|
||||
<0x53100114 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
||||
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x53100000 0x1000>;
|
||||
|
||||
sham: sham@0 {
|
||||
compatible = "ti,omap4-sham";
|
||||
reg = <0 0x200>;
|
||||
interrupts = <109>;
|
||||
dmas = <&edma 36 0>;
|
||||
dma-names = "rx";
|
||||
};
|
||||
};
|
||||
|
||||
aes: aes@53500000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x53500000 0xa0>;
|
||||
interrupts = <103>;
|
||||
dmas = <&edma 6 0>,
|
||||
<&edma 5 0>;
|
||||
dma-names = "tx", "rx";
|
||||
aes_target: target-module@53500000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x53500080 0x4>,
|
||||
<0x53500084 0x4>,
|
||||
<0x53500088 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
||||
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x53500000 0x1000>;
|
||||
|
||||
aes: aes@0 {
|
||||
compatible = "ti,omap4-aes";
|
||||
reg = <0 0xa0>;
|
||||
interrupts = <103>;
|
||||
dmas = <&edma 6 0>,
|
||||
<&edma 5 0>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
|
||||
mcasp0: mcasp@48038000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp0";
|
||||
reg = <0x48038000 0x2000>,
|
||||
<0x46000000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <80>, <81>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 8 2>,
|
||||
<&edma 9 2>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
<0x5600fe10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
resets = <&prm_gfx 0>;
|
||||
reset-names = "rstctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x1000000>;
|
||||
|
||||
mcasp1: mcasp@4803c000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp1";
|
||||
reg = <0x4803C000 0x2000>,
|
||||
<0x46400000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <82>, <83>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 10 2>,
|
||||
<&edma 11 2>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rng: rng@48310000 {
|
||||
compatible = "ti,omap4-rng";
|
||||
ti,hwmods = "rng";
|
||||
reg = <0x48310000 0x2000>;
|
||||
interrupts = <111>;
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "am33xx-l4.dtsi"
|
||||
#include "am33xx-clocks.dtsi"
|
||||
|
||||
&prcm {
|
||||
prm_per: prm@c00 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xc00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_wkup: prm@d00 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xd00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_device: prm@f00 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xf00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_gfx: prm@1100 {
|
||||
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1100 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user