ARM:AM33XX: Add emif/ddr support
This patch adds AM33xx emif/ddr support along with board specific defines. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Chandan Nath
Albert ARIBAUD
parent
f87fa62af9
commit
62d7fe7c91
@ -20,6 +20,9 @@ SOBJS := lowlevel_init.o
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COBJS += clock.o
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COBJS += sys_info.o
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COBJS += ddr.o
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COBJS += emif4.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
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147
arch/arm/cpu/armv7/am33xx/ddr.c
Normal file
147
arch/arm/cpu/armv7/am33xx/ddr.c
Normal file
@ -0,0 +1,147 @@
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/*
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* DDR Configuration for AM33xx devices.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated -
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http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/io.h>
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/**
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* Base address for EMIF instances
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*/
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static struct emif_regs *emif_reg = {
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(struct emif_regs *)EMIF4_0_CFG_BASE};
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/**
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* Base address for DDR instance
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*/
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static struct ddr_regs *ddr_reg[2] = {
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(struct ddr_regs *)DDR_PHY_BASE_ADDR,
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(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
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/**
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* Base address for ddr io control instances
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*/
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static struct ddr_cmdtctrl *ioctrl_reg = {
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(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
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/**
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* As a convention, all functions here return 0 on success
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* -1 on failure.
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*/
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/**
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* Configure SDRAM
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*/
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int config_sdram(struct sdram_config *cfg)
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{
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writel(cfg->sdrcr, &emif_reg->sdrcr);
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writel(cfg->sdrcr2, &emif_reg->sdrcr2);
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writel(cfg->refresh, &emif_reg->sdrrcr);
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writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
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return 0;
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}
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/**
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* Set SDRAM timings
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*/
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int set_sdram_timings(struct sdram_timing *t)
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{
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writel(t->time1, &emif_reg->sdrtim1);
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writel(t->time1_sh, &emif_reg->sdrtim1sr);
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writel(t->time2, &emif_reg->sdrtim2);
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writel(t->time2_sh, &emif_reg->sdrtim2sr);
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writel(t->time3, &emif_reg->sdrtim3);
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writel(t->time3_sh, &emif_reg->sdrtim3sr);
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return 0;
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}
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/**
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* Configure DDR PHY
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*/
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int config_ddr_phy(struct ddr_phy_control *p)
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{
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writel(p->reg, &emif_reg->ddrphycr);
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writel(p->reg_sh, &emif_reg->ddrphycsr);
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return 0;
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}
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/**
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* Configure DDR CMD control registers
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*/
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int config_cmd_ctrl(struct cmd_control *cmd)
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{
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writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
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writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
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writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
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writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
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writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
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writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
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writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
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writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
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writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
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writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
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writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
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writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
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writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
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writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
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writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
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return 0;
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}
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/**
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* Configure DDR DATA registers
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*/
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int config_ddr_data(int macrono, struct ddr_data *data)
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{
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writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
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writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
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writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
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writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
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writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
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writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
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writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
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writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
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writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
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writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
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writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
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writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
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writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
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return 0;
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}
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int config_io_ctrl(struct ddr_ioctrl *ioctrl)
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{
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writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
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writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
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writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
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writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
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writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
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return 0;
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}
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201
arch/arm/cpu/armv7/am33xx/emif4.c
Normal file
201
arch/arm/cpu/armv7/am33xx/emif4.c
Normal file
@ -0,0 +1,201 @@
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/*
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* emif4.c
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*
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* AM33XX emif4 configuration file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
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struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
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struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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#ifdef CONFIG_AM335X_CONFIG_DDR
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static void data_macro_config(int dataMacroNum)
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{
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struct ddr_data data;
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data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
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|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
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data.datardsratio1 = DDR2_RD_DQS>>2;
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data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
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|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
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data.datawdsratio1 = DDR2_WR_DQS>>2;
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data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
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|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
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data.datawiratio1 = DDR2_PHY_WRLVL>>2;
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data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
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|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
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data.datagiratio1 = DDR2_PHY_GATELVL>>2;
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data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
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|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
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data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
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data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
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|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
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data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
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data.datadldiff0 = PHY_DLL_LOCK_DIFF;
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config_ddr_data(dataMacroNum, &data);
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}
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static void cmd_macro_config(void)
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{
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struct cmd_control cmd;
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cmd.cmd0csratio = DDR2_RATIO;
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cmd.cmd0csforce = CMD_FORCE;
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cmd.cmd0csdelay = CMD_DELAY;
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cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
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cmd.cmd1csratio = DDR2_RATIO;
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cmd.cmd1csforce = CMD_FORCE;
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cmd.cmd1csdelay = CMD_DELAY;
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cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
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cmd.cmd2csratio = DDR2_RATIO;
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cmd.cmd2csforce = CMD_FORCE;
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cmd.cmd2csdelay = CMD_DELAY;
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cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
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config_cmd_ctrl(&cmd);
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}
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static void config_vtp(void)
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{
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
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&vtpreg->vtp0ctrlreg);
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/* Poll for READY */
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while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
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VTP_CTRL_READY)
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;
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}
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static void config_emif_ddr2(void)
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{
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int i;
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int ret;
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struct sdram_config cfg;
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struct sdram_timing tmg;
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struct ddr_phy_control phyc;
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/*Program EMIF0 CFG Registers*/
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phyc.reg = EMIF_READ_LATENCY;
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phyc.reg_sh = EMIF_READ_LATENCY;
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phyc.reg2 = EMIF_READ_LATENCY;
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tmg.time1 = EMIF_TIM1;
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tmg.time1_sh = EMIF_TIM1;
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tmg.time2 = EMIF_TIM2;
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tmg.time2_sh = EMIF_TIM2;
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tmg.time3 = EMIF_TIM3;
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tmg.time3_sh = EMIF_TIM3;
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cfg.sdrcr = EMIF_SDCFG;
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cfg.sdrcr2 = EMIF_SDCFG;
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cfg.refresh = 0x00004650;
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cfg.refresh_sh = 0x00004650;
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/* Program EMIF instance */
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ret = config_ddr_phy(&phyc);
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if (ret < 0)
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printf("Couldn't configure phyc\n");
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ret = config_sdram(&cfg);
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if (ret < 0)
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printf("Couldn't configure SDRAM\n");
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ret = set_sdram_timings(&tmg);
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if (ret < 0)
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printf("Couldn't configure timings\n");
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/* Delay */
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for (i = 0; i < 5000; i++)
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;
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cfg.refresh = EMIF_SDREF;
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cfg.refresh_sh = EMIF_SDREF;
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cfg.sdrcr = EMIF_SDCFG;
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cfg.sdrcr2 = EMIF_SDCFG;
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ret = config_sdram(&cfg);
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if (ret < 0)
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printf("Couldn't configure SDRAM\n");
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}
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void config_ddr(void)
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{
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int data_macro_0 = 0;
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int data_macro_1 = 1;
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struct ddr_ioctrl ioctrl;
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enable_emif_clocks();
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config_vtp();
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cmd_macro_config();
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data_macro_config(data_macro_0);
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data_macro_config(data_macro_1);
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writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
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writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
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ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
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ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
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ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
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ioctrl.data1ctl = DDR_IOCTRL_VALUE;
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ioctrl.data2ctl = DDR_IOCTRL_VALUE;
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config_io_ctrl(&ioctrl);
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writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
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writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
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config_emif_ddr2();
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}
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#endif
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264
arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
264
arch/arm/include/asm/arch-am33xx/ddr_defs.h
Normal file
@ -0,0 +1,264 @@
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/*
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* ddr_defs.h
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*
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* ddr specific header
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#ifndef _DDR_DEFS_H
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#define _DDR_DEFS_H
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#include <asm/arch/hardware.h>
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/* AM335X EMIF Register values */
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#define EMIF_SDMGT 0x80000000
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#define EMIF_SDRAM 0x00004650
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#define EMIF_PHYCFG 0x2
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#define DDR_PHY_RESET (0x1 << 10)
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#define DDR_FUNCTIONAL_MODE_EN 0x1
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#define DDR_PHY_READY (0x1 << 2)
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_LOCK_EN (0x1 << 4)
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#define VTP_CTRL_START_EN (0x1)
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#define DDR2_RATIO 0x80
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#define CMD_FORCE 0x00
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#define CMD_DELAY 0x00
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#define EMIF_READ_LATENCY 0x04
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#define EMIF_TIM1 0x0666B3D6
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#define EMIF_TIM2 0x143731DA
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#define EMIF_TIM3 0x00000347
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#define EMIF_SDCFG 0x43805332
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#define EMIF_SDREF 0x0000081a
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#define DDR2_DLL_LOCK_DIFF 0x0
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#define DDR2_RD_DQS 0x12
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#define DDR2_PHY_FIFO_WE 0x80
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#define DDR2_INVERT_CLKOUT 0x00
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#define DDR2_WR_DQS 0x00
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_WR_DATA 0x40
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#define PHY_RANK0_DELAY 0x01
|
||||
#define PHY_DLL_LOCK_DIFF 0x0
|
||||
#define DDR_IOCTRL_VALUE 0x18B
|
||||
|
||||
/**
|
||||
* This structure represents the EMIF registers on AM33XX devices.
|
||||
*/
|
||||
struct emif_regs {
|
||||
unsigned int sdrrev; /* offset 0x00 */
|
||||
unsigned int sdrstat; /* offset 0x04 */
|
||||
unsigned int sdrcr; /* offset 0x08 */
|
||||
unsigned int sdrcr2; /* offset 0x0C */
|
||||
unsigned int sdrrcr; /* offset 0x10 */
|
||||
unsigned int sdrrcsr; /* offset 0x14 */
|
||||
unsigned int sdrtim1; /* offset 0x18 */
|
||||
unsigned int sdrtim1sr; /* offset 0x1C */
|
||||
unsigned int sdrtim2; /* offset 0x20 */
|
||||
unsigned int sdrtim2sr; /* offset 0x24 */
|
||||
unsigned int sdrtim3; /* offset 0x28 */
|
||||
unsigned int sdrtim3sr; /* offset 0x2C */
|
||||
unsigned int res1[2];
|
||||
unsigned int sdrmcr; /* offset 0x38 */
|
||||
unsigned int sdrmcsr; /* offset 0x3C */
|
||||
unsigned int res2[8];
|
||||
unsigned int sdritr; /* offset 0x60 */
|
||||
unsigned int res3[20];
|
||||
unsigned int ddrphycr; /* offset 0xE4 */
|
||||
unsigned int ddrphycsr; /* offset 0xE8 */
|
||||
unsigned int ddrphycr2; /* offset 0xEC */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR PHY control and corresponding shadow registers.
|
||||
*/
|
||||
struct ddr_phy_control {
|
||||
unsigned long reg;
|
||||
unsigned long reg_sh;
|
||||
unsigned long reg2;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates SDRAM timing and corresponding shadow registers.
|
||||
*/
|
||||
struct sdram_timing {
|
||||
unsigned long time1;
|
||||
unsigned long time1_sh;
|
||||
unsigned long time2;
|
||||
unsigned long time2_sh;
|
||||
unsigned long time3;
|
||||
unsigned long time3_sh;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates SDRAM configuration.
|
||||
* (Includes refresh control registers) */
|
||||
struct sdram_config {
|
||||
unsigned long sdrcr;
|
||||
unsigned long sdrcr2;
|
||||
unsigned long refresh;
|
||||
unsigned long refresh_sh;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure SDRAM
|
||||
*/
|
||||
int config_sdram(struct sdram_config *cfg);
|
||||
|
||||
/**
|
||||
* Set SDRAM timings
|
||||
*/
|
||||
int set_sdram_timings(struct sdram_timing *val);
|
||||
|
||||
/**
|
||||
* Configure DDR PHY
|
||||
*/
|
||||
int config_ddr_phy(struct ddr_phy_control *cfg);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR registers on AM33XX devices.
|
||||
*/
|
||||
struct ddr_regs {
|
||||
unsigned int resv0[7];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int cm0csforce; /* offset 0x020 */
|
||||
unsigned int cm0csdelay; /* offset 0x024 */
|
||||
unsigned int cm0dldiff; /* offset 0x028 */
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv1[8];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int cm1csforce; /* offset 0x054 */
|
||||
unsigned int cm1csdelay; /* offset 0x058 */
|
||||
unsigned int cm1dldiff; /* offset 0x05C */
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv2[8];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int cm2csforce; /* offset 0x088 */
|
||||
unsigned int cm2csdelay; /* offset 0x08C */
|
||||
unsigned int cm2dldiff; /* offset 0x090 */
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv3[12];
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int dt0rdsratio1; /* offset 0x0CC */
|
||||
unsigned int resv4[3];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int dt0wdsratio1; /* offset 0x0E0 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int dt0wiratio1; /* offset 0x0F4 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int dt0giratio1; /* offset 0x100 */
|
||||
unsigned int resv6[2];
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int dt0fwsratio1; /* offset 0x10C */
|
||||
unsigned int resv7[5];
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int dt0wrsratio1; /* offset 0x124 */
|
||||
unsigned int resv8[3];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
unsigned int resv9[39];
|
||||
unsigned int dt1rdelays0; /* offset 0x1D8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD control registers.
|
||||
*/
|
||||
struct cmd_control {
|
||||
unsigned long cmd0csratio;
|
||||
unsigned long cmd0csforce;
|
||||
unsigned long cmd0csdelay;
|
||||
unsigned long cmd0dldiff;
|
||||
unsigned long cmd0iclkout;
|
||||
unsigned long cmd1csratio;
|
||||
unsigned long cmd1csforce;
|
||||
unsigned long cmd1csdelay;
|
||||
unsigned long cmd1dldiff;
|
||||
unsigned long cmd1iclkout;
|
||||
unsigned long cmd2csratio;
|
||||
unsigned long cmd2csforce;
|
||||
unsigned long cmd2csdelay;
|
||||
unsigned long cmd2dldiff;
|
||||
unsigned long cmd2iclkout;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR DATA registers.
|
||||
*/
|
||||
struct ddr_data {
|
||||
unsigned long datardsratio0;
|
||||
unsigned long datardsratio1;
|
||||
unsigned long datawdsratio0;
|
||||
unsigned long datawdsratio1;
|
||||
unsigned long datawiratio0;
|
||||
unsigned long datawiratio1;
|
||||
unsigned long datagiratio0;
|
||||
unsigned long datagiratio1;
|
||||
unsigned long datafwsratio0;
|
||||
unsigned long datafwsratio1;
|
||||
unsigned long datawrsratio0;
|
||||
unsigned long datawrsratio1;
|
||||
unsigned long datadldiff0;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR CMD control registers
|
||||
*/
|
||||
int config_cmd_ctrl(struct cmd_control *cmd);
|
||||
|
||||
/**
|
||||
* Configure DDR DATA registers
|
||||
*/
|
||||
int config_ddr_data(int data_macrono, struct ddr_data *data);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR io control on AM33XX devices.
|
||||
*/
|
||||
struct ddr_cmdtctrl {
|
||||
unsigned int resv1[1];
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int resv2[12];
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD & DATA io control registers.
|
||||
*/
|
||||
struct ddr_ioctrl {
|
||||
unsigned long cmd1ctl;
|
||||
unsigned long cmd2ctl;
|
||||
unsigned long cmd3ctl;
|
||||
unsigned long data1ctl;
|
||||
unsigned long data2ctl;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR io control registers
|
||||
*/
|
||||
int config_io_ctrl(struct ddr_ioctrl *ioctrl);
|
||||
|
||||
struct ddr_ctrl {
|
||||
unsigned int ddrioctrl;
|
||||
unsigned int resv1[325];
|
||||
unsigned int ddrckectrl;
|
||||
};
|
||||
|
||||
void config_ddr(void);
|
||||
|
||||
#endif /* _DDR_DEFS_H */
|
||||
39
arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
39
arch/arm/include/asm/arch-am33xx/sys_proto.h
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* sys_proto.h
|
||||
*
|
||||
* System information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
#define BOARD_REV_ID 0x0
|
||||
struct {
|
||||
u32 board_type_v1;
|
||||
u32 board_type_v2;
|
||||
u32 mtype;
|
||||
char *board_string;
|
||||
char *nand_string;
|
||||
} board_sysinfo;
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
u32 get_sysboot_value(void);
|
||||
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void);
|
||||
#endif
|
||||
|
||||
u32 get_device_type(void);
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user