powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb
- Remove duplicate doc/README.p1010rdb - Rename README to README.P1010RDB-PA - Add new README.P1010RDB-PB P1010RDB-PB is a variation of previous P1010RDB-PA board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
This commit is contained in:
Shengzhou Liu
York Sun
parent
439fbe75a0
commit
62af7615eb
@ -204,5 +204,5 @@ Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
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=> bootm 1000000 3000000 2000000
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Please contact your local field applications engineer or sales representative
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to obtain related documents, such as P1010-RDB User Guide for details.
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For more details, please refer to P1010RDB User Guide and access website
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www.freescale.com
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188
board/freescale/p1010rdb/README.P1010RDB-PB
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188
board/freescale/p1010rdb/README.P1010RDB-PB
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@ -0,0 +1,188 @@
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Overview
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=========
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The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
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P1010RDB-PB is a variation of previous P1010RDB-PA board.
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The P1010 is a cost-effective, low-power, highly integrated host processor
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based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
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addresses the requirements of several routing, gateways, storage, consumer,
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and industrial applications. Applications of interest include the main CPUs and
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I/O processors in network attached storage (NAS), the voice over IP (VoIP)
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router/gateway, and wireless LAN (WLAN) and industrial controllers.
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The P1010RDB-PB board features are as following:
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Memory subsystem:
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- 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
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- 32M bytes NOR flash single-chip memory
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- 2G bytes NAND flash memory
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- 16M bytes SPI memory
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- 256K bit M24256 I2C EEPROM
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- I2C Board EEPROM 128x8 bit memory
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- SD/MMC connector to interface with the SD memory card
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Interfaces:
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- Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
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- PCIe 2.0: two x1 mini-PCIe slots
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- SATA 2.0: two SATA interfaces
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- USB 2.0: one USB interface
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- FlexCAN: two FlexCAN interfaces (revision 2.0B)
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- UART: one USB-to-Serial interface
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- TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
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1 FXO port connected via a relay to FXS for switchover to POTS
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Board connectors:
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- Mini-ITX power supply connector
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- JTAG/COP for debugging
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POR: support critical POR setting changed via switch on board
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PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
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Physical Memory Map on P1010RDB
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===============================
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Address Start Address End Memory type Attributes
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0x0000_0000 0x3fff_ffff DDR 1G Cacheable
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0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
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0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
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0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
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0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
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0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
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0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
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0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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Serial Port Configuration on P1010RDB
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=====================================
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Configure the serial port of the attached computer with the following values:
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-Data rate: 115200 bps
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-Number of data bits: 8
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-Parity: None
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-Number of Stop bits: 1
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-Flow Control: Hardware/None
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P1010RDB-PB default DIP-switch settings
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=======================================
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SW1[1:8]= 10101010
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SW2[1:8]= 11011000
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SW3[1:8]= 10010000
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SW4[1:4]= 1010
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SW5[1:8]= 11111010
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P1010RDB-PB boot mode settings via DIP-switch
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=============================================
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SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
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SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
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SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
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SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
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Note: 1 stands for 'on', 0 stands for 'off'
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Switch P1010RDB-PB boot mode via software without setting DIP-switch
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====================================================================
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=> run boot_bank0 (boot from NOR bank0)
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=> run boot_bank1 (boot from NOR bank1)
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=> run boot_nand (boot from NAND flash)
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=> run boot_spi (boot from SPI flash)
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=> run boot_sd (boot from SD card)
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Frequency combination support on P1010RDB-PB
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=============================================
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SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
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0101 1 1010 0 800 400 800
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1001 1 1010 0 800 400 667
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1010 1 1100 0 667 333 667
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1000 0 1010 0 533 266 667
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0101 1 1010 1 1000 400 800
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1001 1 1010 1 1000 400 667
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Setting of pin mux
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==================
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Since pins multiplexing, TDM and CAN are muxed with SPI flash.
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SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
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To enable TDM:
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=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
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=> save;reset
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To enable FlexCAN:
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=> setenv hwconfig fsl_p1010mux:tdm_can=can
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=> save;reset
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To enable SDHC in case of NOR/NAND/SPI boot
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a) For temporary use case in runtime without reboot system
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run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
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b) For long-term use case
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set 'esdhc' in hwconfig and save it.
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To enable IFC in case of SD boot
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a) For temporary use case in runtime without reboot system
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run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
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b) For long-term use case
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set 'ifc' in hwconfig and save it.
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Build images for different boot mode
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====================================
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First setup cross compile environment on build host
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$ export ARCH=powerpc
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$ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
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1. For NOR boot
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$ make P1010RDB-PB_NOR
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2. For NAND boot
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$ make P1010RDB-PB_NAND
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3. For SPI boot
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$ make P1010RDB-PB_SPIFLASH
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4. For SD boot
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$ make P1010RDB-PB_SDCARD
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Steps to program images to flash for different boot mode
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========================================================
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1. NOR boot
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=> tftp 1000000 u-boot.bin
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For bank0
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=> pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
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set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
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For bank1
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=> pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
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set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
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2. NAND boot
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=> tftp 1000000 u-boot-nand.bin
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=> nand erase 0 $filesize; nand write $loadaddr 0 $filesize
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Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
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3. SPI boot
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1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
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2) => tftp 1000000 u-boot-spi-combined.bin
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3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
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set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
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4. SD boot
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1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
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2) => tftp 1000000 u-boot-sd-combined.bin
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3) => mux sdhc
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4) => mmc write 1000000 0 1050
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set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
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Boot Linux from network using TFTP on P1010RDB-PB
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=================================================
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Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
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=> tftp 1000000 uImage
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=> tftp 2000000 p1010rdb.dtb
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=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
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=> bootm 1000000 3000000 2000000
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For more details, please refer to P1010RDB-PB User Guide and access website
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www.freescale.com and Freescale QorIQ SDK Infocenter document.
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@ -1,198 +0,0 @@
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Overview
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=========
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The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
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The P1010 is a cost-effective, low-power, highly integrated host processor
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based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
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that addresses the requirements of several routing, gateways, storage, consumer,
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and industrial applications. Applications of interest include the main CPUs and
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I/O processors in network attached storage (NAS), the voice over IP (VoIP)
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router/gateway, and wireless LAN (WLAN) and industrial controllers.
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The P1010RDB board features are as follows:
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Memory subsystem:
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- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
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- 32 Mbyte NOR flash single-chip memory
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- 32 Mbyte NAND flash memory
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- 256 Kbit M24256 I2C EEPROM
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- 16 Mbyte SPI memory
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- I2C Board EEPROM 128x8 bit memory
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- SD/MMC connector to interface with the SD memory card
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Interfaces:
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- PCIe:
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- Lane0: x1 mini-PCIe slot
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- Lane1: x1 PCIe standard slot
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- SATA:
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- 1 internal SATA connector to 2.5" 160G SATA2 HDD
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- 1 eSATA connector to rear panel
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- 10/100/1000 BaseT Ethernet ports:
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- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
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- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
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- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
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- USB 2.0 port:
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- x1 USB2.0 port: via an ULPI PHY to micro-AB connector
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- x1 USB2.0 poort via an internal PHY to micro-AB connector
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- FlexCAN ports:
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- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
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interface;
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- DUART interface:
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- DUART interface: supports two UARTs up to 115200 bps for
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console display
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- J45 connectors are used for these 2 UART ports.
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- TDM
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- 2 FXS ports connected via an external SLIC to the TDM
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interface. SLIC is controllled via SPI.
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- 1 FXO port connected via a relay to FXS for switchover to
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POTS
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Board connectors:
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- Mini-ITX power supply connector
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- JTAG/COP for debugging
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IEEE Std. 1588 signals for test and measurement
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Real-time clock on I2C bus
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POR
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- support critical POR setting changed via switch on board
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PCB
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- 6-layer routing (4-layer signals, 2-layer power and ground)
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Serial Port Configuration on P1010RDB
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=====================================
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Configure the serial port of the attached computer with the following values:
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-Data rate: 115200 bps
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-Number of data bits: 8
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-Parity: None
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-Number of Stop bits: 1
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-Flow Control: Hardware/None
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Settings of DIP-switch
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======================
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SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
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SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
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SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
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Note: 1 stands for 'on', 0 stands for 'off'
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Setting of hwconfig
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===================
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If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
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"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
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setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
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By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
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is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
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instead of to CAN/UART1.
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Build and burn u-boot to NOR flash
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==================================
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1. Build u-boot.bin image
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export ARCH=powerpc
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
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make P1010RDB_NOR
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2. Burn u-boot.bin into NOR flash
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=> tftp $loadaddr $uboot
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=> protect off eff80000 +$filesize
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=> erase eff80000 +$filesize
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=> cp.b $loadaddr eff80000 $filesize
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3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
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Alternate NOR bank
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============================
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1. Burn u-boot.bin into alternate NOR bank
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=> tftp $loadaddr $uboot
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=> protect off eef80000 +$filesize
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=> erase eef80000 +$filesize
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=> cp.b $loadaddr eef80000 $filesize
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2. Switch to alternate NOR bank
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=> mw.b ffb00009 1
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=> reset
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or set SW1[8]= ON
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SW1[8]= OFF: Upper bank used for booting start
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SW1[8]= ON: Lower bank used for booting start
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CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
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0 - boot from upper 4 sectors
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1 - boot from lower 4 sectors
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Build and burn u-boot to NAND flash
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===================================
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1. Build u-boot.bin image
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export ARCH=powerpc
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
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make P1010RDB_NAND
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2. Burn u-boot-nand.bin into NAND flash
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=> tftp $loadaddr $uboot-nand
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=> nand erase 0 $filesize
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=> nand write $loadaddr 0 $filesize
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3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
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Build and burn u-boot to SPI flash
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==================================
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1. Build u-boot-spi.bin image
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make P1010RDB_SPIFLASH_config; make
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Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
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Download u-boot.bin to linux and you can find some config files
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under /usr/share such as config_xx.dat. Do below command:
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boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
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u-boot-spi.bin
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to generate u-boot-spi.bin.
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2. Burn u-boot-spi.bin into SPI flash
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=> tftp $loadaddr $uboot-spi
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=> sf erase 0 100000
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=> sf write $loadaddr 0 $filesize
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3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
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CPLD POR setting registers
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==========================
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1. Set POR switch selection register (addr 0xFFB00011) to 0.
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2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
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proper values.
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If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
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switch command by I2C.
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3. Send reset command.
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After reset, the new POR setting will be implemented.
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Two examples are given in below:
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Switch from NOR to NAND boot with default frequency:
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=> i2c dev 0
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=> i2c mw 18 1 f9
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=> i2c mw 18 3 f0
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=> mw.b ffb00011 0
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=> mw.b ffb00017 1
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=> reset
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Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
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=> i2c dev 0
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=> i2c mw 18 1 f1
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=> i2c mw 18 3 f0
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=> mw.b ffb00011 0
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=> mw.b ffb00014 2
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=> mw.b ffb00015 5
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=> mw.b ffb00016 3
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=> mw.b ffb00017 f
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=> reset
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Boot Linux from network using TFTP on P1010RDB
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==============================================
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Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
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=> tftp 1000000 uImage
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=> tftp 2000000 p1010rdb.dtb
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=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
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=> bootm 1000000 3000000 2000000
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Please contact your local field applications engineer or sales representative
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to obtain related documents, such as P1010-RDB User Guide for details.
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