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Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)

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405 SDRAM: - The SDRAM parameters can now be defined in the board
             config file and the 405 SDRAM controller values will
             be calculated upon bootup (see PPChameleonEVB).
             When those settings are not defined in the board
             config file, the register setup will be as it is now,
             so this implementation should not break any current
             design using this code.

             Thanks to Andrea Marson from DAVE for this patch.

440 DDR:   - Added function sdram_tr1_set to auto calculate the
             TR1 value for the DDR.
           - Added ECC support (see p3p440).

Patch by Stefan Roese, 17 Mar 2006
This commit is contained in:
Stefan Roese
2006-03-17 10:28:24 +01:00
parent 05d8dce9d0
commit 62534beb2f
5 changed files with 378 additions and 38 deletions
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10
include/configs/PPChameleonEVB.h
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@@ -139,8 +139,18 @@
#define CFG_I2C_RTC_ADDR 0x68
#define CFG_M41T11_BASE_YEAR 1900
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
#define CFG_SDRAM_CL 2
#define CFG_SDRAM_tRP 20
#define CFG_SDRAM_tRC 65
#define CFG_SDRAM_tRCD 20
#undef CFG_SDRAM_tRFC
/*
* Miscellaneous configurable options
*/