ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
9d01b7872e
commit
6213db78f4
@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
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__udelay(130);
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}
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static void ddr3_leveling(u32 base, const struct emif_regs *regs)
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static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
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{
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if (is_omap54xx())
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omap5_ddr3_leveling(base, regs);
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
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u32 reg, i;
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emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
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/* Update PHY_REG_RDDQS_RATIO */
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emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
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for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
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reg = readl(emif_phy_status++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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}
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/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
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emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
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for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
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reg = readl(emif_phy_status++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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}
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/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
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emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
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for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
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reg = readl(emif_phy_status++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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writel(reg, emif_ext_phy_ctrl_reg++);
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}
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/* Disable Leveling */
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writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
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writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
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writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
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}
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static void ddr3_init(u32 base, const struct emif_regs *regs)
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static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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/* Clear Error Status */
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clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
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clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
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/* Disable refreshed before leveling */
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clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
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EMIF_REG_INITREF_DIS_SHIFT);
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/* Start Full leveling */
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writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
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__udelay(300);
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/* Check for leveling timeout */
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if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
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printf("Leveling timeout on EMIF%d\n", emif_num(base));
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return;
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}
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/* Enable refreshes after leveling */
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clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
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debug("HW leveling success\n");
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/*
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* Update slave ratios in EXT_PHY_CTRLx registers
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* as per HW leveling output
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*/
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update_hwleveling_output(base, regs);
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}
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static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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if (warm_reset())
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emif_reset_phy(base);
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do_ext_phy_settings(base, regs);
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writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
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&emif->emif_sdram_ref_ctrl);
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/* Update timing registers */
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writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
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writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
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writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
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writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
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writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
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writel(regs->zq_config, &emif->emif_zq_config);
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writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
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writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
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writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
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writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
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writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
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writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
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writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
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writel(regs->sdram_config_init, &emif->emif_sdram_config);
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__udelay(1000);
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writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
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if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
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dra7_ddr3_leveling(base, regs);
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}
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static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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@ -269,25 +378,20 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
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writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
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/*
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* The same sequence should work on OMAP5432 as well. But strange that
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* it is not working
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*/
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if (is_dra7xx()) {
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do_ext_phy_settings(base, regs);
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writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
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writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
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writel(regs->sdram_config_init, &emif->emif_sdram_config);
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} else {
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writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
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writel(regs->sdram_config_init, &emif->emif_sdram_config);
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do_ext_phy_settings(base, regs);
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}
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writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
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writel(regs->sdram_config_init, &emif->emif_sdram_config);
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do_ext_phy_settings(base, regs);
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/* enable leveling */
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writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
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omap5_ddr3_leveling(base, regs);
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}
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ddr3_leveling(base, regs);
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static void ddr3_init(u32 base, const struct emif_regs *regs)
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{
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if (is_omap54xx())
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omap5_ddr3_init(base, regs);
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else
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dra7_ddr3_init(base, regs);
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}
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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@ -1075,7 +1179,7 @@ static void do_sdram_init(u32 base)
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if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
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set_lpmode_selfrefresh(base);
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emif_reset_phy(base);
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ddr3_leveling(base, regs);
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omap5_ddr3_leveling(base, regs);
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}
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/* Write to the shadow registers */
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@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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@ -441,7 +447,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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0x00500050,
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0x00000000,
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0x00600020,
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0x40010080,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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@ -450,8 +456,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x10040100,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00330033,
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0x00330033,
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@ -470,7 +482,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x00500050,
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0x00000000,
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0x00600020,
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0x40010080,
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0x40011080,
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0x08102040,
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0x0,
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0x0,
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@ -479,8 +491,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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0x0
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};
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/* Ext phy ctrl 1-35 regs */
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
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0x10040100,
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0x00A400A4,
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0x00A900A9,
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0x00B000B0,
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0x00B000B0,
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0x00A400A4,
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0x00390039,
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0x00320032,
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@ -562,7 +580,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
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*regs = &mr_regs;
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}
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void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
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static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
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{
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u32 *ext_phy_ctrl_base = 0;
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u32 *emif_ext_phy_ctrl_base = 0;
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@ -601,6 +619,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
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}
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}
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static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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u32 *emif_ext_phy_ctrl_base = 0;
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u32 emif_nr;
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const u32 *ext_phy_ctrl_const_regs;
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u32 i, hw_leveling, size;
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emif_nr = (base == EMIF1_BASE) ? 1 : 2;
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hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
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emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
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emif_get_ext_phy_ctrl_const_regs(emif_nr,
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&ext_phy_ctrl_const_regs, &size);
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writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
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writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
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if (!hw_leveling) {
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/*
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* Copy the predefined PHY register values
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* in case of sw leveling
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*/
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for (i = 1; i < 25; i++) {
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writel(ext_phy_ctrl_const_regs[i],
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&emif_ext_phy_ctrl_base[i * 2]);
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writel(ext_phy_ctrl_const_regs[i],
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&emif_ext_phy_ctrl_base[i * 2 + 1]);
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}
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} else {
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/*
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* Write the init value for HW levling to occur
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*/
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for (i = 21; i < 35; i++) {
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writel(ext_phy_ctrl_const_regs[i],
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&emif_ext_phy_ctrl_base[i * 2]);
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writel(ext_phy_ctrl_const_regs[i],
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&emif_ext_phy_ctrl_base[i * 2 + 1]);
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}
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}
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}
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void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
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{
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if (is_omap54xx())
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do_ext_phy_settings_omap5(base, regs);
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else
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do_ext_phy_settings_dra7(base, regs);
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}
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#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
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.max_freq = 532000000,
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@ -44,6 +44,8 @@
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#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
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#define EMIF_REG_FAST_INIT_SHIFT 29
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#define EMIF_REG_FAST_INIT_MASK (1 << 29)
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#define EMIF_REG_LEVLING_TO_SHIFT 4
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#define EMIF_REG_LEVELING_TO_MASK (7 << 4)
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#define EMIF_REG_PHY_DLL_READY_SHIFT 2
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#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
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@ -509,6 +511,13 @@
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#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
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#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
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/* EMIF_PHY_CTRL_36 */
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#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8)
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#define PHY_RDDQS_RATIO_REGS 5
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#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5
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#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10
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/*Leveling Fields */
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#define DDR3_WR_LVL_INT 0x73
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#define DDR3_RD_LVL_INT 0x33
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@ -68,7 +68,13 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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/* Ext phy ctrl regs 1-35 */
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static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00740074,
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0x00780078,
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0x007c007c,
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0x007b007b,
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0x00800080,
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0x00360036,
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0x00340034,
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@ -90,7 +96,7 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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0x00000000,
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0x00600020,
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0x40010080,
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0x40011080,
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0x08102040,
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0x00400040,
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@ -126,6 +132,11 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
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};
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static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00820082,
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0x008b008b,
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0x00800080,
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0x007e007e,
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0x00800080,
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0x00370037,
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0x00390039,
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@ -145,7 +156,7 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
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0x00000000,
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0x00600020,
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0x40010080,
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0x40011080,
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0x08102040,
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0x00400040,
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