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Merge with git://www.denx.de/git/u-boot.git

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This commit is contained in:
Markus Klotzbuecher 2007-04-23 13:17:22 +02:00 committed by Markus Klotzbuecher
commit 61ea75aa07
280 changed files with 14968 additions and 5187 deletions
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1138
CHANGELOG
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File diff suppressed because it is too large Load Diff

5
CREDITS
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@ -474,3 +474,8 @@ N: Timur Tabi
E: timur@freescale.com
D: Support for MPC8349E-mITX
W: www.freescale.com
N: Michal Simek
E: monstr@monstr.eu
D: Support for Microblaze, ML401, XUPV2P board
W: www.monstr.eu

26
MAINTAINERS
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@ -257,15 +257,6 @@ Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied &
supported core modules
- see http://www.arm.com
/products/DevTools
/Hardware_Platforms.html
versatile ARM926EJ-S
versatile ARM926EJ-S
Denis Peter <d.peter@mpl.ch>
MIP405 PPC4xx
@ -444,6 +435,9 @@ Gary Jennejohn <gj@denx.de>
smdk2400 ARM920T
trab ARM920T
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
@ -461,6 +455,15 @@ Rolf Offermanns <rof@sysgo.de>
shannon SA1100
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied &
supported core modules
-see http://www.arm.com
/products/DevTools
/Hardware_Platforms.html
versatile ARM926EJ-S
versatile ARM926EJ-S
Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
@ -564,6 +567,11 @@ Yasushi Shoji <yashi@atmark-techno.com>
SUZAKU MicroBlaze
Michal Simek <monstr@monstr.eu>
ML401 MicroBlaze
XUPV2P MicroBlaze
#########################################################################
# Coldfire Systems: #
# #

3
MAKEALL
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@ -155,6 +155,7 @@ LIST_85xx=" \
LIST_74xx=" \
DB64360 DB64460 EVB64260 P3G4 \
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
mpc7448hpc2
"
LIST_7xx=" \
@ -293,7 +294,7 @@ LIST_nios2=" \
#########################################################################
LIST_microblaze=" \
suzaku
suzaku ml401 xupv2p
"
#########################################################################

71
Makefile
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@ -149,7 +149,7 @@ ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-uclinux-
endif
ifeq ($(ARCH),avr32)
CROSS_COMPILE = avr32-
CROSS_COMPILE = avr32-linux-
endif
endif
endif
@ -219,6 +219,7 @@ LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
LIBS += libfdt/libfdt.a
LIBS += $(BOARDLIBS)
LIBS := $(addprefix $(obj),$(LIBS))
@ -430,6 +431,7 @@ inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
lite5200b_config \
lite5200b_PM_config \
lite5200b_LOWBOOT_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/icecube
@ -438,6 +440,10 @@ lite5200b_LOWBOOT_config: unconfig
@ echo "... DDR memory revision"
@ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
@ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
@[ -z "$(findstring _PM_,$@)" ] || \
{ echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \
echo "... with power management (low-power mode) support" ; \
}
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
@ -1193,44 +1199,31 @@ PPChameleonEVB_HI_33_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
rainier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
rainier_nand_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)nand_spl
@mkdir -p $(obj)board/amcc/sequoia
@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
@echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
sequoia_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
sequoia_config \
rainier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
sequoia_nand_config: unconfig
sequoia_nand_config \
rainier_nand_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)nand_spl
@mkdir -p $(obj)board/amcc/sequoia
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "Compile NAND boot image for sequoia"
@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sc3_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sc3
sycamore_config: unconfig
@$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
@ -1247,8 +1240,10 @@ W7OLMC_config \
W7OLMG_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx w7o
walnut_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx walnut amcc
# Walnut & Sycamore images are identical (recognized via PVR)
walnut_config \
sycamore_config: unconfig
@$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
WUH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
@ -1256,12 +1251,11 @@ WUH405_config: unconfig
XPEDITE1K_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
yosemite_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
yosemite_config \
yellowstone_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_YELLOWSTONE" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a yosemite ppc ppc4xx yosemite amcc
yucca_config: unconfig
@ -1829,6 +1823,9 @@ EVB64260_config \
EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
@ -2361,6 +2358,16 @@ suzaku_config: unconfig
@echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
ml401_config: unconfig
@ >include/config.h
@echo "#define CONFIG_ML401 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze ml401 xilinx
xupv2p_config: unconfig
@ >include/config.h
@echo "#define CONFIG_XUPV2P 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze xupv2p xilinx
#########################################################################
## Blackfin
#########################################################################

55
README
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@ -164,6 +164,7 @@ Directory Hierarchy:
- lib_mips Files generic to MIPS architecture
- lib_nios Files generic to NIOS architecture
- lib_ppc Files generic to PowerPC architecture
- libfdt Library files to support flattened device trees
- net Networking code
- post Power On Self Test
- rtc Real Time Clock drivers
@ -431,12 +432,23 @@ The following options need to be configured:
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_OF_FLAT_TREE
CONFIG_OF_LIBFDT / CONFIG_OF_FLAT_TREE
New kernel versions are expecting firmware settings to be
passed using flat open firmware trees.
The environment variable "disable_of", when set, disables this
functionality.
passed using flattened device trees (based on open firmware
concepts).
CONFIG_OF_LIBFDT
* New libfdt-based support
* Adds the "fdt" command
* The bootm command does _not_ modify the fdt
CONFIG_OF_FLAT_TREE
* Deprecated, see CONFIG_OF_LIBFDT
* Original ft_build.c-based support
* Automatically modifies the dft as part of the bootm command
* The environment variable "disable_of", when set,
disables this functionality.
CONFIG_OF_FLAT_TREE_MAX_SIZE
@ -449,13 +461,16 @@ The following options need to be configured:
CONFIG_OF_HAS_BD_T
The resulting flat device tree will have a copy of the bd_t.
Space should be pre-allocated in the dts for the bd_t.
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of the bd_t. Space should be
pre-allocated in the dts for the bd_t.
CONFIG_OF_HAS_UBOOT_ENV
The resulting flat device tree will have a copy of u-boot's
environment variables
* CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
* CONFIG_OF_FLAT_TREE - The resulting flat device tree
will have a copy of u-boot's environment variables
CONFIG_OF_BOARD_SETUP
@ -722,6 +737,8 @@ The following options need to be configured:
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET)
Other Commands:
fdt (flattened device tree) command: CONFIG_OF_LIBFDT
Note: Don't enable the "icache" and "dcache" commands
(configuration option CFG_CMD_CACHE) unless you know
@ -2444,17 +2461,17 @@ configurations; the following names are supported:
csb272_config lwmon_config sbc8260_config
CU824_config MBX860T_config sbc8560_33_config
DUET_ADS_config MBX_config sbc8560_66_config
EBONY_config MPC8260ADS_config SM850_config
ELPT860_config MPC8540ADS_config SPD823TS_config
ESTEEM192E_config MPC8540EVAL_config stxgp3_config
ETX094_config MPC8560ADS_config SXNI855T_config
FADS823_config NETVIA_config TQM823L_config
FADS850SAR_config omap1510inn_config TQM850L_config
FADS860T_config omap1610h2_config TQM855L_config
FPS850L_config omap1610inn_config TQM860L_config
omap5912osk_config walnut_config
omap2420h4_config Yukon8220_config
ZPC1900_config
EBONY_config mpc7448hpc2_config SM850_config
ELPT860_config MPC8260ADS_config SPD823TS_config
ESTEEM192E_config MPC8540ADS_config stxgp3_config
ETX094_config MPC8540EVAL_config SXNI855T_config
FADS823_config NMPC8560ADS_config TQM823L_config
FADS850SAR_config NETVIA_config TQM850L_config
FADS860T_config omap1510inn_config TQM855L_config
FPS850L_config omap1610h2_config TQM860L_config
omap1610inn_config walnut_config
omap5912osk_config Yukon8220_config
omap2420h4_config ZPC1900_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for

2
avr32_config.mk
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@ -21,5 +21,5 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
PLATFORM_LDFLAGS += --relax

2
board/AtmarkTechno/suzaku/suzaku.c
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@ -24,7 +24,7 @@
/* This is a board specific file. It's OK to include board specific
* header files */
#include <asm/suzaku.h>
#include <config.h>
void do_reset(void)
{

3
board/AtmarkTechno/suzaku/u-boot.lds
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@ -61,6 +61,7 @@ SECTIONS
{
__bss_start = .;
*(.bss)
__bss_start = .;
__bss_end = .;
}
__end = . ;
}

20
board/amcc/acadia/Makefile
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@ -23,25 +23,29 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o cpr.o memory.o
COBJS = $(BOARD).o cpr.o memory.o
SOBJS =
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak .depend *~
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude $(obj).depend
#########################################################################

61
board/amcc/acadia/acadia.c
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@ -26,10 +26,7 @@
extern void board_pll_init_f(void);
/* Some specific Acadia Defines */
#define CPLD_BASE 0x80000000
void liveoak_gpio_init(void)
static void acadia_gpio_init(void)
{
/*
* GPIO0 setup (select GPIO or alternate function)
@ -54,62 +51,16 @@ void liveoak_gpio_init(void)
out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
}
#if 0 /* test-only: not called at all??? */
void ext_bus_cntlr_init(void)
{
#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
mtebc(pb4ap, EBC_PB4AP);
mtebc(pb4cr, EBC_PB4CR);
#endif
}
#endif
int board_early_init_f(void)
{
unsigned int reg;
#if 0 /* test-only */
/*
* If CRAM memory and SPI/NAND boot, and if the CRAM memory is
* already initialized by the pre-loader then we can't reinitialize
* CPR registers, GPIO registers and EBC registers as this will
* have the effect of un-initializing CRAM.
*/
spr_reg = (volatile unsigned long) mfspr(SPRG7);
if (spr_reg != LOAK_CRAM) { /* != CRAM */
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
liveoak_gpio_init();
ext_bus_cntlr_init();
mtebc(pb1ap, CFG_EBC_PB1AP);
mtebc(pb1cr, CFG_EBC_PB1CR);
mtebc(pb2ap, CFG_EBC_PB2AP);
mtebc(pb2cr, CFG_EBC_PB2CR);
}
#else
board_pll_init_f();
liveoak_gpio_init();
/* ext_bus_cntlr_init(); */
#endif
#if 0 /* test-only (orig) */
/*
* If we boot from NAND Flash, we are running in
* RAM, so disable the EBC_CS0 so that it goes back
* to the NOR Flash. It will be enabled later
* for the NAND Flash on EBC_CS1
*/
mfsdr(sdrultra0, reg);
mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
#endif
#if 0 /* test-only */
/* configure for NAND */
mfsdr(sdrultra0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
#endif
acadia_gpio_init();
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
@ -128,7 +79,7 @@ int board_early_init_f(void)
int misc_init_f(void)
{
/* Set EPLD to take PHY out of reset */
out8(CPLD_BASE + 0x05, 0x00);
out8(CFG_CPLD_BASE + 0x05, 0x00);
udelay(100000);
return 0;

13
board/amcc/acadia/config.mk
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@ -1,5 +1,5 @@
#
# (C) Copyright 2000
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,21 +21,10 @@
# MA 02111-1307 USA
#
sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFC0000
endif
ifeq ($(CONFIG_NAND_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
ifeq ($(CONFIG_SPI_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
PAD_TO = 0x00840000
endif
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

34
board/amcc/acadia/cpr.c
View File

@ -76,19 +76,19 @@ void board_pll_init_f(void)
* | UART0 | 28.57 | 7 (0x07)|
* | UART1 | 28.57 | 7 (0x07)|
* | DAC | 28.57 | 7 (0xA7)|
* | ADC | 4 | 50 (0x32)|
* | ADC | 4 | 50 (0x32)|
* | PWM | 28.57 | 7 (0x07)|
* | EMAC | 4 | 50 (0x32)|
* -----------------------------------
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
}
@ -117,11 +117,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
}
@ -143,20 +143,20 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
#endif /* CPU_<speed>_405EZ */
#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk (void)
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
@ -192,4 +192,4 @@ unsigned long get_tbclk (void)
return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */

1108
board/amcc/acadia/flash.c
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File diff suppressed because it is too large Load Diff

551
board/amcc/acadia/memory.c
View File

@ -21,529 +21,80 @@
* MA 02111-1307 USA
*/
/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define CRAM_BANK0_BASE 0x0
#define CRAM_DIDR 0x00100000
#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
#define CRAM_DEVID_NOT_SUPPORTED 0x00000000
#define PSRAM_PASS 0x50415353 /* "PASS" */
#define PSRAM_FAIL 0x4641494C /* "FAIL" */
static u32 is_cram_inited(void);
static u32 is_cram(void);
static long int cram_init(u32);
static void cram_bcr_write(u32);
void udelay (unsigned long);
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
volatile unsigned long spr_reg;
/*
* If CRAM not initialized or CRAM looks initialized because this
* is after a warm reboot then set SPRG7 to indicate CRAM needs
* initialization. Note that CRAM is initialized by the SPI and
* NAND preloader.
*/
spr_reg = (volatile unsigned long) mfspr(SPRG6);
if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
mtspr(SPRG7, LOAK_NONE); /* "NONE" */
}
#if 1
/*
* When running the NAND SPL, the normal EBC configuration is not
* done, so We need to enable EPLD access on EBC_CS_2 and the memory
* on EBC_CS_3
*/
/* Enable CPLD - Needed for PSRAM Access */
/* Init SDRAM by setting EBC Bank 3 for PSRAM */
mtebc(pb1ap, CFG_EBC_PB1AP);
mtebc(pb1cr, CFG_EBC_PB1CR);
mtebc(pb2ap, CFG_EBC_PB2AP);
mtebc(pb2cr, CFG_EBC_PB2CR);
/* pre-boot loader code: we are in OCM */
mtspr(SPRG6, LOAK_SPL); /* "SPL " */
mtspr(SPRG7, LOAK_OCM); /* "OCM " */
#endif
return;
}
static void cram_bcr_write(u32 wr_val)
{
u32 tmp_reg;
u32 val;
volatile u32 gpio_reg;
wr_val <<= 2;
/* # Program CRAM write */
/* set CRAM_CRE to 1 */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
/*
* set CRAM_CRE = 0x1
* set wr_val = wr_val << 2
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
wr_val = wr_val << 2;
/* wr_val = 0x1c048; */
/* Write BCR to CRAM on CS1 */
out32(wr_val + 0x00200000, 0);
debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
/*
* # stop PLL clock before programming CRAM
* set EPLD0_MUX_CTL.OESPR3 = 1
* delay 2
*/
/* Write BCR to CRAM on CS2 */
out32(wr_val + 0x02200000, 0);
debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
/*
* # CS1
* read 0x00200000
* #shift 2 bit left before write
* set val = wr_val + 0x00200000
* write dmem val 0
* read 0x00200000 val
* print val/8x
*/
tmp_reg = in32(0x00200000);
val = wr_val + 0x00200000;
/* val = 0x0021c048; */
out32(val, 0x0000);
udelay(100000);
val = in32(0x00200000);
sync();
eieio();
debug("CRAM VAL: %x for CS1 ", val);
/* set CRAM_CRE back to 0 (normal operation) */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
/*
* # CS2
* read 0x02200000
* #shift 2 bit left before write
* set val = wr_val + 0x02200000
* write dmem val 0
* read 0x02200000 val
* print val/8x
*/
tmp_reg = in32(0x02200000);
val = wr_val + 0x02200000;
/* val = 0x0221c048; */
out32(val, 0x0000);
udelay(100000);
val = in32(0x02200000);
debug("CRAM VAL: %x for CS2 ", val);
/*
* # Start PLL clock before programming CRAM
* set EPLD0_MUX_CTL.OESPR3 = 0
*/
/*
* set CRAMCR = 0x1
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
/*
* # read CRAM config BCR ( bit19:18 = 10b )
* #read 0x00200000
* # 1001_1001_0001_1111 ( 991f ) =>
* #10_0110_0100_0111_1100 => 2647c => 0022647c
* #0011_0010_0011_1110 (323e)
* #
*/
/*
* set EPLD0_MUX_CTL.CRAMCR = 0x0
*/
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
return;
}
static u32 is_cram_inited()
{
volatile unsigned long spr_reg;
/*
* If CRAM is initialized already, then don't reinitialize it again.
* In the case of NAND boot and SPI boot, CRAM will already be
* initialized by the pre-loader
*/
spr_reg = (volatile unsigned long) mfspr(SPRG7);
if (spr_reg == LOAK_CRAM) {
return 1;
} else {
return 0;
}
}
/******
* return 0 if not CRAM
* return 1 if CRAM and it's already inited by preloader
* else return cram_id (CRAM Device Identification Register)
******/
static u32 is_cram(void)
{
u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
volatile u32 gpio_reg;
volatile u32 cram_id = 0;
if (is_cram_inited() == 1) {
/* this is CRAM and it is already inited (by preloader) */
cram_id = 1;
} else {
/*
* # CRAM CLOCK
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 0
* set GPIO0_OR.G8 = 0
*/
gpio_reg = in32(GPIO0_TCR);
gpio_TCR = gpio_reg;
out32(GPIO0_TCR, gpio_reg | 0x00800000);
gpio_reg = in32(GPIO0_OSRL);
gpio_OSRL = gpio_reg;
out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
gpio_reg = in32(GPIO0_OR);
gpio_OR = gpio_reg;
out32(GPIO0_OR, gpio_reg & 0xff7fffff);
/*
* # CRAM Addreaa Valid
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 0
* set GPIO0_OR.G10 = 0
*/
gpio_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, gpio_reg | 0x00200000);
gpio_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
gpio_reg = in32(GPIO0_OR);
out32(GPIO0_OR, gpio_reg & 0xffdfffff);
/*
* # config input (EBC_WAIT)
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
gpio_reg = in32(GPIO0_ISR1L);
gpio_ISR1L = gpio_reg;
out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
gpio_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
/*
* Enable CRE to read Registers
* set GPIO0_TCR.21 = 1
* set GPIO1_OR.21 = 1
*/
gpio_reg = in32(GPIO1_TCR);
out32(GPIO1_TCR, gpio_reg | 0x00000400);
gpio_reg = in32(GPIO1_OR);
out32(GPIO1_OR, gpio_reg | 0x00000400);
/* Read Version ID */
cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
udelay(100000);
asm volatile(" sync");
asm volatile(" eieio");
debug("Cram ID: %X ", cram_id);
switch (cram_id) {
case MICRON_MT45W8MW16BGX_CRAM_ID:
case MICRON_MT45W8MW16BGX_CRAM_ID2:
/* supported CRAM vendor/part */
break;
case CRAM_DEVID_NOT_SUPPORTED:
default:
/* check for DIDR Vendor ID of Micron */
if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
MICRON_DIDR_VENDOR_ID)
{
/* supported CRAM vendor */
break;
}
/* this is not CRAM or not supported CRAM vendor/part */
cram_id = 0;
/*
* reset the GPIO registers to the values that were
* there before this routine
*/
out32(GPIO0_TCR, gpio_TCR);
out32(GPIO0_OSRL, gpio_OSRL);
out32(GPIO0_OR, gpio_OR);
out32(GPIO0_ISR1L, gpio_ISR1L);
break;
}
}
return cram_id;
}
static long int cram_init(u32 already_inited)
{
volatile u32 tmp_reg;
u32 cram_wr_val;
if (already_inited == 0) return 0;
/*
* If CRAM is initialized already, then don't reinitialize it again.
* In the case of NAND boot and SPI boot, CRAM will already be
* initialized by the pre-loader
*/
if (already_inited != 1) {
/*
* #o CRAM Card
* # - CRAMCRE @reg16 = 1; for CRAM to use
* # - CRAMCRE @reg16 = 0; for CRAM to program
*
* # enable CRAM SEL, move from setEPLD.cmd
* set EPLD0_MUX_CTL.OECRAM = 0
* set EPLD0_MUX_CTL.CRAMCR = 1
* set EPLD0_ETHRSTBOOT.SLCRAM = 0
* #end
*/
/*
* #1. EBC need to program READY, CLK, ADV for ASync mode
* # config output
*/
/*
* # CRAM CLOCK
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 0
* set GPIO0_OR.G8 = 0
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00800000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
tmp_reg = in32(GPIO0_OR);
out32(GPIO0_OR, tmp_reg & 0xff7fffff);
/*
* # CRAM Addreaa Valid
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 0
* set GPIO0_OR.G10 = 0
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00200000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
tmp_reg = in32(GPIO0_OR);
out32(GPIO0_OR, tmp_reg & 0xffdfffff);
/*
* # config input (EBC_WAIT)
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
tmp_reg = in32(GPIO0_ISR1L);
out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
/*
* # config CS4 from GPIO
* set GPIO0_TCR.G0 = 1
* set GPIO0_OSRL.G0 = 1
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x80000000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x40000000);
/*
* #2. EBC in Async mode
* # set EBC0_PB1AP = 0x078f0ec0
* set EBC0_PB1AP = 0x078f1ec0
* set EBC0_PB2AP = 0x078f1ec0
*/
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
/*
* #set EBC0_PB1CR = 0x000bc000
* #enable CS2 for CRAM
* set EBC0_PB2CR = 0x020bc000
*/
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
/*
* #3. set CRAM in Sync mode
* #exec cm_bcr_write.cmd { 0x701f }
* #3. set CRAM in Sync mode (full drv strength)
* exec cm_bcr_write.cmd { 0x701F }
*/
cram_wr_val = 0x7012; /* CRAM burst setting */
cram_bcr_write(cram_wr_val);
/*
* #4. EBC in Sync mode
* #set EBC0_PB1AP = 0x9f800fc0
* #set EBC0_PB1AP = 0x900001c0
* set EBC0_PB2AP = 0x9C0201c0
* set EBC0_PB2AP = 0x9C0201c0
*/
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
/*
* #5. EBC need to program READY, CLK, ADV for Sync mode
* # config output
* set GPIO0_TCR.G8 = 1
* set GPIO0_OSRL.G8 = 1
* set GPIO0_TCR.G10 = 1
* set GPIO0_OSRL.G10 = 1
*/
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00800000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x00004000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg | 0x00200000);
tmp_reg = in32(GPIO0_OSRL);
out32(GPIO0_OSRL, tmp_reg | 0x00000400);
/*
* # config input
* set GPIO0_ISR1L.G9 = 1
* set GPIO0_TCR.G9 = 0
*/
tmp_reg = in32(GPIO0_ISR1L);
out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
tmp_reg = in32(GPIO0_TCR);
out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
/*
* # config EBC to use RDY
* set SDR0_ULTRA0.EBCREN = 1
*/
mfsdr(sdrultra0, tmp_reg);
mtsdr(sdrultra0, tmp_reg | 0x04000000);
/*
* set EPLD0_MUX_CTL.OESPR3 = 0
*/
mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
} /* if (already_inited != 1) */
return (64 * 1024 * 1024);
}
/******
* return 0 if not PSRAM
* return 1 if is PSRAM
******/
static int is_psram(u32 addr)
{
u32 test_pattern = 0xdeadbeef;
volatile u32 readback;
if (addr == CFG_SDRAM_BASE) {
/* This is to temp enable OE for PSRAM */
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
udelay(10000);
}
out32(addr, test_pattern);
asm volatile(" sync");
asm volatile(" eieio");
readback = (volatile u32) in32(addr);
asm volatile(" sync");
asm volatile(" eieio");
if (readback == test_pattern) {
return 1;
} else {
return 0;
}
}
static long int psram_init(void)
{
u32 readback;
long psramsize = 0;
int i;
/* This is to temp enable OE for PSRAM */
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
udelay(10000);
/*
* PSRAM bank 1: read then write to address 0x00000000
*/
for (i = 0; i < 100; i++) {
if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
readback = PSRAM_PASS;
} else {
readback = PSRAM_FAIL;
break;
}
}
if (readback == PSRAM_PASS) {
debug("psram_init(bank0): pass\n");
psramsize = (16 * 1024 * 1024);
} else {
debug("psram_init(bank0): fail\n");
return 0;
}
#if 0
/*
* PSRAM bank 1: read then write to address 0x01000000
*/
for (i = 0; i < 100; i++) {
if (is_psram((1 << 24) + (i*256)) == 1) {
readback = PSRAM_PASS;
} else {
readback = PSRAM_FAIL;
break;
}
}
if (readback == PSRAM_PASS) {
debug("psram_init(bank1): pass\n");
psramsize = psramsize + (16 * 1024 * 1024);
}
#endif
mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
return psramsize;
}
long int initdram(int board_type)
{
long int sram_size;
u32 cram_inited;
u32 val;
/* Determine Attached Memory Expansion Card*/
cram_inited = is_cram();
if (cram_inited != 0) { /* CRAM */
debug("CRAM Expansion Card attached\n");
sram_size = cram_init(cram_inited);
} else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
debug("PSRAM Expansion Card attached\n");
sram_size = psram_init();
} else { /* no SRAM */
debug("No Memory Card Attached!!\n");
sram_size = 0;
}
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
return sram_size;
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | 0x04000000);
return (CFG_MBYTES_RAM << 20);
}
int testdram(void)

13
board/amcc/acadia/u-boot.lds
View File

@ -62,19 +62,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)

1
board/amcc/bamboo/bamboo.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <spd_sdram.h>
#include <ppc440.h>
#include "bamboo.h"

10
board/amcc/bamboo/bamboo.h
View File

@ -264,19 +264,9 @@
#define TRUE 1
#define FALSE 0
#define GPIO_GROUP_MAX 2
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
/* For the other GPIO number, you must shift */
#define GPIO0 0
#define GPIO1 1
/*#define MAX_SELECTION_NB CORE_NB */
#define MAX_CORE_SELECT_NB 22

105
board/amcc/katmai/cmd_katmai.c
View File

@ -27,6 +27,9 @@
#include <i2c.h>
#include <asm/byteorder.h>
#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */
#define DEBUG
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
@ -49,55 +52,28 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
chip = IIC0_ALT_BOOTPROM_ADDR;
do {
printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0))
nbytes=0;
strcpy(sysClock, console_buffer);
} while (nbytes == 0);
/* on Katmai SysClk is always 33MHz */
strcpy(sysClock, "33");
do {
if (strcmp(sysClock, "66") == 0) {
printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
} else {
#ifdef CONFIG_STRESS
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
}
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "533") != 0)
if ((strcmp(console_buffer, "400") != 0) &&
(strcmp(console_buffer, "500") != 0) &&
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
&& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
} else {
if ((strcmp(console_buffer, "400") != 0) &
(strcmp(console_buffer, "500") != 0) &
(strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
& (strcmp(console_buffer, "667") != 0)
#endif
) {
nbytes = 0;
}
) {
nbytes = 0;
}
strcpy(cpuClock, console_buffer);
@ -124,13 +100,13 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
if (strcmp(cpuClock, "400") == 0) {
if ((strcmp(console_buffer, "100") != 0) &
if ((strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
if ((strcmp(console_buffer, "133") != 0) &
if ((strcmp(console_buffer, "133") != 0) &&
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
@ -147,9 +123,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (strcmp(console_buffer, "quit") == 0)
return 0;
if ((strcmp(console_buffer, "33") != 0) &
(strcmp(console_buffer, "66") != 0) &
(strcmp(console_buffer, "100") != 0) &
if ((strcmp(console_buffer, "33") != 0) &&
(strcmp(console_buffer, "66") != 0) &&
(strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
@ -176,11 +152,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
if ((strcmp(cpuClock, "400") == 0) &
if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
@ -189,42 +165,16 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
if ((strcmp(cpuClock, "667") == 0) &
if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
#endif
}
if (strcmp(sysClock, "66") == 0) {
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "100") == 0))
data = 0x84706206;
if ((strcmp(cpuClock, "400") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x847062c6;
if ((strcmp(cpuClock, "533") == 0))
data = 0x85708206;
#ifdef CONFIG_STRESS
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "133") == 0))
data = 0x8570a256;
if ((strcmp(cpuClock, "667") == 0) &
(strcmp(plbClock, "166") == 0))
data = 0x8570a206;
#endif
}
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
@ -233,19 +183,20 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
data = 0x00000701;
data = 0x000007E1;
if (strcmp(pcixClock, "66") == 0)
data = 0x00000601;
data = 0x000006E1;
if (strcmp(pcixClock, "100") == 0)
data = 0x00000501;
data = 0x000005E1;
if (strcmp(pcixClock, "133") == 0)
data = 0x00000401;
data = 0x000004E1;
if (strcmp(plbClock, "166") == 0)
data |= 0x05950000;
/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */
data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */
else
data |= 0x05A50000;

2
board/amcc/katmai/init.S
View File

@ -103,7 +103,7 @@ tlbtabB:
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)

1
board/amcc/katmai/katmai.c
View File

@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
#include <asm-ppc/gpio.h>
#include "../cpu/ppc4xx/440spe_pcie.h"

4
board/amcc/sequoia/sequoia.c
View File

@ -363,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
rev = *(u8 *)(CFG_BCSR_BASE + 0);
val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {

2
board/atmel/atstk1000/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(BOARD).a
COBJS := $(BOARD).o flash.o
COBJS := $(BOARD).o flash.o eth.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

24
board/atmel/atstk1000/atstk1000.c
View File

@ -23,6 +23,8 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
DECLARE_GLOBAL_DATA_PTR;
@ -40,9 +42,27 @@ static const struct sdram_info sdram = {
.txsr = 5,
};
void board_init_memories(void)
int board_early_init_f(void)
{
gd->sdram_size = sdram_init(&sdram);
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
gpio_enable_ebi();
gpio_enable_usart1();
#if defined(CONFIG_MACB)
gpio_enable_macb0();
gpio_enable_macb1();
#endif
#if defined(CONFIG_MMC)
gpio_enable_mmci();
#endif
return 0;
}
long int initdram(int board_type)
{
return sdram_init(&sdram);
}
void board_init_info(void)

22
cpu/at32ap/at32ap7000/hebi.c → board/atmel/atstk1000/eth.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2006 Atmel Corporation
* Copyright (C) 2005-2006 Atmel Corporation
*
* Ethernet initialization for the ATSTK1000 starterkit
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,18 +23,16 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/memory-map.h>
#include <asm/arch/platform.h>
void cpu_enable_sdram(void)
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET)
void atstk1000_eth_initialize(bd_t *bi)
{
const struct device *hmatrix;
int id = 0;
hmatrix = get_device(DEVICE_HMATRIX);
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(hmatrix, SFR4, 1 << 1);
macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]);
macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]);
}
#endif

2
board/atmel/atstk1000/flash.c
View File

@ -57,7 +57,7 @@ unsigned long flash_init(void)
gd->bd->bi_flashstart = CFG_FLASH_BASE;
gd->bd->bi_flashsize = CFG_FLASH_SIZE;
gd->bd->bi_flashoffset = __edata_lma - _text;
gd->bd->bi_flashoffset = _edata - _text;
flash_info[0].size = CFG_FLASH_SIZE;
flash_info[0].sector_count = 135;

21
board/atmel/atstk1000/u-boot.lds
View File

@ -40,35 +40,38 @@ SECTIONS
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
. = ALIGN(8);
.rodata : {
*(.rodata)
*(.rodata.*)
}
_etext = .;
__data_lma = ALIGN(8);
. = 0x24000000;
. = ALIGN(8);
_data = .;
.data : AT(__data_lma) {
.data : {
*(.data)
*(.data.*)
}
. = ALIGN(4);
__u_boot_cmd_start = .;
__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
.u_boot_cmd : AT(__u_boot_cmd_lma) {
.u_boot_cmd : {
KEEP(*(.u_boot_cmd))
}
__u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;
.got : {
*(.got)
}
_egot = .;
. = ALIGN(8);
_edata = .;
__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
.bss : AT(__edata_lma) {
.bss : {
*(.bss)
*(.bss.*)
}

2
board/bf533-ezkit/Makefile
View File

@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
# Copyright (c) 2007 Analog Device Inc.
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.

6
board/bf533-ezkit/bf533-ezkit.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - ezkit533.c
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>

8
board/bf533-ezkit/flash-defines.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash-defines.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __FLASHDEFINES_H__
@ -60,7 +60,7 @@ void reset_flash(void);
int erase_flash(void);
int erase_block_flash(int, unsigned long);
void unlock_flash(long lOffset);
int write_data(long lStart, long lCount, long lStride, int *pnData);
int write_data(long lStart, long lCount, uchar *pnData);
int FillData(long lStart, long lCount, long lStride, int *pnData);
int read_data(long lStart, long lCount, long lStride, int *pnData);
int read_flash(long nOffset, int *pnValue);

85
board/bf533-ezkit/flash.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash.c Flash driver for PSD4256GV
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
*
* (C) Copyright 2000-2004
@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <asm/io.h>
@ -178,63 +178,66 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int ret;
ret = write_data(addr, cnt, 1, (int *)src);
int d;
if (addr % 2) {
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
d = (int)((d & 0x00FF) | (*src++ << 8));
ret = write_data(addr - 1, 2, (uchar *) & d);
if (ret == FLASH_FAIL)
return ERR_NOT_ERASED;
ret = write_data(addr + 1, cnt - 1, src);
} else
ret = write_data(addr, cnt, src);
if (ret == FLASH_FAIL)
return ERR_NOT_ERASED;
return FLASH_SUCCESS;
}
int write_data(long lStart, long lCount, long lStride, int *pnData)
int write_data(long lStart, long lCount, uchar * pnData)
{
long i = 0;
int j = 0;
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
int d;
int iShift = 0;
int iNumWords = 2;
int nLeftover = lCount % 4;
int nSector = 0;
int flag = 0;
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
for (iShift = 0, j = 0; (j < iNumWords);
j++, ulOffset += (lStride * 2)) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND)) {
printf
("Invalid locations, Try writing to another location \n");
return FLASH_FAIL;
}
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
iShift += 16;
}
if (lCount % 2) {
flag = 1;
lCount = lCount - 1;
}
if (nLeftover > 0) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash already programmed. Please erase to reprogram \n");
printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if (write_flash(ulOffset, pnData[i]) < 0) {
d = (int)(pnData[i] | pnData[i + 1] << 8);
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
if ((i > 0) && (!(i % AFP_SectorSize2)))
printf(".");
}
if (flag) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | (d & 0xFF00));
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}

6
board/bf533-ezkit/psd4256.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - psd4256.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*

2
board/bf533-stamp/Makefile
View File

@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
# Copyright (c) 2007 Analog Device Inc.
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.

6
board/bf533-stamp/bf533-stamp.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - stamp.c STAMP board specific routines
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>

6
board/bf533-stamp/bf533-stamp.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - stamp.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __STAMP_H__

6
board/bf537-stamp/bf537-stamp.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - BF537.c
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>

6
board/bf537-stamp/flash-defines.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash-defines.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __FLASHDEFINES_H__

6
board/bf537-stamp/flash.c
View File

@ -1,7 +1,7 @@
/*
* U-boot - flash.c Flash driver for PSD4256GV
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
*
* (C) Copyright 2000-2004
@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <malloc.h>

6
board/bf561-ezkit/bf561-ezkit.c
View File

@ -2,7 +2,7 @@
* U-boot - ezkit561.c
*
* Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>

161
board/mpc8641hpcn/pixis.c → board/freescale/common/pixis.c
View File

@ -23,14 +23,25 @@
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <mpc86xx.h>
#include "pixis.h"
static ulong strfractoint(uchar *strptr);
/*
* Simple board reset.
*/
void pixis_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void)
}
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
u8 tmp;
@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
diswd, 1, 0, disable_watchdog,
diswd, 1, 0, pixis_disable_watchdog_cmd,
"diswd - Disable watchdog timer \n",
NULL);
@ -263,7 +275,7 @@ U_BOOT_CMD(
* input: strptr i.e. argv[2]
*/
ulong strfractoint(uchar *strptr)
static ulong strfractoint(uchar *strptr)
{
int i, j, retval;
int mulconst;
@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr)
return retval;
}
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
pixis_reset();
/* not reached */
}
if (strcmp(argv[1], "cf") == 0) {
/*
* Reset with frequency changed:
* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
*/
if (argc < 5) {
puts(cmdtp->usage);
return 1;
}
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
set_px_go();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[1], "altbank") == 0) {
/*
* Reset using alternate flash bank:
*/
if (argv[2] == 0) {
/*
* Reset from alternate bank without changing
* frequency and without watchdog timer enabled.
* altbank
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2) {
puts(cmdtp->usage);
return 1;
}
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank.\n");
set_px_go();
} else if (strcmp(argv[2], "cf") == 0) {
/*
* Reset with frequency changed
* altbank cf <SYSCLK freq> <COREPLL ratio>
* <MPXPLL ratio>
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
puts("to boot from the other bank.\n");
set_px_go_with_watchdog();
} else {
puts(cmdtp->usage);
return 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[2], "wd") == 0) {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled:
* altbank wd
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board to boot from the other bank.\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
puts(cmdtp->usage);
return 1;
}
} else {
puts(cmdtp->usage);
return 1;
}
return 0;
}
U_BOOT_CMD(
pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
"pixis_reset - Reset the board using the FPGA sequencer\n",
" pixis_reset\n"
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);

4
board/mpc8641hpcn/pixis.h → board/freescale/common/pixis.h
View File

@ -20,6 +20,7 @@
* MA 02111-1307 USA
*/
extern void pixis_reset(void);
extern int set_px_sysclk(ulong sysclk);
extern int set_px_mpxpll(ulong mpxpll);
extern int set_px_corepll(ulong corepll);
@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set);
extern void set_altbank(void);
extern void set_px_go(void);
extern void set_px_go_with_watchdog(void);
extern int disable_watchdog(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[]);
extern ulong strfractoint(uchar *strptr);

49
board/icecube/icecube.c
View File

@ -42,6 +42,53 @@
#include "mt48lc16m16a2-75.h"
# endif
#endif
#ifdef CONFIG_LITE5200B_PM
/* u-boot part of low-power mode implementation */
#define SAVED_ADDR (*(void **)0x00000000)
#define PSC2_4 0x02
void lite5200b_wakeup(void)
{
unsigned char wakeup_pin;
void (*linux_wakeup)(void);
/* check PSC2_4, if it's down "QT" is signaling we have a wakeup
* from low power mode */
*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
__asm__ volatile ("sync");
wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
if (wakeup_pin & PSC2_4)
return;
/* acknowledge to "QT"
* by holding pin at 1 for 10 uS */
*(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
__asm__ volatile ("sync");
*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
__asm__ volatile ("sync");
udelay(10);
/* put ram out of self-refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
__asm__ volatile ("sync");
*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
__asm__ volatile ("sync");
*(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
__asm__ volatile ("sync");
udelay(10); /* wait a bit */
/* jump back to linux kernel code */
linux_wakeup = SAVED_ADDR;
printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
linux_wakeup);
linux_wakeup();
}
#else
#define lite5200b_wakeup()
#endif
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
@ -208,6 +255,8 @@ long int initdram (int board_type)
__asm__ volatile ("sync");
}
lite5200b_wakeup();
return dramsize + dramsize2;
}

4
board/mcc200/lcd.c
View File

@ -180,10 +180,6 @@ void lcd_enable (void)
break;
udelay (PSOC_WAIT_TIME);
}
if (!retries) {
printf ("%s Warning: PSoC doesn't respond on "
"RTS NEGATE\n", __FUNCTION__);
}
return;
}

52
board/mpc7448hpc2/Makefile Normal file
View File

@ -0,0 +1,52 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
.PHONY: distclean
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude ($obj).depend
#########################################################################

918
board/mpc7448hpc2/asm_init.S Normal file
View File

@ -0,0 +1,918 @@
/*
* (C) Copyright 2004-05; Tundra Semiconductor Corp.
*
* Added automatic detect of SDC settings
* Copyright (c) 2005 Freescale Semiconductor, Inc.
* Maintainer tie-fei.zang@freescale.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* FILENAME: asm_init.s
*
* Originator: Alex Bounine
*
* DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip
*
*/
#include <config.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/processor.h>
#include <tsi108.h>
/*
* Build Configuration Options
*/
/* #define DISABLE_PBM disables usage of PB Master */
/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
/*
* Hardcoded SDC settings
*/
#ifdef SDC_HARDCODED_INIT
/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
#define VAL_SD_REFRESH (0x61A)
#define VAL_SD_TIMING (0x0308336b)
#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
#endif /* SDC_HARDCODED_INIT */
/*
CPU Configuration:
CPU Address and Data Parity enables.
#define CPU_AP
#define CPU_DP
*/
/*
* Macros
* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
* expected to work correctly for the CSR space within 32KB range.
*
* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
* These macros are absolutely identical except their names. This difference
* is provided intentionally for better readable code.
*/
#define LOAD_PTR(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
#define LOAD_U32(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
/* LOADMEM initializes a register with the contents of a specified 32-bit
* memory location, usually a CSR value.
*/
#define LOAD_MEM(reg,addr32) \
addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
#ifndef SDC_HARDCODED_INIT
sdc_clk_sync:
/* MHz: 0,0,183,100,133,167,200,233 */
.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
#endif
/*
* board_asm_init() - early initialization function. Coded to be portable to
* dual-CPU configuration.
* Checks CPU number and performs board HW initialization if called for CPU0.
* Registers used: r3,r4,r5,r6,r19,r29
*
* NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
* and the rest of the board. Current implementation demonstrates two
* possible ways to identify CPU number:
* - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
* - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
*/
.globl board_asm_init
board_asm_init:
mflr r19 /* Save LR to be able return later. */
bl icache_enable /* Enable icache to reduce reads from flash. */
/* Initialize pointer to Tsi108 register space */
LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Check Processor Version Number */
mfspr r3, PVR
rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
cmpli 0,0,r3,0x8000 /* MPC74xx */
bne cont_brd_init
/*
* For MPC744x/5x enable extended BATs[4-7]
* Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
* to disable prefetch
*/
mfspr r5, HID0
oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
mtspr HID0, r5
isync
sync
/* Adding code to disable external interventions in MPX bus mode */
mfspr r3, 1014
oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
mtspr 1014, r3
isync
sync
/* Sri: code to enable FP unit */
mfmsr r3
ori r3, r3, 0x2000
mtmsr r3
isync
sync
/* def CONFIG_DUAL_CPU
* For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
*/
#if(1)
mfspr r3,1014 /* read MSSCR0 */
rlwinm. r3,r3,27,31,31 /* get processor ID number */
mtspr SPRN_PIR,r3 /* Save CPU ID */
sync
bne init_done
b do_tsi108_init
cont_brd_init:
/* An alternative method of checking the processor number (in addition
* to configuration using MSSCR0[ID] bit on MPC74xx).
* Good for IBM PPC750FX/GX.
*/
lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
rlwinm. r3,r3,24,31,31 /* get processor ID number */
bne init_done
#else
cont_brd_init:
#endif /* CONFIG_DUAL_CPU */
/* Initialize Tsi108 chip */
do_tsi108_init:
/*
* Adjust HLP/Flash parameters. By default after reset the HLP port is
* set to support slow devices. Better performance can be achived when
* an optimal parameters are used for specific EPROM device.
* NOTE: This should be performed ASAP for the emulation platform
* because it has 5MHz HLP clocking.
*/
#ifdef CONFIG_TSI108EMU
ori r4,r29,TSI108_HLP_REG_OFFSET
LOAD_U32(r5,0x434422c0)
stw r5,0x08(r4) /* set HLP B0_CTRL0 */
sync
LOAD_U32(r5,0xd0012000)
stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
sync
#endif
/* Initialize PB interface. */
ori r4,r29,TSI108_PB_REG_OFFSET
#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
/* Relocate (if required) Tsi108 registers. Set new value for
* PB_REG_BAR:
* Note we are in the 32-bit address mode.
*/
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
stw r5,PB_REG_BAR(r4)
andis. r29,r5,0xFFFF
sync
ori r4,r29,TSI108_PB_REG_OFFSET
#endif
/* Set PB Slave configuration register */
LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
lwz r3, PB_RSR(r4) /* get PB bus mode */
xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
stw r5,PB_SCR(r4)
sync
/* Configure PB Arbiter */
lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
#ifdef DISABLE_PBM
ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
#endif
andc r5,r5,r3 /* Clear the masked bit fields */
ori r5,r5,0x0001 /* Set pipeline depth */
stw r5,PB_ARB_CTRL(r4)
#if (0) /* currently using the default settings for PBM after reset */
LOAD_U32(r5,0x) /* value for PB_MCR */
stw r5,PB_MCR(r4)
sync
LOAD_U32(r5,0x) /* value for PB_MCMD */
stw r5,PB_MCMD(r4)
sync
#endif
/* Disable or enable PVT based on processor bus frequency
* 1. Read CG_PWRUP_STATUS register field bits 18,17,16
* 2. See if the value is < or > 133mhz (18:16 = 100)
* 3. If > enable PVT
*/
LOAD_U32(r3,0xC0002234)
lwz r3,0(r3)
rlwinm r3,r3,16,29,31
cmpi 0,0,r3,0x0004
bgt sdc_init
#ifndef CONFIG_TSI108EMU
/* FIXME: Disable PB calibration control for any real Tsi108 board */
li r5,0x0101 /* disable calibration control */
stw r5,PB_PVT_CTRL2(r4)
sync
#endif
/* Initialize SDRAM controller. */
sdc_init:
#ifndef SDC_HARDCODED_INIT
/* get SDC clock prior doing sdram controller autoconfig */
ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
rlwinm r3,r3,12,29,31 /* r3 - SD clk */
lis r5,sdc_clk_sync@h
ori r5,r5,sdc_clk_sync@l
/* Sri: At this point check if r3 = 001. If yes,
* the memory frequency should be same as the
* MPX bus frequency
*/
cmpi 0,0,r3,0x0001
bne get_nsec
lwz r6, CG_PWRUP_STATUS(r4)
rlwinm r6,r6,16,29,31
mr r3,r6
get_nsec:
rlwinm r3,r3,2,0,31
lwzx r9,r5,r3 /* get SD clk rate in nSec */
/* ATTN: r9 will be used by SPD routine */
#endif /* !SDC_HARDCODED_INIT */
ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
/* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
LOAD_U32(r5,0x00)
stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
#ifdef ENABLE_SDRAM_ECC
li r5, 0x01
#endif /* ENABLE_SDRAM_ECC */
stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
sync
#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
/* First read the CG_PWRUP_STATUS register to get the
* memory speed from bits 22,21,20
*/
LOAD_U32(r3,0xC0002234)
lwz r3,0(r3)
rlwinm r3,r3,12,29,31
/* Now first check for 166, then 200, or default */
cmpi 0,0,r3,0x0005
bne check_for_200mhz
/* set values for 166 Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x00000515)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03073368)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
b sdc_init_done
check_for_200mhz:
cmpi 0,0,r3,0x0006
bne set_default_values
/* set values for 200Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x0000061a)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03083348)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
b sdc_init_done
set_default_values:
/* Set refresh rate and timing parameters */
LOAD_U32(r5,VAL_SD_REFRESH)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,VAL_SD_TIMING)
stw r5,SD_TIMING(r4)
sync
/* Initialize DIMM0 control and BAR registers */
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D0_CTRL(r4)
LOAD_U32(r5,VAL_SD_D0_BAR)
stw r5,SD_D0_BAR(r4)
sync
/* Initialize DIMM1 control and BAR registers
* (same as dimm 0, next 512MB, disabled)
*/
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
#ifdef SDC_AUTOPRECH_EN
oris r5,r5,0x0001 /* set auto precharge EN bit */
#endif
stw r5,SD_D1_CTRL(r4)
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
#else /* !SDC_HARDCODED_INIT */
bl tsi108_sdram_spd /* automatically detect SDC settings */
#endif /* SDC_HARDCODED_INIT */
sdc_init_done:
#ifdef DISABLE_PBM
LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
#else
LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
#endif /* DISABLE_PBM */
#ifdef CONFIG_TSI108EMU
oris r5,r5,0x0010 /* set EMULATION_MODE bit */
#endif
stw r5,SD_CTRL(r4)
eieio
sync
/* Enable SDRAM access */
oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
stw r5,SD_CTRL(r4)
sync
wait_init_complete:
lwz r5,SD_STATUS(r4)
andi. r5,r5,0x0001
/* wait until SDRAM initialization is complete */
beq wait_init_complete
/* Map SDRAM into the processor bus address space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Setup BARs associated with direct path PB<->SDRAM */
/* PB_SDRAM_BAR1:
* provides a direct path to the main system memory (cacheable SDRAM)
*/
/* BA=0,Size=512MB, ENable, No Addr.Translation */
LOAD_U32(r5, 0x00000011)
stw r5,PB_SDRAM_BAR1(r4)
sync
/* Make sure that PB_SDRAM_BAR1 decoder is set
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR1(r4)
sync
/* PB_SDRAM_BAR2:
* provides non-cacheable alias (via the direct path) to main
* system memory.
* Size = 512MB, ENable, Addr.Translation - ON,
* BA = 0x0_40000000, TA = 0x0_00000000
*/
LOAD_U32(r5, 0x40010011)
stw r5,PB_SDRAM_BAR2(r4)
sync
/* Make sure that PB_SDRAM_BAR2 decoder is set
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR2(r4)
sync
init_done:
/* All done. Restore LR and return. */
mtlr r19
blr
#if (0)
/*
* init_cpu1
* This routine enables CPU1 on the dual-processor system.
* Now there is only one processor in the system
*/
.global enable_cpu1
enable_cpu1:
lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
addi r3,r3,Tsi108_Base@l
lwz r3,0(r3) /* R3 = CSR Base Addr */
ori r4,r3,TSI108_PB_REG_OFFSET
lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
ori r3,r3,0x0200 /* Set M1_EN bit */
stw r3,PB_ARB_CTRL(r4)
blr
#endif
/*
* enable_EI
* Enable CPU core external interrupt
*/
.global enable_EI
enable_EI:
mfmsr r3
ori r3,r3,0x8000 /* set EE bit */
mtmsr r3
blr
/*
* disable_EI
* Disable CPU core external interrupt
*/
.global disable_EI
disable_EI:
mfmsr r3
li r4,-32768 /* aka "li r4,0x8000" */
andc r3,r3,r4 /* clear EE bit */
mtmsr r3
blr
#ifdef ENABLE_SDRAM_ECC
/* enables SDRAM ECC */
.global enable_ECC
enable_ECC:
ori r4,r29,TSI108_SD_REG_OFFSET
lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
ori r3,r3,0x0001 /* Set ECC_EN bit */
stw r3,SD_ECC_CTRL(r4)
blr
/*
* clear_ECC_err
* Clears all pending SDRAM ECC errors
* (normally after SDRAM scrubbing/initialization)
*/
.global clear_ECC_err
clear_ECC_err:
ori r4,r29,TSI108_SD_REG_OFFSET
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
stw r3,SD_INT_STATUS(r4)
blr
#endif /* ENABLE_SDRAM_ECC */
#ifndef SDC_HARDCODED_INIT
/* SDRAM SPD Support */
#define SD_I2C_CTRL1 (0x400)
#define SD_I2C_CTRL2 (0x404)
#define SD_I2C_RD_DATA (0x408)
#define SD_I2C_WR_DATA (0x40C)
/*
* SDRAM SPD Support Macros
*/
#define SPD_DIMM0 (0x00000100)
#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
#define SPD_RDIMM (0x01)
#define SPD_UDIMM (0x02)
#define SPD_CAS_3 0x8
#define SPD_CAS_4 0x10
#define SPD_CAS_5 0x20
#define ERR_NO_DIMM_FOUND (0xdb0)
#define ERR_TRAS_FAIL (0xdb1)
#define ERR_TRCD_FAIL (0xdb2)
#define ERR_TRP_FAIL (0xdb3)
#define ERR_TWR_FAIL (0xdb4)
#define ERR_UNKNOWN_PART (0xdb5)
#define ERR_NRANK_INVALID (0xdb6)
#define ERR_DIMM_SIZE (0xdb7)
#define ERR_ADDR_MODE (0xdb8)
#define ERR_RFRSH_RATE (0xdb9)
#define ERR_DIMM_TYPE (0xdba)
#define ERR_CL_VALUE (0xdbb)
#define ERR_TRFC_FAIL (0xdbc)
/* READ_SPD requirements:
* byte - byte address in SPD device (0 - 255)
* r3 = will return data read from I2C Byte location
* r4 - unchanged (SDC base addr)
* r5 - clobbered in routine (I2C status)
* r10 - number of DDR slot where first SPD device is detected
*/
#define READ_SPD(byte_num) \
addis r3, 0, byte_num@l; \
or r3, r3, r10; \
ori r3, r3, 0x0A; \
stw r3, SD_I2C_CTRL1(r4); \
li r3, I2C_CNTRL2_START; \
stw r3, SD_I2C_CTRL2(r4); \
eieio; \
sync; \
li r3, 0x100; \
1:; \
addic. r3, r3, -1; \
bne 1b; \
2:; \
lwz r5, SD_I2C_CTRL2(r4); \
rlwinm. r3,r5,0,23,23; \
bne 2b; \
rlwinm. r3,r5,0,3,3; \
lwz r3,SD_I2C_RD_DATA(r4)
#define SPD_MIN_RFRSH (0x80)
#define SPD_MAX_RFRSH (0x85)
refresh_rates: /* in nSec */
.long 15625 /* Normal (0x80) */
.long 3900 /* Reduced 0.25x (0x81) */
.long 7800 /* Reduced 0.5x (0x82) */
.long 31300 /* Extended 2x (0x83) */
.long 62500 /* Extended 4x (0x84) */
.long 125000 /* Extended 8x (0x85) */
/*
* tsi108_sdram_spd
*
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
* Uses registers: r4 - SDC base address (not changed)
* r9 - SDC clocking period in nSec
* Changes registers: r3,r5,r6,r7,r8,r10,r11
*/
tsi108_sdram_spd:
li r10,SPD_DIMM0
xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
do_first_dimm:
/* Program Refresh Rate Register */
READ_SPD(12) /* get Refresh Rate */
beq check_next_slot
li r5, ERR_RFRSH_RATE
cmpi 0,0,r3,SPD_MIN_RFRSH
ble spd_fail
cmpi 0,0,r3,SPD_MAX_RFRSH
bgt spd_fail
addi r3,r3,-SPD_MIN_RFRSH
rlwinm r3,r3,2,0,31
lis r5,refresh_rates@h
ori r5,r5,refresh_rates@l
lwzx r5,r5,r3 /* get refresh rate in nSec */
divwu r5,r5,r9 /* calculate # of SDC clocks */
stw r5,SD_REFRESH(r4) /* Set refresh rate */
sync
/* Program SD Timing Register */
li r7, 0 /* clear r7 prior parameter collection */
READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
beq spd_read_fail
li r5, ERR_DIMM_TYPE
cmpi 0,0,r3,SPD_UDIMM
beq do_cl
cmpi 0,0,r3,SPD_RDIMM
bne spd_fail
oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
do_cl:
READ_SPD(18) /* Get CAS Latency */
beq spd_read_fail
li r5,ERR_CL_VALUE
andi. r6,r3,SPD_CAS_3
beq cl_4
li r6,3
b set_cl
cl_4:
andi. r6,r3,SPD_CAS_4
beq cl_5
li r6,4
b set_cl
cl_5:
andi. r6,r3,SPD_CAS_5
beq spd_fail
li r6,5
set_cl:
rlwimi r7,r6,24,5,7
READ_SPD(30) /* Get tRAS */
beq spd_read_fail
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_tras
addi r6,r6,1
set_tras:
li r5,ERR_TRAS_FAIL
cmpi 0,0,r6,0x0F /* max supported value */
bgt spd_fail
rlwimi r7,r6,16,12,15
READ_SPD(29) /* Get tRCD */
beq spd_read_fail
/* right shift tRCD by 2 bits as per DDR2 spec */
rlwinm r3,r3,30,2,31
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trcd
addi r6,r6,1
set_trcd:
li r5,ERR_TRCD_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,12,17,19
READ_SPD(27) /* Get tRP value */
beq spd_read_fail
rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trp
addi r6,r6,1
set_trp:
li r5,ERR_TRP_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,8,21,23
READ_SPD(36) /* Get tWR value */
beq spd_read_fail
rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_twr
addi r6,r6,1
set_twr:
addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
li r5,ERR_TWR_FAIL
cmpi 0,0,r6,0x07 /* max supported value */
bgt spd_fail
rlwimi r7,r6,5,24,26
READ_SPD(42) /* Get tRFC */
beq spd_read_fail
li r5, ERR_TRFC_FAIL
/* Tsi108 spec: tRFC=(tRFC + 1)/2 */
addi r3,r3,1
rlwinm. r3,r3,31,1,31 /* divide by 2 */
beq spd_fail
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
beq set_trfc
addi r6,r6,1
set_trfc:
cmpi 0,0,r6,0x1F /* max supported value */
bgt spd_fail
rlwimi r7,r6,0,27,31
stw r7,SD_TIMING(r4)
sync
/*
* The following two registers are set on per-DIMM basis.
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS
*/
do_each_dimm:
/* Program SDRAM DIMM Control Register */
li r7, 0 /* clear r7 prior parameter collection */
READ_SPD(13) /* Get Primary SDRAM Width */
beq spd_read_fail
cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
beq do_nbank
oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
do_nbank:
READ_SPD(17) /* Get Number of banks on SDRAM device */
beq spd_read_fail
/* Grendel only distinguish betw. 4 or 8-bank memory parts */
li r5,ERR_UNKNOWN_PART /* non-supported memory part */
cmpi 0,0,r3,4
beq do_nrank
cmpi 0,0,r3,8
bne spd_fail
ori r7,r7,0x1000
do_nrank:
READ_SPD(5) /* Get # of Ranks */
beq spd_read_fail
li r5,ERR_NRANK_INVALID
andi. r6,r3,0x7 /* Use bits [2..0] only */
beq do_addr_mode
cmpi 0,0,r6,1
bgt spd_fail
rlwimi r7,r6,8,23,23
do_addr_mode:
READ_SPD(4) /* Get # of Column Addresses */
beq spd_read_fail
li r5, ERR_ADDR_MODE
andi. r3,r3,0x0f /* cut off reserved bits */
cmpi 0,0,r3,8
ble spd_fail
cmpi 0,0,r3,15
bgt spd_fail
addi r6,r3,-8 /* calculate ADDR_MODE parameter */
rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
set_dimm_ctrl:
#ifdef SDC_AUTOPRECH_EN
oris r7,r7,0x0001 /* set auto precharge EN bit */
#endif
ori r7,r7,1 /* set ENABLE bit */
cmpi 0,0,r10,SPD_DIMM0
bne 1f
stw r7,SD_D0_CTRL(r4)
sync
b set_dimm_bar
1:
stw r7,SD_D1_CTRL(r4)
sync
/* Program SDRAM DIMMx Base Address Register */
set_dimm_bar:
READ_SPD(5) /* get # of Ranks */
beq spd_read_fail
andi. r7,r3,0x7
addi r7,r7,1
READ_SPD(31) /* Read DIMM rank density */
beq spd_read_fail
rlwinm r5,r3,27,29,31
rlwinm r6,r3,3,24,28
or r5,r6,r5 /* r5 = Normalized Rank Density byte */
lis r8, 0x0080 /* 128MB >> 4 */
mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
neg r7,r8
rlwinm r7,r7,28,4,31
or r7,r7,r11 /* set ADDR field */
rlwinm r8,r8,12,20,31
add r11,r11,r8 /* set Base Addr for next DIMM */
cmpi 0,0,r10,SPD_DIMM0
bne set_dimm1_size
stw r7,SD_D0_BAR(r4)
sync
li r10,SPD_DIMM1
READ_SPD(0)
bne do_each_dimm
b spd_done
set_dimm1_size:
stw r7,SD_D1_BAR(r4)
sync
spd_done:
blr
check_next_slot:
cmpi 0,0,r10,SPD_DIMM1
beq spd_read_fail
li r10,SPD_DIMM1
b do_first_dimm
spd_read_fail:
ori r3,r0,0xdead
b err_hung
spd_fail:
li r3,0x0bad
sync
err_hung: /* hang here for debugging */
nop
nop
b err_hung
#endif /* !SDC_HARDCODED_INIT */

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#
# Copyright (c) 2005 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Flash address
TEXT_BASE = 0xFF000000
# RAM address
#TEXT_BASE = 0x00400000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float

107
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/*
* (C) Copyright 2005 Freescale Semiconductor, Inc.
*
* Roy Zang <tie-fei.zang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* modifications for the Tsi108 Emul Board by avb@Tundra
*/
/*
* board support/init functions for the
* Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
*/
#include <common.h>
#include <74xx_7xx.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup (void *blob, bd_t *bd);
#endif
#undef DEBUG
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
int display_mem_map (void);
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r ((gd_t *) gd, dest_addr);
/* NOTREACHED */
}
/*
* Check Board Identity:
* report board type
*/
int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
/*
* Read Processor ID:
*
* report calling processor number
*/
int read_pid (void)
{
return 0; /* we are on single CPU platform for a while */
}
long int dram_size (int board_type)
{
return 0x20000000; /* 256M bytes */
}
long int initdram (int board_type)
{
return dram_size (board_type);
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup (blob, bd);
p = ft_get_prop (blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32 (bd->bi_memstart);
*p = cpu_to_be32 (bd->bi_memsize);
}
}
#endif

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/*****************************************************************************
* (C) Copyright 2003; Tundra Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*****************************************************************************/
/*----------------------------------------------------------------------------
* FILENAME: tsi108_init.c
*
* Originator: Alex Bounine
*
* DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip
*---------------------------------------------------------------------------*/
#include <common.h>
#include <74xx_7xx.h>
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <tsi108.h>
extern void mpicInit (int verbose);
/*
* Configuration Options
*/
typedef struct {
ulong upper;
ulong lower;
} PB2OCN_LUT_ENTRY;
PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
/* 0 - 7 */
{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
/* 8 - 15 */
{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
/* 16 - 23 */
{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
/* 24 - 31 */
{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
{0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
};
#ifdef CFG_CLK_SPREAD
typedef struct {
ulong ctrl0;
ulong ctrl1;
} PLL_CTRL_SET;
/*
* Clock Generator SPLL0 initialization values
* PLL0 configuration table for various PB_CLKO freq.
* Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
* Fout depends on required PB_CLKO. Based on Fref = 33 MHz
*/
static PLL_CTRL_SET pll0_config[8] = {
{0x00000000, 0x00000000}, /* 0: bypass */
{0x00000000, 0x00000000}, /* 1: reserved */
{0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
{0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
{0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
{0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
{0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
{0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
};
#endif /* CFG_CLK_SPREAD */
/*
* Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
* (based on recommended Tsi108 reference clock 33MHz)
*/
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
/*
* get_board_bus_clk ()
*
* returns the bus clock in Hz.
*/
unsigned long get_board_bus_clk (void)
{
ulong i;
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
return pb_clk_sel[i] * 1000000;
}
/*
* board_early_init_f ()
*
* board-specific initialization executed from flash
*/
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
switch (i) {
case 0: /* external clock */
printf ("Using external clock\n");
break;
case 1: /* system clock */
gd->mem_clk = gd->bus_clk;
break;
case 4: /* 133 MHz */
case 5: /* 166 MHz */
case 6: /* 200 MHz */
gd->mem_clk = pb_clk_sel[i] * 1000000;
break;
default:
printf ("Invalid DDR2 clock setting\n");
return -1;
}
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
return 0;
}
/*
* board_early_init_r() - Tsi108 initialization function executed right after
* relocation. Contains code that cannot be executed from flash.
*/
int board_early_init_r (void)
{
ulong temp, i;
ulong reg_val;
volatile ulong *reg_ptr;
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
for (i = 0; i < 32; i++) {
*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
*reg_ptr++ = 0x00;
}
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
* read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
__asm__ __volatile__ ("sync");
/*
* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
* processor bus address space. Immediately after reset LUT and address
* translation are disabled for this BAR. Now we have to initialize LUT
* and switch from the BOOT mode to the normal operation mode.
*
* The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
* and covers 512MB of address space. To allow larger aperture we also
* have to relocate register window of Tsi108
*
* Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
* mode.
*
* initialize pointer to LUT associated with PB_OCN_BAR1
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
for (i = 0; i < 32; i++) {
*reg_ptr++ = pb2ocn_lut1[i].lower;
*reg_ptr++ = pb2ocn_lut1[i].upper;
}
__asm__ __volatile__ ("sync");
/* Base addresses for CS0, CS1, CS2, CS3 */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__ ("sync");
/* Masks for HLP banks */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
/* Set CTRL0 values for banks */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
/* Set banks to latched mode, enabled, and other default settings */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
/*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__ ("sync");
/*
* SRI: At this point we have enabled the HLP banks. That means we can
* now read from the NVRAM and initialize the environment variables.
* We will over-ride the env_init called in board_init_f
* This is really a work-around because, the HLP bank 1
* where NVRAM resides is not visible during board_init_f
* (lib_ppc/board.c)
* Alternatively, we could use the I2C EEPROM at start-up to configure
* and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2.
*/
env_init ();
#ifndef DISABLE_PBM
/*
* For IBM processors we have to set Address-Only commands generated
* by PBM that are different from ones set after reset.
*/
temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp))
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
#endif /* DISABLE_PBM */
#ifdef CONFIG_PCI
/*
* Initialize PCI/X block
*/
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__ ("sync");
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
temp = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__ ("sync");
/* This register is on the PCI side to interpret the address it receives
* and maps it as a IO address.
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0xFA000001);
__asm__ __volatile__ ("sync");
/*
* Map PCI/X Memory Space
*
* Transactions directed from OCM to PCI Memory Space are directed
* from PB to PCI
* unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
* If address remapping is required the corresponding PCI_PFAB_MEM32
* and PCI_PFAB_PFMx register groups have to be configured.
*
* Map the path from the PCI/X bus into the system memory
*
* The memory mapped window assotiated with PCI P2O_BAR2 provides
* access to the system memory without address remapping.
* All system memory is opened for accesses initiated by PCI/X bus
* masters.
*
* Initialize LUT associated with PCI P2O_BAR2
*
* set pointer to LUT associated with PCI P2O_BAR2
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
#ifdef DISABLE_PBM
/* In case when PBM is disabled (no HW supported cache snoopng on PB)
* P2O_BAR2 is directly mapped into the system memory without address
* translation.
*/
reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
*reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
}
/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
reg_val = 0x00007500;
#else
reg_val = 0x00000002; /* Destination port = PBM */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
*reg_ptr++ = 0x40000000;
/* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000;
}
/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
reg_val = 0x00007100;
#endif
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit PCI bus address for system memory
* ( 0 is the best choice for easy mapping)
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__ ("sync");
#ifndef DISABLE_PBM
/*
* The memory mapped window assotiated with PCI P2O_BAR3 provides
* access to the system memory using SDRAM OCN port and address
* translation. This is alternative way to access SDRAM from PCI
* required for Tsi108 emulation testing.
* All system memory is opened for accesses initiated by
* PCI/X bus masters.
*
* Initialize LUT associated with PCI P2O_BAR3
*
* set pointer to LUT associated with PCI P2O_BAR3
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
reg_val = 0x00000004; /* Destination port = SDC */
for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
*reg_ptr++ = 0;
/* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000;
}
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
reg_val =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_P2O_PAGE_SIZES);
reg_val &= ~0x00FF;
reg_val |= 0x0071;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit base PCI bus address for window (0x20000000) */
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__ ("sync");
#endif /* !DISABLE_PBM */
#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
reg_val = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__ ("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
CFG_TSI108_CSR_BASE);
__asm__ __volatile__ ("sync");
#endif
/*
* Finally enable PCI/X Bus Master and Memory Space access
*/
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__ ("sync");
#endif /* CONFIG_PCI */
/*
* Initialize MPIC outputs (interrupt pins):
* Interrupt routing on the Grendel Emul. Board:
* PB_INT[0] -> INT (CPU0)
* PB_INT[1] -> INT (CPU1)
* PB_INT[2] -> MCP (CPU0)
* PB_INT[3] -> MCP (CPU1)
* Set interrupt controller outputs as Level_Sensitive/Active_Low
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__ ("sync");
/*
* Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads)
*/
reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME);
return 0;
}
/*
* Needed to print out L2 cache info
* used in the misc_init_r function
*/
unsigned long get_l2cr (void)
{
unsigned long l2controlreg;
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
return l2controlreg;
}
/*
* misc_init_r()
*
* various things to do after relocation
*
*/
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
/* Ensure that Spread-Spectrum is disabled */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x002e0044); /* D = 0.25% */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
/* Wait and set SSEN for both PLL0 and 1 */
udelay (1000);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
#endif /* CFG_CLK_SPREAD */
#ifdef CFG_L2
l2cache_enable ();
#endif
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
* at this point i.e. above call to l2cache_enable is the very last
* thing done with regards to enabling diabling the cache.
* So this seems like a good place to print all this information
*/
printf ("CACHE: ");
switch (get_cpu_type()) {
case CPU_7447A:
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 512KB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("\n");
break;
case CPU_7448:
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 1MB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
break;
default:
break;
}
return 0;
}

136
board/mpc7448hpc2/u-boot.lds Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

41
board/mpc8360emds/mpc8360emds.c
View File

@ -31,6 +31,10 @@
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GETH1 */
@ -658,22 +662,45 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
" - disables injects\n" " - re-inits memory");
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
&& defined(CONFIG_OF_BOARD_SETUP)
/*
* Prototypes of functions that we use.
*/
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
void
ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_OF_LIBFDT)
int nodeoffset;
int tmp[2];
nodeoffset = fdt_path_offset (fdt, "/memory");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(bd->bi_memstart);
tmp[1] = cpu_to_be32(bd->bi_memsize);
fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
}
#else
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
}
#endif
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
}
#endif /* CONFIG_OF_x */

20
board/mpc8360emds/pci.c
View File

@ -21,6 +21,10 @@
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#endif
#include <asm/fsl_i2c.h>
@ -299,6 +303,22 @@ void pci_init_board(void)
}
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
void
ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int err;
int tmp[2];
nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500");
if (nodeoffset >= 0) {
tmp[0] = cpu_to_be32(hose[0].first_busno);
tmp[1] = cpu_to_be32(hose[0].last_busno);
err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp));
}
}
#endif /* CONFIG_OF_LIBFDT */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)

4
board/mpc8641hpcn/Makefile
View File

@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o pixis.o sys_eeprom.o
COBJS := $(BOARD).o sys_eeprom.o \
../freescale/common/pixis.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

113
board/mpc8641hpcn/mpc8641hpcn.c
View File

@ -1,9 +1,5 @@
/*
* Copyright 2004 Freescale Semiconductor.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
* Copyright 2006, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -25,18 +21,18 @@
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <spd.h>
#include <asm/io.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif
#include "pixis.h"
#include "../freescale/common/pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
#endif
void
mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
ulong val;
ulong corepll;
/*
* No args is a simple reset request.
*/
if (argc <= 1) {
out8(PIXIS_BASE + PIXIS_RST, 0);
/* not reached */
}
cmd = argv[1][1];
switch (cmd) {
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
while (1) ; /* Not reached */
case 'l':
if (argv[2][1] == 'f') {
read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint(argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else
goto my_usage;
while (1) ; /* Not reached */
} else if (argv[2][1] == 'd') {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
/*
* Reset from next bank without changing
* frequency and without watchdog timer enabled.
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2)
goto my_usage;
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank....\n");
set_px_go();
}
default:
goto my_usage;
}
my_usage:
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
puts(" reset altbank [wd]\n");
puts("For example: reset cf 40 2.5 10\n");
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
}
/*
* get_board_sys_clk
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ

3
board/nc650/config.mk
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -27,4 +27,3 @@
#
TEXT_BASE = 0x40700000
BOARDLIBS = $(obj)drivers/nand/libnand.a

6
board/nc650/nc650.c
View File

@ -177,16 +177,14 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);

2
board/uc101/uc101.c
View File

@ -221,6 +221,8 @@ long int initdram (int board_type)
int checkboard (void)
{
puts ("Board: MAN UC101\n");
/* clear the Display */
*(char *)(CFG_DISP_CWORD) = 0x80;
return 0;
}

65
board/xilinx/ml401/Makefile Normal file
View File

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/ml401/config.mk Normal file
View File

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
#
TEXT_BASE = 0x12000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

49
board/xilinx/ml401/ml401.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

67
board/xilinx/ml401/u-boot.lds Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

67
board/xilinx/ml401/xparameters.h Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 66666667
/* Interrupt controller is intc_0 */
#define XILINX_INTC_BASEADDR 0xd1000fc0
#define XILINX_INTC_NUM_INTR_INPUTS 12
/* Timer pheriphery is opb_timer_0 */
#define XILINX_TIMER_BASEADDR 0xa2000000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is console_uart */
#define XILINX_UART_BASEADDR 0xa0000000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is opb_gpio_0*/
#define XILINX_GPIO_BASEADDR 0x90000000
/* Flash Memory is opb_emc_0 */
#define XILINX_FLASH_START 0x28000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is plb_ddr_0 */
#define XILINX_RAM_START 0x10000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is opb_sysace_0 */
#define XILINX_SYSACE_BASEADDR 0xCF000000
#define XILINX_SYSACE_HIGHADDR 0xCF0001FF
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is opb_ethernet_0 */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

4
board/xilinx/xilinx_enet/emac_adapter.c
View File

@ -147,7 +147,11 @@ eth_rx(void)
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
#ifndef CONFIG_EMACLITE
NetReceive((uchar *)etherrxbuff, RecvFrameLength);
#else
NetReceive(etherrxbuff, RecvFrameLength);
#endif
return (1);
} else {
return (0);

65
board/xilinx/xupv2p/Makefile Normal file
View File

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/xupv2p/config.mk Normal file
View File

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
#
TEXT_BASE = 0x38000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

67
board/xilinx/xupv2p/u-boot.lds Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

64
board/xilinx/xupv2p/xparameters.h Normal file
View File

@ -0,0 +1,64 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 11
/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 1
/* Uart pheriphery is RS232_Uart_1 */
#define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
/* FLASH doesn't exist none */
/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
#define XILINX_RAM_START 0x30000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

49
board/xilinx/xupv2p/xupv2p.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

4
common/Makefile
View File

@ -32,7 +32,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_cache.o cmd_console.o \
cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
cmd_eeprom.o cmd_elf.o cmd_ext2.o \
cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
@ -45,7 +45,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
env_nvram.o env_nowhere.o \
exports.o \
flash.o fpga.o ft_build.o \
fdt_support.o flash.o fpga.o ft_build.o \
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \

26
common/cmd_bdinfo.c
View File

@ -180,6 +180,32 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#elif defined(CONFIG_MICROBLAZE) /* ! PPC, which leaves Microblaze */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
bd_t *bd = gd->bd;
print_num ("mem start ", (ulong)bd->bi_memstart);
print_num ("mem size ", (ulong)bd->bi_memsize);
print_num ("flash start ", (ulong)bd->bi_flashstart);
print_num ("flash size ", (ulong)bd->bi_flashsize);
print_num ("flash offset ", (ulong)bd->bi_flashoffset);
#if defined(CFG_SRAM_BASE)
print_num ("sram start ", (ulong)bd->bi_sramstart);
print_num ("sram size ", (ulong)bd->bi_sramsize);
#endif
#if defined(CFG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
printf ("\nbaudrate = %d bps\n", (ulong)bd->bi_baudrate);
return 0;
}
#else /* ! PPC, which leaves MIPS */

105
common/cmd_bootm.c
View File

@ -34,7 +34,12 @@
#include <environment.h>
#include <asm/byteorder.h>
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
@ -467,7 +472,7 @@ U_BOOT_CMD(
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
"\tWhen booting a Linux kernel which requires a flat device-tree\n"
"\ta third argument is required which is the address of the of the\n"
"\tdevice-tree blob. To boot that kernel without an initrd image,\n"
@ -529,7 +534,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
bd_t *kbd;
void (*kernel)(bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
char *of_flat_tree = NULL;
ulong of_data = 0;
#endif
@ -622,7 +627,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* Check if there is an initrd image
*/
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
/* Look for a '-' which indicates to ignore the ramdisk argument */
if (argc >= 3 && strcmp(argv[2], "-") == 0) {
debug ("Skipping initrd\n");
@ -739,12 +744,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
len = data = 0;
}
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
if(argc > 3) {
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
hdr = (image_header_t *)of_flat_tree;
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header(of_flat_tree) == 0) {
#else
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
#endif
#ifndef CFG_NO_FLASH
if (addr2info((ulong)of_flat_tree) != NULL)
of_data = (ulong)of_flat_tree;
@ -787,7 +795,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
printf("ERROR: uImage is not uncompressed\n");
return;
}
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) {
#else
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
#endif
printf ("ERROR: uImage data is not a flat device tree\n");
return;
}
@ -824,12 +836,20 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
of_data += 4 - tail;
}
#if defined(CONFIG_OF_LIBFDT)
if (fdt_check_header((void *)of_data) != 0) {
#else
if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
#endif
printf ("ERROR: image is not a flat device tree\n");
return;
}
#if defined(CONFIG_OF_LIBFDT)
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
#else
if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
#endif
printf ("ERROR: flat device tree size does not agree with image\n");
return;
}
@ -913,7 +933,52 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
unlock_ram_in_cache();
#endif
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_LIBFDT)
/* move of_flat_tree if needed */
if (of_data) {
int err;
ulong of_start, of_len;
of_len = be32_to_cpu(fdt_totalsize(of_data));
/* position on a 4K boundary before the initrd/kbd */
if (initrd_start)
of_start = initrd_start - of_len;
else
of_start = (ulong)kbd - of_len;
of_start &= ~(4096 - 1); /* align on page */
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
of_data, of_data + of_len - 1, of_len, of_len);
of_flat_tree = (char *)of_start;
printf (" Loading Device Tree to %08lx, end %08lx ... ",
of_start, of_start + of_len - 1);
err = fdt_open_into((void *)of_start, (void *)of_data, of_len);
if (err != 0) {
printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__);
}
/*
* Add the chosen node if it doesn't exist, add the env and bd_t
* if the user wants it (the logic is in the subroutines).
*/
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
return;
}
#ifdef CONFIG_OF_HAS_UBOOT_ENV
if (fdt_env(of_flat_tree) < 0) {
printf("Failed creating the /u-boot-env node, aborting.\n");
return;
}
#endif
#ifdef CONFIG_OF_HAS_BD_T
if (fdt_bd_t(of_flat_tree) < 0) {
printf("Failed creating the /bd_t node, aborting.\n");
return;
}
#endif
}
#endif
#if defined(CONFIG_OF_FLAT_TREE)
/* move of_flat_tree if needed */
if (of_data) {
ulong of_start, of_len;
@ -942,13 +1007,13 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* r6: Start of command line string
* r7: End of command line string
*/
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
if (!of_flat_tree) /* no device tree; boot old style */
#endif
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
/* does not return */
#ifdef CONFIG_OF_FLAT_TREE
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
/*
* Linux Kernel Parameters (passing device tree):
* r3: ptr to OF flat tree, followed by the board info data
@ -957,8 +1022,28 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
* r6: NULL
* r7: NULL
*/
#if defined(CONFIG_OF_FLAT_TREE)
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
/* ft_dump_blob(of_flat_tree); */
#endif
#if defined(CONFIG_OF_LIBFDT)
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
return;
}
#ifdef CONFIG_OF_HAS_UBOOT_ENV
if (fdt_env(of_flat_tree) < 0) {
printf("Failed creating the /u-boot-env node, aborting.\n");
return;
}
#endif
#ifdef CONFIG_OF_HAS_BD_T
if (fdt_bd_t(of_flat_tree) < 0) {
printf("Failed creating the /bd_t node, aborting.\n");
return;
}
#endif
#endif /* if defined(CONFIG_OF_LIBFDT) */
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
#endif

635
common/cmd_fdt.c Normal file
View File

@ -0,0 +1,635 @@
/*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
* Based on code written by:
* Pantelis Antoniou <pantelis.antoniou@gmail.com> and
* Matthew McClintock <msm@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <linux/ctype.h>
#include <linux/types.h>
#ifdef CONFIG_OF_LIBFDT
#include <asm/global_data.h>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
/*
* Global data (for the gd->bd)
*/
DECLARE_GLOBAL_DATA_PTR;
/*
* Scratchpad memory.
*/
static char data[SCRATCHPAD];
/*
* Function prototypes/declarations.
*/
static int fdt_valid(void);
static void print_data(const void *data, int len);
/*
* Flattened Device Tree command, see the help for parameter definitions.
*/
int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/*
* Figure out which subcommand was given
*/
op = argv[1][0];
/********************************************************************
* Set the address of the fdt
********************************************************************/
if (op == 'a') {
/*
* Set the address [and length] of the fdt.
*/
fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16);
if (!fdt_valid()) {
return 1;
}
if (argc >= 4) {
int len;
int err;
/*
* Optional new length
*/
len = simple_strtoul(argv[3], NULL, 16);
if (len < fdt_totalsize(fdt)) {
printf ("New length %d < existing length %d, ignoring.\n",
len, fdt_totalsize(fdt));
} else {
/*
* Open in place with a new length.
*/
err = fdt_open_into(fdt, fdt, len);
if (err != 0) {
printf ("libfdt: %s\n", fdt_strerror(err));
}
}
}
/********************************************************************
* Move the fdt
********************************************************************/
} else if (op == 'm') {
struct fdt_header *newaddr;
int len;
int err;
if (argc != 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/*
* Set the address and length of the fdt.
*/
fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16);
if (!fdt_valid()) {
return 1;
}
newaddr = (struct fdt_header *)simple_strtoul(argv[3], NULL, 16);
len = simple_strtoul(argv[4], NULL, 16);
if (len < fdt_totalsize(fdt)) {
printf ("New length %d < existing length %d, aborting.\n",
len, fdt_totalsize(fdt));
return 1;
}
/*
* Copy to the new location.
*/
err = fdt_open_into(fdt, newaddr, len);
if (err != 0) {
printf ("libfdt: %s\n", fdt_strerror(err));
return 1;
}
fdt = newaddr;
/********************************************************************
* Set the value of a node in the fdt.
********************************************************************/
} else if (op == 's') {
char *pathp; /* path */
char *prop; /* property */
struct fdt_property *nodep; /* node struct pointer */
char *newval; /* value from the user (as a string) */
char *vp; /* temporary value pointer */
char *cp; /* temporary char pointer */
int nodeoffset; /* node offset from libfdt */
int len; /* new length of the property */
int oldlen; /* original length of the property */
unsigned long tmp; /* holds converted values */
int ret; /* return value */
/*
* Parameters: Node path, property, value.
*/
if (argc < 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
pathp = argv[2];
prop = argv[3];
newval = argv[4];
if (strcmp(pathp, "/") == 0) {
nodeoffset = 0;
} else {
nodeoffset = fdt_path_offset (fdt, pathp);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt: %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
nodep = fdt_getprop (fdt, nodeoffset, prop, &oldlen);
if (oldlen < 0) {
printf ("libfdt %s\n", fdt_strerror(oldlen));
return 1;
} else if (oldlen == 0) {
/*
* The specified property has no value
*/
printf("%s has no value, cannot set one (yet).\n", prop);
return 1;
} else {
/*
* Convert the new property
*/
vp = data;
if (*newval == '<') {
/*
* Bigger values than bytes.
*/
len = 0;
newval++;
while ((*newval != '>') && (*newval != '\0')) {
cp = newval;
tmp = simple_strtoul(cp, &newval, 16);
if ((newval - cp) <= 2) {
*vp = tmp & 0xFF;
vp += 1;
len += 1;
} else if ((newval - cp) <= 4) {
*(uint16_t *)vp = __cpu_to_be16(tmp);
vp += 2;
len += 2;
} else if ((newval - cp) <= 8) {
*(uint32_t *)vp = __cpu_to_be32(tmp);
vp += 4;
len += 4;
} else {
printf("Sorry, I could not convert \"%s\"\n", cp);
return 1;
}
while (*newval == ' ')
newval++;
}
if (*newval != '>') {
printf("Unexpected character '%c'\n", *newval);
return 1;
}
} else if (*newval == '[') {
/*
* Byte stream. Convert the values.
*/
len = 0;
newval++;
while ((*newval != ']') && (*newval != '\0')) {
tmp = simple_strtoul(newval, &newval, 16);
*vp++ = tmp & 0xFF;
len++;
while (*newval == ' ')
newval++;
}
if (*newval != ']') {
printf("Unexpected character '%c'\n", *newval);
return 1;
}
} else {
/*
* Assume it is a string. Copy it into our data area for
* convenience (including the terminating '\0').
*/
len = strlen(newval) + 1;
strcpy(data, newval);
}
ret = fdt_setprop(fdt, nodeoffset, prop, data, len);
if (ret < 0) {
printf ("libfdt %s\n", fdt_strerror(ret));
return 1;
}
}
/********************************************************************
* Print (recursive) / List (single level)
********************************************************************/
} else if ((op == 'p') || (op == 'l')) {
/*
* Recursively print (a portion of) the fdt.
*/
static int offstack[MAX_LEVEL];
static char tabs[MAX_LEVEL+1] = "\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t";
int depth = MAX_LEVEL; /* how deep to print */
char *pathp; /* path */
char *prop; /* property */
void *nodep; /* property node pointer */
int nodeoffset; /* node offset from libfdt */
int nextoffset; /* next node offset from libfdt */
uint32_t tag; /* tag */
int len; /* length of the property */
int level = 0; /* keep track of nesting level */
/*
* list is an alias for print, but limited to 1 level
*/
if (op == 'l') {
depth = 1;
}
/*
* Get the starting path. The root node is an oddball,
* the offset is zero and has no name.
*/
pathp = argv[2];
if (argc > 3)
prop = argv[3];
else
prop = NULL;
if (strcmp(pathp, "/") == 0) {
nodeoffset = 0;
printf("/");
} else {
nodeoffset = fdt_path_offset (fdt, pathp);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
/*
* The user passed in a property as well as node path. Print only
* the given property and then return.
*/
if (prop) {
nodep = fdt_getprop (fdt, nodeoffset, prop, &len);
if (len == 0) {
printf("%s %s\n", pathp, prop); /* no property value */
return 0;
} else if (len > 0) {
printf("%s=", prop);
print_data (nodep, len);
printf("\n");
return 0;
} else {
printf ("libfdt %s\n", fdt_strerror(len));
return 1;
}
}
/*
* The user passed in a node path and no property, print the node
* and all subnodes.
*/
offstack[0] = nodeoffset;
while(level >= 0) {
tag = fdt_next_tag(fdt, nodeoffset, &nextoffset, &pathp);
switch(tag) {
case FDT_BEGIN_NODE:
if(level <= depth)
printf("%s%s {\n", &tabs[MAX_LEVEL - level], pathp);
level++;
offstack[level] = nodeoffset;
if (level >= MAX_LEVEL) {
printf("Aaaiii <splat> nested too deep.\n");
return 1;
}
break;
case FDT_END_NODE:
level--;
if(level <= depth)
printf("%s};\n", &tabs[MAX_LEVEL - level]);
if (level == 0) {
level = -1; /* exit the loop */
}
break;
case FDT_PROP:
nodep = fdt_getprop (fdt, offstack[level], pathp, &len);
if (len < 0) {
printf ("libfdt %s\n", fdt_strerror(len));
return 1;
} else if (len == 0) {
/* the property has no value */
if(level <= depth)
printf("%s%s;\n", &tabs[MAX_LEVEL - level], pathp);
} else {
if(level <= depth) {
printf("%s%s=", &tabs[MAX_LEVEL - level], pathp);
print_data (nodep, len);
printf(";\n");
}
}
break;
case FDT_NOP:
break;
case FDT_END:
return 1;
default:
if(level <= depth)
printf("Unknown tag 0x%08X\n", tag);
return 1;
}
nodeoffset = nextoffset;
}
/********************************************************************
* Remove a property/node
********************************************************************/
} else if (op == 'r') {
int nodeoffset; /* node offset from libfdt */
int err;
/*
* Get the path. The root node is an oddball, the offset
* is zero and has no name.
*/
if (strcmp(argv[2], "/") == 0) {
nodeoffset = 0;
} else {
nodeoffset = fdt_path_offset (fdt, argv[2]);
if (nodeoffset < 0) {
/*
* Not found or something else bad happened.
*/
printf ("libfdt %s\n", fdt_strerror(nodeoffset));
return 1;
}
}
/*
* Do the delete. A fourth parameter means delete a property,
* otherwise delete the node.
*/
if (argc > 3) {
err = fdt_delprop(fdt, nodeoffset, argv[3]);
if (err < 0) {
printf("fdt_delprop libfdt: %s\n", fdt_strerror(err));
return err;
}
} else {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("fdt_del_node libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/********************************************************************
* Create a chosen node
********************************************************************/
} else if (op == 'c') {
fdt_chosen(fdt, 0, 0, 1);
/********************************************************************
* Create a u-boot-env node
********************************************************************/
} else if (op == 'e') {
fdt_env(fdt);
/********************************************************************
* Create a bd_t node
********************************************************************/
} else if (op == 'b') {
fdt_bd_t(fdt);
/********************************************************************
* Unrecognized command
********************************************************************/
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
return 0;
}
/********************************************************************/
static int fdt_valid(void)
{
int err;
if (fdt == NULL) {
printf ("The address of the fdt is invalid (NULL).\n");
return 0;
}
err = fdt_check_header(fdt);
if (err == 0)
return 1; /* valid */
if (err < 0) {
printf("libfdt: %s", fdt_strerror(err));
/*
* Be more informative on bad version.
*/
if (err == -FDT_ERR_BADVERSION) {
if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) {
printf (" - too old, fdt $d < %d",
fdt_version(fdt), FDT_FIRST_SUPPORTED_VERSION);
fdt = NULL;
}
if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) {
printf (" - too new, fdt $d > %d",
fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION);
fdt = NULL;
}
return 0;
}
printf("\n");
return 0;
}
return 1;
}
/********************************************************************/
/*
* OF flat tree handling
* Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
* Updated by: Matthew McClintock <msm@freescale.com>
* Converted to libfdt by: Gerald Van Baren <vanbaren@cideas.com>
*/
static int is_printable_string(const void *data, int len)
{
const char *s = data;
/* zero length is not */
if (len == 0)
return 0;
/* must terminate with zero */
if (s[len - 1] != '\0')
return 0;
/* printable or a null byte (concatenated strings) */
while (((*s == '\0') || isprint(*s)) && (len > 0)) {
/*
* If we see a null, there are three possibilities:
* 1) If len == 1, it is the end of the string, printable
* 2) Next character also a null, not printable.
* 3) Next character not a null, continue to check.
*/
if (s[0] == '\0') {
if (len == 1)
return 1;
if (s[1] == '\0')
return 0;
}
s++;
len--;
}
/* Not the null termination, or not done yet: not printable */
if (*s != '\0' || (len != 0))
return 0;
return 1;
}
static void print_data(const void *data, int len)
{
int j;
const u8 *s;
/* no data, don't print */
if (len == 0)
return;
/*
* It is a string, but it may have multiple strings (embedded '\0's).
*/
if (is_printable_string(data, len)) {
puts("\"");
j = 0;
while (j < len) {
if (j > 0)
puts("\", \"");
puts(data);
j += strlen(data) + 1;
data += strlen(data) + 1;
}
puts("\"");
return;
}
switch (len) {
case 1: /* byte */
printf("<%02x>", (*(u8 *) data) & 0xff);
break;
case 2: /* half-word */
printf("<%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
break;
case 4: /* word */
printf("<%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
break;
case 8: /* double-word */
#if __WORDSIZE == 64
printf("<%016llx>", be64_to_cpu(*(uint64_t *) data));
#else
printf("<%08x ", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
data += 4;
printf("%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
#endif
break;
default: /* anything else... hexdump */
printf("[");
for (j = 0, s = data; j < len; j++)
printf("%02x%s", s[j], j < len - 1 ? " " : "");
printf("]");
break;
}
}
/********************************************************************/
U_BOOT_CMD(
fdt, 5, 0, do_fdt,
"fdt - flattened device tree utility commands\n",
"addr <addr> [<length>] - Set the fdt location to <addr>\n"
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr>\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
"fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n"
"fdt mknode <path> <node> - Create a new node after <path>\n"
"fdt rm <path> [<prop>] - Delete the node or <property>\n"
"fdt chosen - Add/update the \"/chosen\" branch in the tree\n"
#ifdef CONFIG_OF_HAS_UBOOT_ENV
"fdt env - Add/replace the \"/u-boot-env\" branch in the tree\n"
#endif
#ifdef CONFIG_OF_HAS_BD_T
"fdt bd_t - Add/replace the \"/bd_t\" branch in the tree\n"
#endif
"Hints:\n"
" * Set a larger length with the fdt addr command to add to the blob.\n"
" * If the property you are setting/printing has a '#' character,\n"
" you MUST escape it with a \\ character or quote it with \" or\n"
" it will be ignored as a comment.\n"
" * If the value has spaces in it, you MUST escape the spaces with\n"
" \\ characters or quote it with \"\"\n"
"Examples: fdt print / # print the whole tree\n"
" fdt print /cpus \"#address-cells\"\n"
" fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n"
);
#endif /* CONFIG_OF_LIBFDT */

3
common/cmd_i2c.c
View File

@ -969,7 +969,7 @@ U_BOOT_CMD(
"i2c sdram chip - print SDRAM configuration information\n"
#endif /* CFG_CMD_SDRAM */
);
#else /* CONFIG_I2C_CMD_TREE */
#endif /* CONFIG_I2C_CMD_TREE */
U_BOOT_CMD(
imd, 4, 1, do_i2c_md, \
"imd - i2c memory display\n", \
@ -1024,6 +1024,5 @@ U_BOOT_CMD(
" (valid chip values 50..57)\n"
);
#endif
#endif /* CONFIG_I2C_CMD_TREE */
#endif /* CFG_CMD_I2C */

21
common/cmd_ide.c
View File

@ -423,7 +423,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
part = simple_strtoul(++ep, NULL, 16);
}
if (get_partition_info (ide_dev_desc, part, &info)) {
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
SHOW_BOOT_PROGRESS (-1);
return 1;
}
@ -513,9 +513,11 @@ void ide_init (void)
#endif
unsigned char c;
int i, bus;
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
unsigned int ata_reset_time;
#endif
#ifdef CONFIG_AMIGAONEG3SE
unsigned int max_bus_scan;
unsigned int ata_reset_time;
char *s;
#endif
#ifdef CONFIG_IDE_8xx_PCCARD
@ -617,10 +619,9 @@ void ide_init (void)
udelay (100000); /* 100 ms */
ide_outb (dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
udelay (100000); /* 100 ms */
#ifdef CONFIG_AMIGAONEG3SE
ata_reset_time = ATA_RESET_TIME;
s = getenv("ide_reset_timeout");
if (s) ata_reset_time = 2*simple_strtol(s, NULL, 10);
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
if ((s = getenv("ide_reset_timeout")) != NULL)
ata_reset_time = simple_strtol(s, NULL, 10);
#endif
i = 0;
do {
@ -628,7 +629,7 @@ void ide_init (void)
c = ide_inb (dev, ATA_STATUS);
i++;
#ifdef CONFIG_AMIGAONEG3SE
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
if (i > (ata_reset_time * 100)) {
#else
if (i > (ATA_RESET_TIME * 100)) {
@ -1343,7 +1344,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
++n;
++blknr;
buffer += ATA_SECTORWORDS;
buffer += ATA_BLOCKSIZE;
}
IDE_READ_E:
ide_led (DEVICE_LED(device), 0); /* LED off */
@ -1427,7 +1428,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
c = ide_inb (device, ATA_STATUS); /* clear IRQ */
++n;
++blknr;
buffer += ATA_SECTORWORDS;
buffer += ATA_BLOCKSIZE;
}
WR_OUT:
ide_led (DEVICE_LED(device), 0); /* LED off */
@ -2051,7 +2052,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
n+=cnt;
blkcnt-=cnt;
blknr+=cnt;
buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */
buffer+=(cnt*ATAPI_READ_BLOCK_SIZE);
} while (blkcnt > 0);
return (n);
}

2
common/cmd_scsi.c
View File

@ -248,7 +248,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
part = simple_strtoul(++ep, NULL, 16);
}
if (get_partition_info (scsi_dev_desc, part, &info)) {
if (get_partition_info (&scsi_dev_desc[dev], part, &info)) {
printf("error reading partinfo\n");
return 1;
}

347
common/fdt_support.c Normal file
View File

@ -0,0 +1,347 @@
/*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/ctype.h>
#include <linux/types.h>
#ifdef CONFIG_OF_LIBFDT
#include <asm/global_data.h>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
/*
* Global data (for the gd->bd)
*/
DECLARE_GLOBAL_DATA_PTR;
/********************************************************************/
int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
bd_t *bd = gd->bd;
int nodeoffset;
int err;
u32 tmp; /* used to set 32 bit integer properties */
char *str; /* used to set string properties */
ulong clock;
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
if (initrd_start && initrd_end) {
struct fdt_reserve_entry re;
int used;
int total;
int j;
err = fdt_num_reservemap(fdt, &used, &total);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
if (used >= total) {
printf("fdt_chosen: no room in the reserved map (%d of %d)\n",
used, total);
return -1;
}
/*
* Look for an existing entry and update it. If we don't find
* the entry, we will j be the next available slot.
*/
for (j = 0; j < used; j++) {
err = fdt_get_reservemap(fdt, j, &re);
if (re.address == initrd_start) {
break;
}
}
err = fdt_replace_reservemap_entry(fdt, j,
initrd_start, initrd_end - initrd_start + 1);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Find the "chosen" node.
*/
nodeoffset = fdt_path_offset (fdt, "/chosen");
/*
* If we have a "chosen" node already the "force the writing"
* is not set, our job is done.
*/
if ((nodeoffset >= 0) && !force)
return 0;
/*
* No "chosen" node in the blob: create it.
*/
if (nodeoffset < 0) {
/*
* Create a new node "/chosen" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
}
/*
* Update pre-existing properties, create them if non-existant.
*/
str = getenv("bootargs");
if (str != NULL) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
if (initrd_start && initrd_end) {
tmp = __cpu_to_be32(initrd_start);
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
tmp = __cpu_to_be32(initrd_end);
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#ifdef OF_STDOUT_PATH
err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
#endif
nodeoffset = fdt_path_offset (fdt, "/cpus");
if (nodeoffset >= 0) {
clock = cpu_to_be32(bd->bi_intfreq);
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#ifdef OF_TBCLK
nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency");
if (nodeoffset >= 0) {
clock = cpu_to_be32(OF_TBCLK);
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
#endif
return err;
}
/********************************************************************/
#ifdef CONFIG_OF_HAS_UBOOT_ENV
/* Function that returns a character from the environment */
extern uchar(*env_get_char) (int);
int fdt_env(void *fdt)
{
int nodeoffset;
int err;
int k, nxt;
int i;
static char tmpenv[256];
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
/*
* See if we already have a "u-boot-env" node, delete it if so.
* Then create a new empty node.
*/
nodeoffset = fdt_path_offset (fdt, "/u-boot-env");
if (nodeoffset >= 0) {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Create a new node "/u-boot-env" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
char *s, *lval, *rval;
/*
* Find the end of the name=definition
*/
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
;
s = tmpenv;
for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
*s++ = env_get_char(k);
*s++ = '\0';
lval = tmpenv;
/*
* Find the first '=': it separates the name from the value
*/
s = strchr(tmpenv, '=');
if (s != NULL) {
*s++ = '\0';
rval = s;
} else
continue;
err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
return 0;
}
#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */
/********************************************************************/
#ifdef CONFIG_OF_HAS_BD_T
#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
static const struct {
const char *name;
int offset;
} bd_map[] = {
BDM(memstart),
BDM(memsize),
BDM(flashstart),
BDM(flashsize),
BDM(flashoffset),
BDM(sramstart),
BDM(sramsize),
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|| defined(CONFIG_E500)
BDM(immr_base),
#endif
#if defined(CONFIG_MPC5xxx)
BDM(mbar_base),
#endif
#if defined(CONFIG_MPC83XX)
BDM(immrbar),
#endif
#if defined(CONFIG_MPC8220)
BDM(mbar_base),
BDM(inpfreq),
BDM(pcifreq),
BDM(pevfreq),
BDM(flbfreq),
BDM(vcofreq),
#endif
BDM(bootflags),
BDM(ip_addr),
BDM(intfreq),
BDM(busfreq),
#ifdef CONFIG_CPM2
BDM(cpmfreq),
BDM(brgfreq),
BDM(sccfreq),
BDM(vco),
#endif
#if defined(CONFIG_MPC5xxx)
BDM(ipbfreq),
BDM(pcifreq),
#endif
BDM(baudrate),
};
int fdt_bd_t(void *fdt)
{
bd_t *bd = gd->bd;
int nodeoffset;
int err;
u32 tmp; /* used to set 32 bit integer properties */
int i;
err = fdt_check_header(fdt);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
/*
* See if we already have a "bd_t" node, delete it if so.
* Then create a new empty node.
*/
nodeoffset = fdt_path_offset (fdt, "/bd_t");
if (nodeoffset >= 0) {
err = fdt_del_node(fdt, nodeoffset);
if (err < 0) {
printf("libfdt: %s\n", fdt_strerror(err));
return err;
}
}
/*
* Create a new node "/bd_t" (offset 0 is root level)
*/
nodeoffset = fdt_add_subnode(fdt, 0, "bd_t");
if (nodeoffset < 0) {
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
return nodeoffset;
}
/*
* Use the string/pointer structure to create the entries...
*/
for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
tmp = cpu_to_be32(getenv("bootargs"));
err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp));
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
}
/*
* Add a couple of oddball entries...
*/
err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4);
if (err < 0)
printf("libfdt: %s\n", fdt_strerror(err));
return 0;
}
#endif /* ifdef CONFIG_OF_HAS_BD_T */
#endif /* CONFIG_OF_LIBFDT */

4
common/serial.c
View File

@ -41,7 +41,7 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
@ -91,7 +91,7 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif

46
cpu/74xx_7xx/cpu.c
View File

@ -44,6 +44,10 @@
#include <74xx_7xx.h>
#include <asm/cache.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#ifdef CONFIG_AMIGAONEG3SE
#include "../board/MAI/AmigaOneG3SE/via686.h"
#include "../board/MAI/AmigaOneG3SE/memio.h"
@ -101,6 +105,10 @@ get_cpu_type(void)
type = CPU_7457;
break;
case 0x8003:
type = CPU_7447A;
break;
case 0x8004:
type = CPU_7448;
break;
@ -156,6 +164,10 @@ int checkcpu (void)
str = "MPC7410";
break;
case CPU_7447A:
str = "MPC7447A";
break;
case CPU_7448:
str = "MPC7448";
break;
@ -264,20 +276,19 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
*/
#ifdef CONFIG_AMIGAONEG3SE
#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
unsigned long get_tbclk(void)
{
return (gd->bus_clk / 4);
}
#else /* ! CONFIG_AMIGAONEG3SE */
#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
unsigned long get_tbclk (void)
{
return CFG_BUS_HZ / 4;
}
#endif /* CONFIG_AMIGAONEG3SE */
#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
void
@ -289,3 +300,30 @@ watchdog_reset(void)
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup (void *blob, bd_t *bd)
{
u32 *p;
ulong clock;
int len;
clock = bd->bi_busfreq;
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32 (clock);
#if defined(CONFIG_TSI108_ETH)
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy (p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_HAS_ETH1)
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy (p, bd->bi_enet1addr, 6);
#endif
}
#endif
/* ------------------------------------------------------------------------- */

1
cpu/74xx_7xx/cpu_init.c
View File

@ -43,6 +43,7 @@ cpu_init_f (void)
case CPU_7450:
case CPU_7455:
case CPU_7457:
case CPU_7447A:
case CPU_7448:
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);

56
cpu/74xx_7xx/speed.c
View File

@ -31,6 +31,8 @@
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long get_board_bus_clk (void);
static const int hid1_multipliers_x_10[] = {
25, /* 0000 - 2.5x */
75, /* 0001 - 7.5x */
@ -50,6 +52,42 @@ static const int hid1_multipliers_x_10[] = {
0 /* 1111 - off */
};
/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */
static const int hid1_74xx_multipliers_x_10[] = {
115, /* 00000 - 11.5x */
170, /* 00001 - 17x */
75, /* 00010 - 7.5x */
150, /* 00011 - 15x */
70, /* 00100 - 7x */
180, /* 00101 - 18x */
10, /* 00110 - bypass */
200, /* 00111 - 20x */
20, /* 01000 - 2x */
210, /* 01001 - 21x */
65, /* 01010 - 6.5x */
130, /* 01011 - 13x */
85, /* 01100 - 8.5x */
240, /* 01101 - 24x */
95, /* 01110 - 9.5x */
90, /* 01111 - 9x */
30, /* 10000 - 3x */
105, /* 10001 - 10.5x */
55, /* 10010 - 5.5x */
110, /* 10011 - 11x */
40, /* 10100 - 4x */
100, /* 10101 - 10x */
50, /* 10110 - 5x */
120, /* 10111 - 12x */
80, /* 11000 - 8x */
140, /* 11001 - 14x */
60, /* 11010 - 6x */
160, /* 11011 - 16x */
135, /* 11100 - 13.5x */
280, /* 11101 - 28x */
0, /* 11110 - off */
125 /* 11111 - 12.5x */
};
static const int hid1_fx_multipliers_x_10[] = {
00, /* 0000 - off */
00, /* 0001 - off */
@ -89,22 +127,30 @@ int get_clocks (void)
{
ulong clock = 0;
#ifdef CFG_BUS_CLK
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#else
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#endif
/* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) {
case CPU_7447A:
case CPU_7448:
case CPU_7455:
case CPU_7457:
/*
* It is assumed that the PLL_EXT line is zero.
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
clock = (gd->bus_clk / 10) *
hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
break;
case CPU_750GX:
case CPU_750FX:
clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
clock = gd->bus_clk *
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break;
case CPU_7450:
@ -121,7 +167,8 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[get_hid1 () >> 28];
break;
case CPU_UNKNOWN:
@ -131,7 +178,6 @@ int get_clocks (void)
}
gd->cpu_clk = clock;
gd->bus_clk = CFG_BUS_CLK;
return (0);
}

2
cpu/at32ap/Makefile
View File

@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a
START := start.o
SOBJS := entry.o
COBJS := cpu.o hsdramc.o exception.o cache.o
COBJS += interrupts.o device.o pm.o pio.o
COBJS += interrupts.o pio.o atmel_mci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))

2
cpu/at32ap/at32ap7000/Makefile
View File

@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).a
COBJS := hebi.o devices.o
COBJS := gpio.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

448
cpu/at32ap/at32ap7000/devices.c
View File

@ -1,448 +0,0 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/memory-map.h>
#include <asm/arch/platform.h>
#include "../sm.h"
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
const struct clock_domain chip_clock[] = {
[CLOCK_CPU] = {
.reg = SM_PM_CPU_MASK,
.id = CLOCK_CPU,
.bridge = NO_DEVICE,
},
[CLOCK_HSB] = {
.reg = SM_PM_HSB_MASK,
.id = CLOCK_HSB,
.bridge = NO_DEVICE,
},
[CLOCK_PBA] = {
.reg = SM_PM_PBA_MASK,
.id = CLOCK_PBA,
.bridge = DEVICE_PBA_BRIDGE,
},
[CLOCK_PBB] = {
.reg = SM_PM_PBB_MASK,
.id = CLOCK_PBB,
.bridge = DEVICE_PBB_BRIDGE,
},
};
static const struct resource hebi_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 0 },
},
}, {
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 13 },
},
}, {
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 14 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
},
},
};
static const struct resource pba_bridge_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 1 },
}
}, {
.type = RESOURCE_CLOCK,
.u = {
/* HSB-HSB Bridge */
.clock = { CLOCK_HSB, 4 },
},
},
};
static const struct resource pbb_bridge_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 2 },
},
},
};
static const struct resource hramc_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 3 },
},
},
};
static const struct resource pioa_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 10 },
},
},
};
static const struct resource piob_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 11 },
},
},
};
static const struct resource pioc_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 12 },
},
},
};
static const struct resource piod_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 13 },
},
},
};
static const struct resource pioe_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 14 },
},
},
};
static const struct resource sm_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 0 },
},
},
};
static const struct resource intc_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 1 },
},
},
};
static const struct resource hmatrix_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 2 },
},
},
};
#if defined(CFG_HPDC)
static const struct resource hpdc_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 16 },
},
},
};
#endif
#if defined(CFG_MACB0)
static const struct resource macb0_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 8 },
},
}, {
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 6 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
},
},
};
#endif
#if defined(CFG_MACB1)
static const struct resource macb1_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 9 },
},
}, {
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 7 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
},
},
};
#endif
#if defined(CFG_LCDC)
static const struct resource lcdc_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 7 },
},
},
};
#endif
#if defined(CFG_USART0)
static const struct resource usart0_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 3 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
},
},
};
#endif
#if defined(CFG_USART1)
static const struct resource usart1_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 4 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
},
},
};
#endif
#if defined(CFG_USART2)
static const struct resource usart2_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 5 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
},
},
};
#endif
#if defined(CFG_USART3)
static const struct resource usart3_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBA, 6 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
},
},
};
#endif
#if defined(CFG_MMCI)
static const struct resource mmci_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_PBB, 9 },
},
}, {
.type = RESOURCE_GPIO,
.u = {
.gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
},
},
};
#endif
#if defined(CFG_DMAC)
static const struct resource dmac_resource[] = {
{
.type = RESOURCE_CLOCK,
.u = {
.clock = { CLOCK_HSB, 10 },
},
},
};
#endif
const struct device chip_device[] = {
[DEVICE_HEBI] = {
.regs = (void *)HSMC_BASE,
.nr_resources = ARRAY_SIZE(hebi_resource),
.resource = hebi_resource,
},
[DEVICE_PBA_BRIDGE] = {
.nr_resources = ARRAY_SIZE(pba_bridge_resource),
.resource = pba_bridge_resource,
},
[DEVICE_PBB_BRIDGE] = {
.nr_resources = ARRAY_SIZE(pbb_bridge_resource),
.resource = pbb_bridge_resource,
},
[DEVICE_HRAMC] = {
.nr_resources = ARRAY_SIZE(hramc_resource),
.resource = hramc_resource,
},
[DEVICE_PIOA] = {
.regs = (void *)PIOA_BASE,
.nr_resources = ARRAY_SIZE(pioa_resource),
.resource = pioa_resource,
},
[DEVICE_PIOB] = {
.regs = (void *)PIOB_BASE,
.nr_resources = ARRAY_SIZE(piob_resource),
.resource = piob_resource,
},
[DEVICE_PIOC] = {
.regs = (void *)PIOC_BASE,
.nr_resources = ARRAY_SIZE(pioc_resource),
.resource = pioc_resource,
},
[DEVICE_PIOD] = {
.regs = (void *)PIOD_BASE,
.nr_resources = ARRAY_SIZE(piod_resource),
.resource = piod_resource,
},
[DEVICE_PIOE] = {
.regs = (void *)PIOE_BASE,
.nr_resources = ARRAY_SIZE(pioe_resource),
.resource = pioe_resource,
},
[DEVICE_SM] = {
.regs = (void *)SM_BASE,
.nr_resources = ARRAY_SIZE(sm_resource),
.resource = sm_resource,
},
[DEVICE_INTC] = {
.regs = (void *)INTC_BASE,
.nr_resources = ARRAY_SIZE(intc_resource),
.resource = intc_resource,
},
[DEVICE_HMATRIX] = {
.regs = (void *)HMATRIX_BASE,
.nr_resources = ARRAY_SIZE(hmatrix_resource),
.resource = hmatrix_resource,
},
#if defined(CFG_HPDC)
[DEVICE_HPDC] = {
.nr_resources = ARRAY_SIZE(hpdc_resource),
.resource = hpdc_resource,
},
#endif
#if defined(CFG_MACB0)
[DEVICE_MACB0] = {
.regs = (void *)MACB0_BASE,
.nr_resources = ARRAY_SIZE(macb0_resource),
.resource = macb0_resource,
},
#endif
#if defined(CFG_MACB1)
[DEVICE_MACB1] = {
.regs = (void *)MACB1_BASE,
.nr_resources = ARRAY_SIZE(macb1_resource),
.resource = macb1_resource,
},
#endif
#if defined(CFG_LCDC)
[DEVICE_LCDC] = {
.nr_resources = ARRAY_SIZE(lcdc_resource),
.resource = lcdc_resource,
},
#endif
#if defined(CFG_USART0)
[DEVICE_USART0] = {
.regs = (void *)USART0_BASE,
.nr_resources = ARRAY_SIZE(usart0_resource),
.resource = usart0_resource,
},
#endif
#if defined(CFG_USART1)
[DEVICE_USART1] = {
.regs = (void *)USART1_BASE,
.nr_resources = ARRAY_SIZE(usart1_resource),
.resource = usart1_resource,
},
#endif
#if defined(CFG_USART2)
[DEVICE_USART2] = {
.regs = (void *)USART2_BASE,
.nr_resources = ARRAY_SIZE(usart2_resource),
.resource = usart2_resource,
},
#endif
#if defined(CFG_USART3)
[DEVICE_USART3] = {
.regs = (void *)USART3_BASE,
.nr_resources = ARRAY_SIZE(usart3_resource),
.resource = usart3_resource,
},
#endif
#if defined(CFG_MMCI)
[DEVICE_MMCI] = {
.regs = (void *)MMCI_BASE,
.nr_resources = ARRAY_SIZE(mmci_resource),
.resource = mmci_resource,
},
#endif
#if defined(CFG_DMAC)
[DEVICE_DMAC] = {
.regs = (void *)DMAC_BASE,
.nr_resources = ARRAY_SIZE(dmac_resource),
.resource = dmac_resource,
},
#endif
};

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cpu/at32ap/at32ap7000/gpio.c Normal file
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/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/gpio.h>
/*
* Lots of small functions here. We depend on --gc-sections getting
* rid of the ones we don't need.
*/
void gpio_enable_ebi(void)
{
#ifdef CFG_HSDRAMC
#ifndef CFG_SDRAM_16BIT
gpio_select_periph_A(GPIO_PIN_PE0, 0);
gpio_select_periph_A(GPIO_PIN_PE1, 0);
gpio_select_periph_A(GPIO_PIN_PE2, 0);
gpio_select_periph_A(GPIO_PIN_PE3, 0);
gpio_select_periph_A(GPIO_PIN_PE4, 0);
gpio_select_periph_A(GPIO_PIN_PE5, 0);
gpio_select_periph_A(GPIO_PIN_PE6, 0);
gpio_select_periph_A(GPIO_PIN_PE7, 0);
gpio_select_periph_A(GPIO_PIN_PE8, 0);
gpio_select_periph_A(GPIO_PIN_PE9, 0);
gpio_select_periph_A(GPIO_PIN_PE10, 0);
gpio_select_periph_A(GPIO_PIN_PE11, 0);
gpio_select_periph_A(GPIO_PIN_PE12, 0);
gpio_select_periph_A(GPIO_PIN_PE13, 0);
gpio_select_periph_A(GPIO_PIN_PE14, 0);
gpio_select_periph_A(GPIO_PIN_PE15, 0);
#endif
gpio_select_periph_A(GPIO_PIN_PE26, 0);
#endif
}
void gpio_enable_usart0(void)
{
gpio_select_periph_B(GPIO_PIN_PA8, 0);
gpio_select_periph_B(GPIO_PIN_PA9, 0);
}
void gpio_enable_usart1(void)
{
gpio_select_periph_A(GPIO_PIN_PA17, 0);
gpio_select_periph_A(GPIO_PIN_PA18, 0);
}
void gpio_enable_usart2(void)
{
gpio_select_periph_B(GPIO_PIN_PB26, 0);
gpio_select_periph_B(GPIO_PIN_PB27, 0);
}
void gpio_enable_usart3(void)
{
gpio_select_periph_B(GPIO_PIN_PB18, 0);
gpio_select_periph_B(GPIO_PIN_PB19, 0);
}
void gpio_enable_macb0(void)
{
gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
#if !defined(CONFIG_RMII)
gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */
#endif
}
void gpio_enable_macb1(void)
{
gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
#if !defined(CONFIG_RMII)
gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
#endif
}
void gpio_enable_mmci(void)
{
gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */
gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */
gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */
gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
}

477
cpu/at32ap/atmel_mci.c Normal file
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/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifdef CONFIG_MMC
#include <part.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
#include "atmel_mci.h"
#ifdef DEBUG
#define pr_debug(fmt, args...) printf(fmt, ##args)
#else
#define pr_debug(...) do { } while(0)
#endif
#ifndef CFG_MMC_CLK_OD
#define CFG_MMC_CLK_OD 150000
#endif
#ifndef CFG_MMC_CLK_PP
#define CFG_MMC_CLK_PP 5000000
#endif
#ifndef CFG_MMC_OP_COND
#define CFG_MMC_OP_COND 0x00100000
#endif
#define MMC_DEFAULT_BLKLEN 512
#define MMC_DEFAULT_RCA 1
static unsigned int mmc_rca;
static block_dev_desc_t mmc_blkdev;
block_dev_desc_t *mmc_get_dev(int dev)
{
return &mmc_blkdev;
}
static void mci_set_mode(unsigned long hz, unsigned long blklen)
{
unsigned long bus_hz;
unsigned long clkdiv;
bus_hz = get_mci_clk_rate();
clkdiv = (bus_hz / hz) / 2 - 1;
pr_debug("mmc: setting clock %lu Hz, block size %lu\n",
hz, blklen);
if (clkdiv & ~255UL) {
clkdiv = 255;
printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
hz);
}
blklen &= 0xfffc;
mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
| MMCI_BF(BLKLEN, blklen)));
}
#define RESP_NO_CRC 1
#define R1 MMCI_BF(RSPTYP, 1)
#define R2 MMCI_BF(RSPTYP, 2)
#define R3 (R1 | RESP_NO_CRC)
#define R6 R1
#define NID MMCI_BF(MAXLAT, 0)
#define NCR MMCI_BF(MAXLAT, 1)
#define TRCMD_START MMCI_BF(TRCMD, 1)
#define TRDIR_READ MMCI_BF(TRDIR, 1)
#define TRTYP_BLOCK MMCI_BF(TRTYP, 0)
#define INIT_CMD MMCI_BF(SPCMD, 1)
#define OPEN_DRAIN MMCI_BF(OPDCMD, 1)
#define ERROR_FLAGS (MMCI_BIT(DTOE) \
| MMCI_BIT(RDIRE) \
| MMCI_BIT(RENDE) \
| MMCI_BIT(RINDE) \
| MMCI_BIT(RTOE))
static int
mmc_cmd(unsigned long cmd, unsigned long arg,
void *resp, unsigned long flags)
{
unsigned long *response = resp;
int i, response_words = 0;
unsigned long error_flags;
u32 status;
pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n",
cmd, arg, flags);
error_flags = ERROR_FLAGS;
if (!(flags & RESP_NO_CRC))
error_flags |= MMCI_BIT(RCRCE);
flags &= ~MMCI_BF(CMDNB, ~0UL);
if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
response_words = 1;
else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
response_words = 4;
mmci_writel(ARGR, arg);
mmci_writel(CMDR, cmd | flags);
do {
udelay(40);
status = mmci_readl(SR);
} while (!(status & MMCI_BIT(CMDRDY)));
pr_debug("mmc: status 0x%08lx\n", status);
if (status & ERROR_FLAGS) {
printf("mmc: command %lu failed (status: 0x%08lx)\n",
cmd, status);
return -EIO;
}
if (response_words)
pr_debug("mmc: response:");
for (i = 0; i < response_words; i++) {
response[i] = mmci_readl(RSPR);
pr_debug(" %08lx", response[i]);
}
pr_debug("\n");
return 0;
}
static int mmc_acmd(unsigned long cmd, unsigned long arg,
void *resp, unsigned long flags)
{
unsigned long aresp[4];
int ret;
/*
* Seems like the APP_CMD part of an ACMD has 64 cycles max
* latency even though the ACMD part doesn't. This isn't
* entirely clear in the SD Card spec, but some cards refuse
* to work if we attempt to use 5 cycles max latency here...
*/
ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
R1 | NCR | (flags & OPEN_DRAIN));
if (ret)
return ret;
if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
return -ENODEV;
ret = mmc_cmd(cmd, arg, resp, flags);
return ret;
}
static unsigned long
mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
unsigned long *buffer)
{
int ret, i = 0;
unsigned long resp[4];
unsigned long card_status, data;
unsigned long wordcount;
u32 status;
if (blkcnt == 0)
return 0;
pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n",
dev, start, blkcnt);
/* Put the device into Transfer state */
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
if (ret) goto fail;
/* Set block length */
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
if (ret) goto fail;
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
for (i = 0; i < blkcnt; i++, start++) {
ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
start * mmc_blkdev.blksz, resp,
(R1 | NCR | TRCMD_START | TRDIR_READ
| TRTYP_BLOCK));
if (ret) goto fail;
ret = -EIO;
wordcount = 0;
do {
do {
status = mmci_readl(SR);
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
goto fail;
} while (!(status & MMCI_BIT(RXRDY)));
if (status & MMCI_BIT(RXRDY)) {
data = mmci_readl(RDR);
/* pr_debug("%x\n", data); */
*buffer++ = data;
wordcount++;
}
} while(wordcount < (512 / 4));
pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount);
do {
status = mmci_readl(SR);
} while (!(status & MMCI_BIT(BLKE)));
putc('.');
}
out:
/* Put the device back into Standby state */
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
return i;
fail:
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
printf("mmc: bread failed, card status = ", card_status);
goto out;
}
static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = resp[2] >> 24;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 16;
cid->psn = (resp[2] << 16) | (resp[3] >> 16);
cid->mdt = resp[3] >> 8;
}
static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = 0;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 24;
cid->psn = (resp[2] << 8) | (resp[3] >> 24);
cid->mdt = (resp[3] >> 8) & 0x0fff;
}
static void mmc_dump_cid(const struct mmc_cid *cid)
{
printf("Manufacturer ID: %02lX\n", cid->mid);
printf("OEM/Application ID: %04lX\n", cid->oid);
printf("Product name: %s\n", cid->pnm);
printf("Product Revision: %lu.%lu\n",
cid->prv >> 4, cid->prv & 0x0f);
printf("Product Serial Number: %lu\n", cid->psn);
printf("Manufacturing Date: %02lu/%02lu\n",
cid->mdt >> 4, cid->mdt & 0x0f);
}
static void mmc_dump_csd(const struct mmc_csd *csd)
{
unsigned long *csd_raw = (unsigned long *)csd;
printf("CSD data: %08lx %08lx %08lx %08lx\n",
csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]);
printf("CSD structure version: 1.%u\n", csd->csd_structure);
printf("MMC System Spec version: %u\n", csd->spec_vers);
printf("Card command classes: %03x\n", csd->ccc);
printf("Read block length: %u\n", 1 << csd->read_bl_len);
if (csd->read_bl_partial)
puts("Supports partial reads\n");
else
puts("Does not support partial reads\n");
printf("Write block length: %u\n", 1 << csd->write_bl_len);
if (csd->write_bl_partial)
puts("Supports partial writes\n");
else
puts("Does not support partial writes\n");
if (csd->wp_grp_enable)
printf("Supports group WP: %u\n", csd->wp_grp_size + 1);
else
puts("Does not support group WP\n");
printf("Card capacity: %u bytes\n",
(csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) *
(1 << csd->read_bl_len));
printf("File format: %u/%u\n",
csd->file_format_grp, csd->file_format);
puts("Write protection: ");
if (csd->perm_write_protect)
puts(" permanent");
if (csd->tmp_write_protect)
puts(" temporary");
putc('\n');
}
static int mmc_idle_cards(void)
{
int ret;
/* Reset and initialize all cards */
ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
if (ret)
return ret;
/* Keep the bus idle for 74 clock cycles */
return mmc_cmd(0, 0, NULL, INIT_CMD);
}
static int sd_init_card(struct mmc_cid *cid, int verbose)
{
unsigned long resp[4];
int i, ret = 0;
mmc_idle_cards();
for (i = 0; i < 1000; i++) {
ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND,
resp, R3 | NID);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
if (ret)
return ret;
sd_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Get RCA of the card that responded */
ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
if (ret)
return ret;
mmc_rca = resp[0] >> 16;
if (verbose)
printf("SD Card detected (RCA %u)\n", mmc_rca);
return 0;
}
static int mmc_init_card(struct mmc_cid *cid, int verbose)
{
unsigned long resp[4];
int i, ret = 0;
mmc_idle_cards();
for (i = 0; i < 1000; i++) {
ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
R3 | NID | OPEN_DRAIN);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
/* Get CID of all cards. FIXME: Support more than one card */
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
if (ret)
return ret;
mmc_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Set Relative Address of the card that responded */
ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
R1 | NCR | OPEN_DRAIN);
return ret;
}
int mmc_init(int verbose)
{
struct mmc_cid cid;
struct mmc_csd csd;
int ret;
/* Initialize controller */
mmci_writel(CR, MMCI_BIT(SWRST));
mmci_writel(CR, MMCI_BIT(MCIEN));
mmci_writel(DTOR, 0x5f);
mmci_writel(IDR, ~0UL);
mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
ret = sd_init_card(&cid, verbose);
if (ret) {
mmc_rca = MMC_DEFAULT_RCA;
ret = mmc_init_card(&cid, verbose);
}
if (ret)
return ret;
/* Get CSD from the card */
ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR);
if (ret)
return ret;
if (verbose)
mmc_dump_csd(&csd);
/* Initialize the blockdev structure */
mmc_blkdev.if_type = IF_TYPE_MMC;
mmc_blkdev.part_type = PART_TYPE_DOS;
mmc_blkdev.block_read = mmc_bread;
sprintf((char *)mmc_blkdev.vendor,
"Man %02x%04x Snr %08x",
cid.mid, cid.oid, cid.psn);
strncpy((char *)mmc_blkdev.product, cid.pnm,
sizeof(mmc_blkdev.product));
sprintf((char *)mmc_blkdev.revision, "%x %x",
cid.prv >> 4, cid.prv & 0x0f);
mmc_blkdev.blksz = 1 << csd.read_bl_len;
mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2));
mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
#if 0
if (fat_register_device(&mmc_blkdev, 1))
printf("Could not register MMC fat device\n");
#else
init_part(&mmc_blkdev);
#endif
return 0;
}
int mmc_read(ulong src, uchar *dst, int size)
{
return -ENOSYS;
}
int mmc_write(uchar *src, ulong dst, int size)
{
return -ENOSYS;
}
int mmc2info(ulong addr)
{
return 0;
}
#endif /* CONFIG_MMC */

197
cpu/at32ap/atmel_mci.h Normal file
View File

@ -0,0 +1,197 @@
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CPU_AT32AP_ATMEL_MCI_H__
#define __CPU_AT32AP_ATMEL_MCI_H__
/* Atmel MultiMedia Card Interface (MCI) registers */
#define MMCI_CR 0x0000
#define MMCI_MR 0x0004
#define MMCI_DTOR 0x0008
#define MMCI_SDCR 0x000c
#define MMCI_ARGR 0x0010
#define MMCI_CMDR 0x0014
#define MMCI_RSPR 0x0020
#define MMCI_RSPR1 0x0024
#define MMCI_RSPR2 0x0028
#define MMCI_RSPR3 0x002c
#define MMCI_RDR 0x0030
#define MMCI_TDR 0x0034
#define MMCI_SR 0x0040
#define MMCI_IER 0x0044
#define MMCI_IDR 0x0048
#define MMCI_IMR 0x004c
/* Bitfields in CR */
#define MMCI_MCIEN_OFFSET 0
#define MMCI_MCIEN_SIZE 1
#define MMCI_MCIDIS_OFFSET 1
#define MMCI_MCIDIS_SIZE 1
#define MMCI_PWSEN_OFFSET 2
#define MMCI_PWSEN_SIZE 1
#define MMCI_PWSDIS_OFFSET 3
#define MMCI_PWSDIS_SIZE 1
#define MMCI_SWRST_OFFSET 7
#define MMCI_SWRST_SIZE 1
/* Bitfields in MR */
#define MMCI_CLKDIV_OFFSET 0
#define MMCI_CLKDIV_SIZE 8
#define MMCI_PWSDIV_OFFSET 8
#define MMCI_PWSDIV_SIZE 3
#define MMCI_PDCPADV_OFFSET 14
#define MMCI_PDCPADV_SIZE 1
#define MMCI_PDCMODE_OFFSET 15
#define MMCI_PDCMODE_SIZE 1
#define MMCI_BLKLEN_OFFSET 16
#define MMCI_BLKLEN_SIZE 16
/* Bitfields in DTOR */
#define MMCI_DTOCYC_OFFSET 0
#define MMCI_DTOCYC_SIZE 4
#define MMCI_DTOMUL_OFFSET 4
#define MMCI_DTOMUL_SIZE 3
/* Bitfields in SDCR */
#define MMCI_SCDSEL_OFFSET 0
#define MMCI_SCDSEL_SIZE 4
#define MMCI_SCDBUS_OFFSET 7
#define MMCI_SCDBUS_SIZE 1
/* Bitfields in ARGR */
#define MMCI_ARG_OFFSET 0
#define MMCI_ARG_SIZE 32
/* Bitfields in CMDR */
#define MMCI_CMDNB_OFFSET 0
#define MMCI_CMDNB_SIZE 6
#define MMCI_RSPTYP_OFFSET 6
#define MMCI_RSPTYP_SIZE 2
#define MMCI_SPCMD_OFFSET 8
#define MMCI_SPCMD_SIZE 3
#define MMCI_OPDCMD_OFFSET 11
#define MMCI_OPDCMD_SIZE 1
#define MMCI_MAXLAT_OFFSET 12
#define MMCI_MAXLAT_SIZE 1
#define MMCI_TRCMD_OFFSET 16
#define MMCI_TRCMD_SIZE 2
#define MMCI_TRDIR_OFFSET 18
#define MMCI_TRDIR_SIZE 1
#define MMCI_TRTYP_OFFSET 19
#define MMCI_TRTYP_SIZE 2
/* Bitfields in RSPRx */
#define MMCI_RSP_OFFSET 0
#define MMCI_RSP_SIZE 32
/* Bitfields in SR/IER/IDR/IMR */
#define MMCI_CMDRDY_OFFSET 0
#define MMCI_CMDRDY_SIZE 1
#define MMCI_RXRDY_OFFSET 1
#define MMCI_RXRDY_SIZE 1
#define MMCI_TXRDY_OFFSET 2
#define MMCI_TXRDY_SIZE 1
#define MMCI_BLKE_OFFSET 3
#define MMCI_BLKE_SIZE 1
#define MMCI_DTIP_OFFSET 4
#define MMCI_DTIP_SIZE 1
#define MMCI_NOTBUSY_OFFSET 5
#define MMCI_NOTBUSY_SIZE 1
#define MMCI_ENDRX_OFFSET 6
#define MMCI_ENDRX_SIZE 1
#define MMCI_ENDTX_OFFSET 7
#define MMCI_ENDTX_SIZE 1
#define MMCI_RXBUFF_OFFSET 14
#define MMCI_RXBUFF_SIZE 1
#define MMCI_TXBUFE_OFFSET 15
#define MMCI_TXBUFE_SIZE 1
#define MMCI_RINDE_OFFSET 16
#define MMCI_RINDE_SIZE 1
#define MMCI_RDIRE_OFFSET 17
#define MMCI_RDIRE_SIZE 1
#define MMCI_RCRCE_OFFSET 18
#define MMCI_RCRCE_SIZE 1
#define MMCI_RENDE_OFFSET 19
#define MMCI_RENDE_SIZE 1
#define MMCI_RTOE_OFFSET 20
#define MMCI_RTOE_SIZE 1
#define MMCI_DCRCE_OFFSET 21
#define MMCI_DCRCE_SIZE 1
#define MMCI_DTOE_OFFSET 22
#define MMCI_DTOE_SIZE 1
#define MMCI_OVRE_OFFSET 30
#define MMCI_OVRE_SIZE 1
#define MMCI_UNRE_OFFSET 31
#define MMCI_UNRE_SIZE 1
/* Constants for DTOMUL */
#define MMCI_DTOMUL_1_CYCLE 0
#define MMCI_DTOMUL_16_CYCLES 1
#define MMCI_DTOMUL_128_CYCLES 2
#define MMCI_DTOMUL_256_CYCLES 3
#define MMCI_DTOMUL_1024_CYCLES 4
#define MMCI_DTOMUL_4096_CYCLES 5
#define MMCI_DTOMUL_65536_CYCLES 6
#define MMCI_DTOMUL_1048576_CYCLES 7
/* Constants for RSPTYP */
#define MMCI_RSPTYP_NO_RESP 0
#define MMCI_RSPTYP_48_BIT_RESP 1
#define MMCI_RSPTYP_136_BIT_RESP 2
/* Constants for SPCMD */
#define MMCI_SPCMD_NO_SPEC_CMD 0
#define MMCI_SPCMD_INIT_CMD 1
#define MMCI_SPCMD_SYNC_CMD 2
#define MMCI_SPCMD_INT_CMD 4
#define MMCI_SPCMD_INT_RESP 5
/* Constants for TRCMD */
#define MMCI_TRCMD_NO_TRANS 0
#define MMCI_TRCMD_START_TRANS 1
#define MMCI_TRCMD_STOP_TRANS 2
/* Constants for TRTYP */
#define MMCI_TRTYP_BLOCK 0
#define MMCI_TRTYP_MULTI_BLOCK 1
#define MMCI_TRTYP_STREAM 2
/* Bit manipulation macros */
#define MMCI_BIT(name) \
(1 << MMCI_##name##_OFFSET)
#define MMCI_BF(name,value) \
(((value) & ((1 << MMCI_##name##_SIZE) - 1)) \
<< MMCI_##name##_OFFSET)
#define MMCI_BFEXT(name,value) \
(((value) >> MMCI_##name##_OFFSET)\
& ((1 << MMCI_##name##_SIZE) - 1))
#define MMCI_BFINS(name,value,old) \
(((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \
<< MMCI_##name##_OFFSET)) \
| MMCI_BF(name,value))
/* Register access macros */
#define mmci_readl(reg) \
readl((void *)MMCI_BASE + MMCI_##reg)
#define mmci_writel(reg,value) \
writel((value), (void *)MMCI_BASE + MMCI_##reg)
#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */

64
cpu/at32ap/cpu.c
View File

@ -26,33 +26,79 @@
#include <asm/sections.h>
#include <asm/sysreg.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
#include <asm/arch/platform.h>
#include "hsmc3.h"
#include "sm.h"
/* Sanity checks */
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
#endif
#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
# error Invalid PLL multiplier and/or divider
#endif
DECLARE_GLOBAL_DATA_PTR;
static void pm_init(void)
{
uint32_t cksel;
#ifdef CONFIG_PLL
/* Initialize the PLL */
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
| SM_BF(PLLOPT, CFG_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
/* Wait for lock */
while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
#endif
/* Set up clocks for the CPU and all peripheral buses */
cksel = 0;
if (CFG_CLKDIV_CPU)
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
if (CFG_CLKDIV_HSB)
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
if (CFG_CLKDIV_PBA)
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
if (CFG_CLKDIV_PBB)
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
sm_writel(PM_CKSEL, cksel);
gd->cpu_hz = get_cpu_clk_rate();
#ifdef CONFIG_PLL
/* Use PLL0 as main clock */
sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
#endif
}
int cpu_init(void)
{
const struct device *hebi;
extern void _evba(void);
char *p;
gd->cpu_hz = CFG_OSC0_HZ;
/* fff03400: 00010001 04030402 00050005 10011103 */
hebi = get_device(DEVICE_HEBI);
hsmc3_writel(hebi, MODE0, 0x00031103);
hsmc3_writel(hebi, CYCLE0, 0x000c000d);
hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
hsmc3_writel(hebi, SETUP0, 0x00010002);
/* TODO: Move somewhere else, but needs to be run before we
* increase the clock frequency. */
hsmc3_writel(MODE0, 0x00031103);
hsmc3_writel(CYCLE0, 0x000c000d);
hsmc3_writel(PULSE0, 0x0b0a0906);
hsmc3_writel(SETUP0, 0x00010002);
pm_init();
sysreg_write(EVBA, (unsigned long)&_evba);
asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
/* Lock everything that mess with the flash in the icache */
for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);

126
cpu/at32ap/device.c
View File

@ -1,126 +0,0 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/platform.h>
#include "sm.h"
struct device_state {
int refcount;
};
static struct device_state device_state[NR_DEVICES];
static int claim_resource(const struct resource *res)
{
int ret = 0;
switch (res->type) {
case RESOURCE_GPIO:
ret = gpio_set_func(res->u.gpio.gpio_dev,
res->u.gpio.start,
res->u.gpio.nr_pins,
res->u.gpio.func);
break;
case RESOURCE_CLOCK:
ret = pm_enable_clock(res->u.clock.id, res->u.clock.index);
break;
}
return ret;
}
static void free_resource(const struct resource *res)
{
switch (res->type) {
case RESOURCE_GPIO:
gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start,
res->u.gpio.nr_pins);
break;
case RESOURCE_CLOCK:
pm_disable_clock(res->u.clock.id, res->u.clock.index);
break;
}
}
static int init_dev(const struct device *dev)
{
unsigned int i;
int ret = 0;
for (i = 0; i < dev->nr_resources; i++) {
ret = claim_resource(&dev->resource[i]);
if (ret)
goto cleanup;
}
return 0;
cleanup:
while (i--)
free_resource(&dev->resource[i]);
return ret;
}
const struct device *get_device(enum device_id devid)
{
struct device_state *devstate;
const struct device *dev;
unsigned long flags;
int initialized = 0;
int ret = 0;
devstate = &device_state[devid];
dev = &chip_device[devid];
flags = disable_interrupts();
if (devstate->refcount++)
initialized = 1;
if (flags)
enable_interrupts();
if (!initialized)
ret = init_dev(dev);
return ret ? NULL : dev;
}
void put_device(const struct device *dev)
{
struct device_state *devstate;
unsigned long devid, flags;
devid = (unsigned long)(dev - chip_device) / sizeof(struct device);
devstate = &device_state[devid];
flags = disable_interrupts();
devstate--;
if (!devstate) {
unsigned int i;
for (i = 0; i < dev->nr_resources; i++)
free_resource(&dev->resource[i]);
}
if (flags)
enable_interrupts();
}

3
cpu/at32ap/entry.S
View File

@ -42,8 +42,7 @@ timer_interrupt_handler:
* We're running at interrupt level 3, so we don't need to save
* r8-r12 or lr to the stack.
*/
mov r8, lo(timer_overflow)
orh r8, hi(timer_overflow)
lda.w r8, timer_overflow
ld.w r9, r8[0]
mov r10, -1
mtsr SYSREG_COMPARE, r10

7
cpu/at32ap/exception.c
View File

@ -24,6 +24,8 @@
#include <asm/sysreg.h>
#include <asm/ptrace.h>
DECLARE_GLOBAL_DATA_PTR;
static const char * const cpu_modes[8] = {
"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
@ -109,11 +111,10 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
if (regs->sp >= CFG_INIT_SP_ADDR
|| regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE))
if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR);
dump_mem("\nStack: ", regs->sp, gd->stack_end);
panic("Unhandled exception\n");
}

43
cpu/at32ap/hsdramc.c
View File

@ -25,17 +25,11 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/platform.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
#include "hsdramc1.h"
struct hsdramc {
const struct device *hebi;
void *regs;
};
static struct hsdramc hsdramc;
unsigned long sdram_init(const struct sdram_info *info)
{
unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
@ -44,16 +38,6 @@ unsigned long sdram_init(const struct sdram_info *info)
unsigned long bus_hz;
unsigned int i;
hsdramc.hebi = get_device(DEVICE_HEBI);
if (!hsdramc.hebi)
return 0;
/* FIXME: Both of these lines are complete hacks */
hsdramc.regs = hsdramc.hebi->regs + 0x400;
bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
cpu_enable_sdram();
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
| HSDRAMC1_BF(NR, info->row_bits - 11)
| HSDRAMC1_BF(NB, info->bank_bits - 1)
@ -74,7 +58,7 @@ unsigned long sdram_init(const struct sdram_info *info)
+ info->bank_bits + 2);
#endif
hsdramc1_writel(&hsdramc, CR, tmp);
hsdramc1_writel(CR, tmp);
/*
* Initialization sequence for SDRAM, from the data sheet:
@ -87,15 +71,15 @@ unsigned long sdram_init(const struct sdram_info *info)
/*
* 2. A Precharge All command is issued to the SDRAM
*/
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
hsdramc1_readl(&hsdramc, MR);
hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
hsdramc1_readl(MR);
writel(0, sdram);
/*
* 3. Eight auto-refresh (CBR) cycles are provided
*/
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
hsdramc1_readl(&hsdramc, MR);
hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
hsdramc1_readl(MR);
for (i = 0; i < 8; i++)
writel(0, sdram);
@ -106,8 +90,8 @@ unsigned long sdram_init(const struct sdram_info *info)
*
* CAS from info struct, burst length 1, serial burst type
*/
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
hsdramc1_readl(&hsdramc, MR);
hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
hsdramc1_readl(MR);
writel(0, sdram + (info->cas << 4));
/*
@ -117,9 +101,9 @@ unsigned long sdram_init(const struct sdram_info *info)
* From the timing diagram, it looks like tMRD is 3
* cycles...try a dummy read from the peripheral bus.
*/
hsdramc1_readl(&hsdramc, MR);
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
hsdramc1_readl(&hsdramc, MR);
hsdramc1_readl(MR);
hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
hsdramc1_readl(MR);
writel(0, sdram);
/*
@ -128,7 +112,8 @@ unsigned long sdram_init(const struct sdram_info *info)
*
* 15.6 us is a typical value for a burst of length one
*/
hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
bus_hz = get_sdram_clk_rate();
hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000);
printf("SDRAM: %u MB at address 0x%08lx\n",
sdram_size >> 20, info->phys_addr);

8
cpu/at32ap/hsdramc1.h
View File

@ -135,9 +135,9 @@
| HSDRAMC1_BF(name,value))
/* Register access macros */
#define hsdramc1_readl(port,reg) \
readl((port)->regs + HSDRAMC1_##reg)
#define hsdramc1_writel(port,reg,value) \
writel((value), (port)->regs + HSDRAMC1_##reg)
#define hsdramc1_readl(reg) \
readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg)
#define hsdramc1_writel(reg,value) \
writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg)
#endif /* __ASM_AVR32_HSDRAMC1_H__ */

8
cpu/at32ap/hsmc3.h
View File

@ -118,9 +118,9 @@
| HSMC3_BF(name,value))
/* Register access macros */
#define hsmc3_readl(port,reg) \
readl((port)->regs + HSMC3_##reg)
#define hsmc3_writel(port,reg,value) \
writel((value), (port)->regs + HSMC3_##reg)
#define hsmc3_readl(reg) \
readl((void *)HSMC_BASE + HSMC3_##reg)
#define hsmc3_writel(reg,value) \
writel((value), (void *)HSMC_BASE + HSMC3_##reg)
#endif /* __CPU_AT32AP_HSMC3_H__ */

14
cpu/at32ap/interrupts.c
View File

@ -27,7 +27,7 @@
#include <asm/processor.h>
#include <asm/sysreg.h>
#include <asm/arch/platform.h>
#include <asm/arch/memory-map.h>
#define HANDLER_MASK 0x00ffffff
#define INTLEV_SHIFT 30
@ -44,8 +44,6 @@ volatile unsigned long timer_overflow;
*/
static unsigned long tb_factor;
static const struct device *intc_dev;
unsigned long get_tbclk(void)
{
return gd->cpu_hz;
@ -117,16 +115,19 @@ void udelay(unsigned long usec)
static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
unsigned int priority)
{
extern void _evba(void);
unsigned long intpr;
unsigned long handler_addr = (unsigned long)handler;
handler_addr -= (unsigned long)&_evba;
if ((handler_addr & HANDLER_MASK) != handler_addr
|| (priority & INTLEV_MASK) != priority)
return -EINVAL;
intpr = (handler_addr & HANDLER_MASK);
intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
writel(intpr, intc_dev->regs + 4 * nr);
writel(intpr, (void *)INTC_BASE + 4 * nr);
return 0;
}
@ -143,10 +144,7 @@ void timer_init(void)
do_div(tmp, gd->cpu_hz);
tb_factor = (u32)tmp;
intc_dev = get_device(DEVICE_INTC);
if (!intc_dev
|| set_interrupt_handler(0, &timer_interrupt_handler, 3))
if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
return;
/* For all practical purposes, this gives us an overflow interrupt */

82
cpu/at32ap/pio.c
View File

@ -21,74 +21,40 @@
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
#include <asm/arch/gpio.h>
#include <asm/arch/memory-map.h>
#include "pio2.h"
struct pio_state {
const struct device *dev;
u32 alloc_mask;
};
static struct pio_state pio_state[CFG_NR_PIOS];
int gpio_set_func(enum device_id gpio_devid, unsigned int start,
unsigned int nr_pins, enum gpio_func func)
void gpio_select_periph_A(unsigned int pin, int use_pullup)
{
const struct device *gpio;
struct pio_state *state;
u32 mask;
void *base = gpio_pin_to_addr(pin);
uint32_t mask = 1 << (pin & 0x1f);
state = &pio_state[gpio_devid - DEVICE_PIOA];
if (!base)
panic("Invalid GPIO pin %u\n", pin);
gpio = get_device(gpio_devid);
if (!gpio)
return -EBUSY;
state->dev = gpio;
mask = ((1 << nr_pins) - 1) << start;
if (mask & state->alloc_mask) {
put_device(gpio);
return -EBUSY;
}
state->alloc_mask |= mask;
switch (func) {
case GPIO_FUNC_GPIO:
/* TODO */
return -EINVAL;
case GPIO_FUNC_A:
pio2_writel(gpio, ASR, mask);
pio2_writel(gpio, PDR, mask);
pio2_writel(gpio, PUDR, mask);
break;
case GPIO_FUNC_B:
pio2_writel(gpio, BSR, mask);
pio2_writel(gpio, PDR, mask);
pio2_writel(gpio, PUDR, mask);
break;
}
return 0;
pio2_writel(base, ASR, mask);
pio2_writel(base, PDR, mask);
if (use_pullup)
pio2_writel(base, PUER, mask);
else
pio2_writel(base, PUDR, mask);
}
void gpio_free(enum device_id gpio_devid, unsigned int start,
unsigned int nr_pins)
void gpio_select_periph_B(unsigned int pin, int use_pullup)
{
const struct device *gpio;
struct pio_state *state;
u32 mask;
void *base = gpio_pin_to_addr(pin);
uint32_t mask = 1 << (pin & 0x1f);
state = &pio_state[gpio_devid - DEVICE_PIOA];
gpio = state->dev;
mask = ((1 << nr_pins) - 1) << start;
if (!base)
panic("Invalid GPIO pin %u\n", pin);
pio2_writel(gpio, ODR, mask);
pio2_writel(gpio, PER, mask);
state->alloc_mask &= ~mask;
put_device(gpio);
pio2_writel(base, BSR, mask);
pio2_writel(base, PDR, mask);
if (use_pullup)
pio2_writel(base, PUER, mask);
else
pio2_writel(base, PUDR, mask);
}

8
cpu/at32ap/pio2.h
View File

@ -36,9 +36,9 @@
#define PIO2_OWSR 0x00a8
/* Register access macros */
#define pio2_readl(port,reg) \
readl((port)->regs + PIO2_##reg)
#define pio2_writel(port,reg,value) \
writel((value), (port)->regs + PIO2_##reg)
#define pio2_readl(base,reg) \
readl((void *)base + PIO2_##reg)
#define pio2_writel(base,reg,value) \
writel((value), (void *)base + PIO2_##reg)
#endif /* __CPU_AT32AP_PIO2_H__ */

131
cpu/at32ap/pm.c
View File

@ -26,138 +26,17 @@
#include <asm/io.h>
#include <asm/arch/memory-map.h>
#include <asm/arch/platform.h>
#include "sm.h"
/* Sanity checks */
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
#endif
#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
# error Invalid PLL multiplier and/or divider
#ifdef CONFIG_PLL
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
#else
#define MAIN_CLK_RATE (CFG_OSC0_HZ)
#endif
DECLARE_GLOBAL_DATA_PTR;
struct clock_domain_state {
const struct device *bridge;
unsigned long freq;
u32 mask;
};
static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
int pm_enable_clock(enum clock_domain_id id, unsigned int index)
{
const struct clock_domain *ckd = &chip_clock[id];
struct clock_domain_state *state = &ckd_state[id];
if (ckd->bridge != NO_DEVICE) {
state->bridge = get_device(ckd->bridge);
if (!state->bridge)
return -EBUSY;
}
state->mask |= 1 << index;
if (gd->sm)
writel(state->mask, gd->sm->regs + ckd->reg);
return 0;
}
void pm_disable_clock(enum clock_domain_id id, unsigned int index)
{
const struct clock_domain *ckd = &chip_clock[id];
struct clock_domain_state *state = &ckd_state[id];
state->mask &= ~(1 << index);
if (gd->sm)
writel(state->mask, gd->sm->regs + ckd->reg);
if (ckd->bridge)
put_device(state->bridge);
}
unsigned long pm_get_clock_freq(enum clock_domain_id domain)
{
return ckd_state[domain].freq;
}
void pm_init(void)
{
uint32_t cksel = 0;
unsigned long main_clock;
/* Make sure we don't disable any device we're already using */
get_device(DEVICE_HRAMC);
get_device(DEVICE_HEBI);
/* Enable the PICO as well */
ckd_state[CLOCK_CPU].mask |= 1;
gd->sm = get_device(DEVICE_SM);
if (!gd->sm)
panic("Unable to claim system manager device!\n");
/* Disable any devices that haven't been explicitly claimed */
sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
#ifdef CONFIG_PLL
/* Initialize the PLL */
main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
| SM_BF(PLLOPT, CFG_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
/* Wait for lock */
while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
#else
main_clock = CFG_OSC0_HZ;
#endif
/* Set up clocks for the CPU and all peripheral buses */
if (CFG_CLKDIV_CPU) {
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
} else {
ckd_state[CLOCK_CPU].freq = main_clock;
}
if (CFG_CLKDIV_HSB) {
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
} else {
ckd_state[CLOCK_HSB].freq = main_clock;
}
if (CFG_CLKDIV_PBA) {
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
} else {
ckd_state[CLOCK_PBA].freq = main_clock;
}
if (CFG_CLKDIV_PBB) {
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
} else {
ckd_state[CLOCK_PBB].freq = main_clock;
}
sm_writel(gd->sm, PM_CKSEL, cksel);
/* CFG_HZ currently depends on cpu_hz */
gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
#ifdef CONFIG_PLL
/* Use PLL0 as main clock */
sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
#endif
}
#endif /* CFG_POWER_MANAGER */

8
cpu/at32ap/sm.h
View File

@ -196,9 +196,9 @@
| SM_BF(name,value))
/* Register access macros */
#define sm_readl(port,reg) \
readl((port)->regs + SM_##reg)
#define sm_writel(port,reg,value) \
writel((value), (port)->regs + SM_##reg)
#define sm_readl(reg) \
readl((void *)SM_BASE + SM_##reg)
#define sm_writel(reg,value) \
writel((value), (void *)SM_BASE + SM_##reg)
#endif /* __CPU_AT32AP_SM_H__ */

113
cpu/at32ap/start.S
View File

@ -70,32 +70,12 @@ _start:
2: lddpc sp, sp_init
/*
* Relocate the data section and initialize .bss. Everything
* is guaranteed to be at least doubleword aligned by the
* linker script.
*/
lddpc r12, .Ldata_vma
lddpc r11, .Ldata_lma
lddpc r10, .Ldata_end
sub r10, r12
4: ld.d r8, r11++
sub r10, 8
st.d r12++, r8
brne 4b
mov r8, 0
mov r9, 0
lddpc r10, .Lbss_end
sub r10, r12
4: sub r10, 8
st.d r12++, r8
brne 4b
/* Initialize the GOT pointer */
lddpc r6, got_init
3: rsub r6, pc
ld.w pc, r6[start_u_boot@got]
/* Let's go */
rjmp board_init_f
.align 2
.type sp_init,@object
@ -103,11 +83,82 @@ sp_init:
.long CFG_INIT_SP_ADDR
got_init:
.long 3b - _GLOBAL_OFFSET_TABLE_
.Ldata_lma:
.long __data_lma
.Ldata_vma:
.long _data
.Ldata_end:
.long _edata
.Lbss_end:
.long _end
/*
* void relocate_code(new_sp, new_gd, monitor_addr)
*
* Relocate the u-boot image into RAM and continue from there.
* Does not return.
*/
.global relocate_code
.type relocate_code,@function
relocate_code:
mov sp, r12 /* use new stack */
mov r12, r11 /* save new_gd */
mov r11, r10 /* save destination address */
/* copy .text section and flush the cache along the way */
lda.w r8, _text
lda.w r9, _etext
sub lr, r10, r8 /* relocation offset */
1: ldm r8++, r0-r3
stm r10, r0-r3
sub r10, -16
ldm r8++, r0-r3
stm r10, r0-r3
sub r10, -16
cp.w r8, r9
cache r10[-4], 0x0d /* dcache clean/invalidate */
cache r10[-4], 0x01 /* icache invalidate */
brlt 1b
/* flush write buffer */
sync 0
/* copy data sections */
lda.w r9, _edata
1: ld.d r0, r8++
st.d r10++, r0
cp.w r8, r9
brlt 1b
/* zero out .bss */
mov r0, 0
mov r1, 0
lda.w r9, _end
sub r9, r8
1: st.d r10++, r0
sub r9, 8
brgt 1b
/* jump to RAM */
sub r0, pc, . - in_ram
add pc, r0, lr
.align 2
in_ram:
/* find the new GOT and relocate it */
lddpc r6, got_init_reloc
3: rsub r6, pc
mov r8, r6
lda.w r9, _egot
lda.w r10, _got
sub r9, r10
1: ld.w r0, r8[0]
add r0, lr
st.w r8++, r0
sub r9, 4
brgt 1b
/* Move the exception handlers */
mfsr r2, SYSREG_EVBA
add r2, lr
mtsr SYSREG_EVBA, r2
/* Do the rest of the initialization sequence */
call board_init_r
.align 2
got_init_reloc:
.long 3b - _GLOBAL_OFFSET_TABLE_

6
cpu/bf533/Makefile
View File

@ -1,6 +1,6 @@
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
# Copyright (c) 2005-2007 Analog Devices Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -20,8 +20,8 @@
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk

6
cpu/bf533/bf533_serial.h
View File

@ -1,7 +1,7 @@
/*
* U-boot - bf533_serial.h Serial Driver defines
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
@ -38,8 +38,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _Bf533_SERIAL_H

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