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spi: ti_qspi: Drop non DM code

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Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[jagan: update MIGRATION.txt, rebase config_whitelist.txt]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Vignesh Raghavendra 2019-04-16 21:31:59 +05:30 committed by Jagan Teki
parent 216800acf1
commit 61ae9782ef
9 changed files with 48 additions and 225 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
doc/driver-model/MIGRATION.txt
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@ -77,7 +77,6 @@ Partially converted:
drivers/spi/kirkwood_spi.c drivers/spi/kirkwood_spi.c
drivers/spi/mxc_spi.c drivers/spi/mxc_spi.c
drivers/spi/omap3_spi.c drivers/spi/omap3_spi.c
drivers/spi/ti_qspi.c
Status: In progress Status: In progress
Deadline: 2019.07 Deadline: 2019.07

13
drivers/spi/Kconfig
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@ -259,6 +259,13 @@ config TEGRA210_QSPI
be used to access SPI chips on platforms embedding this be used to access SPI chips on platforms embedding this
NVIDIA Tegra210 IP core. NVIDIA Tegra210 IP core.
config TI_QSPI
bool "TI QSPI driver"
imply TI_EDMA3
help
Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
This driver support spi flash single, quad and memory reads.
config XILINX_SPI config XILINX_SPI
bool "Xilinx SPI driver" bool "Xilinx SPI driver"
help help
@ -346,12 +353,6 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs. used on Renesas SoCs.
config TI_QSPI
bool "TI QSPI driver"
help
Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
This driver support spi flash single, quad and memory reads.
config KIRKWOOD_SPI config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver" bool "Marvell Kirkwood SPI Driver"
help help

2
drivers/spi/Makefile
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@ -9,6 +9,7 @@ obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
else else
obj-y += spi.o obj-y += spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
@ -56,7 +57,6 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o

235
drivers/spi/ti_qspi.c
View File

@ -52,9 +52,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define MM_SWITCH 0x01 #define MM_SWITCH 0x01
#define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff8ff #define MEM_CS_UNSELECT 0xfffff8ff
#define MMAP_START_ADDR_DRA 0x5c000000
#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0) #define QSPI_CMD_READ (0x3 << 0)
#define QSPI_CMD_READ_DUAL (0x6b << 0) #define QSPI_CMD_READ_DUAL (0x6b << 0)
@ -98,13 +95,9 @@ struct ti_qspi_regs {
/* ti qspi priv */ /* ti qspi priv */
struct ti_qspi_priv { struct ti_qspi_priv {
#ifndef CONFIG_DM_SPI
struct spi_slave slave;
#else
void *memory_map; void *memory_map;
uint max_hz; uint max_hz;
u32 num_cs; u32 num_cs;
#endif
struct ti_qspi_regs *base; struct ti_qspi_regs *base;
void *ctrl_mod_mmap; void *ctrl_mod_mmap;
ulong fclk; ulong fclk;
@ -113,8 +106,9 @@ struct ti_qspi_priv {
u32 dc; u32 dc;
}; };
static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{ {
struct ti_qspi_priv *priv = dev_get_priv(bus);
uint clk_div; uint clk_div;
if (!hz) if (!hz)
@ -133,6 +127,8 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
&priv->base->clk_ctrl); &priv->base->clk_ctrl);
/* enable SCLK and program the clk divider */ /* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
return 0;
} }
static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
@ -142,38 +138,6 @@ static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
readl(&priv->base->cmd); readl(&priv->base->cmd);
} }
static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
priv->dc = 0;
if (mode & SPI_CPHA)
priv->dc |= QSPI_CKPHA(0);
if (mode & SPI_CPOL)
priv->dc |= QSPI_CKPOL(0);
if (mode & SPI_CS_HIGH)
priv->dc |= QSPI_CSPOL(0);
return 0;
}
static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
writel(priv->dc, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
priv->dc <<= cs * 8;
writel(priv->dc, &priv->base->dc);
return 0;
}
static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
writel(0, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
}
static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{ {
u32 val; u32 val;
@ -186,15 +150,26 @@ static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
writel(val, ctrl_mod_mmap); writel(val, ctrl_mod_mmap);
} }
static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags, const void *dout, void *din, unsigned long flags)
u32 cs)
{ {
struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
uint words = bitlen >> 3; /* fixed 8-bit word length */ uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout; const uchar *txp = dout;
uchar *rxp = din; uchar *rxp = din;
uint status; uint status;
int timeout; int timeout;
unsigned int cs = slave->cs;
bus = dev->parent;
priv = dev_get_priv(bus);
if (cs > priv->num_cs) {
debug("invalid qspi chip select\n");
return -EINVAL;
}
/* Setup mmap flags */ /* Setup mmap flags */
if (flags & SPI_XFER_MMAP) { if (flags & SPI_XFER_MMAP) {
@ -316,126 +291,6 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
} }
#endif #endif
#ifndef CONFIG_DM_SPI
static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
{
return container_of(slave, struct ti_qspi_priv, slave);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* CS handled in xfer */
return;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
ti_qspi_cs_deactivate(priv);
}
void spi_init(void)
{
/* nothing to do */
}
static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
{
u32 memval = 0;
#ifdef CONFIG_QSPI_QUAD_SUPPORT
struct spi_slave *slave = &priv->slave;
memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_8_BITS |
QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS);
slave->mode |= SPI_RX_QUAD;
#else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS;
#endif
writel(memval, &priv->base->setup0);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct ti_qspi_priv *priv;
#ifdef CONFIG_AM43XX
gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
#endif
priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
if (!priv) {
printf("SPI_error: Fail to allocate ti_qspi_priv\n");
return NULL;
}
priv->base = (struct ti_qspi_regs *)QSPI_BASE;
priv->mode = mode;
#if defined(CONFIG_DRA7XX)
priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
priv->fclk = QSPI_DRA7XX_FCLK;
#else
priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
priv->fclk = QSPI_FCLK;
#endif
ti_spi_set_speed(priv, max_hz);
#ifdef CONFIG_TI_SPI_MMAP
ti_spi_setup_spi_register(priv);
#endif
return &priv->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
free(priv);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
__ti_qspi_set_mode(priv, priv->mode);
return __ti_qspi_claim_bus(priv, priv->slave.cs);
}
void spi_release_bus(struct spi_slave *slave)
{
struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
__ti_qspi_release_bus(priv);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
priv->slave.bus, priv->slave.cs, bitlen, flags);
return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
}
#else /* CONFIG_DM_SPI */
static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
struct spi_slave *slave, struct spi_slave *slave,
bool enable) bool enable)
@ -472,20 +327,19 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
writel(memval, &priv->base->setup0); writel(memval, &priv->base->setup0);
} }
static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
ti_spi_set_speed(priv, max_hz);
return 0;
}
static int ti_qspi_set_mode(struct udevice *bus, uint mode) static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{ {
struct ti_qspi_priv *priv = dev_get_priv(bus); struct ti_qspi_priv *priv = dev_get_priv(bus);
return __ti_qspi_set_mode(priv, mode);
priv->dc = 0;
if (mode & SPI_CPHA)
priv->dc |= QSPI_CKPHA(0);
if (mode & SPI_CPOL)
priv->dc |= QSPI_CKPOL(0);
if (mode & SPI_CS_HIGH)
priv->dc |= QSPI_CSPOL(0);
return 0;
} }
static int ti_qspi_claim_bus(struct udevice *dev) static int ti_qspi_claim_bus(struct udevice *dev)
@ -505,7 +359,14 @@ static int ti_qspi_claim_bus(struct udevice *dev)
__ti_qspi_setup_memorymap(priv, slave, true); __ti_qspi_setup_memorymap(priv, slave, true);
return __ti_qspi_claim_bus(priv, slave_plat->cs); writel(priv->dc, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
priv->dc <<= slave_plat->cs * 8;
writel(priv->dc, &priv->base->dc);
return 0;
} }
static int ti_qspi_release_bus(struct udevice *dev) static int ti_qspi_release_bus(struct udevice *dev)
@ -518,29 +379,14 @@ static int ti_qspi_release_bus(struct udevice *dev)
priv = dev_get_priv(bus); priv = dev_get_priv(bus);
__ti_qspi_setup_memorymap(priv, slave, false); __ti_qspi_setup_memorymap(priv, slave, false);
__ti_qspi_release_bus(priv);
writel(0, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
return 0; return 0;
} }
static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
bus = dev->parent;
priv = dev_get_priv(bus);
if (slave->cs > priv->num_cs) {
debug("invalid qspi chip select\n");
return -EINVAL;
}
return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
}
static int ti_qspi_probe(struct udevice *bus) static int ti_qspi_probe(struct udevice *bus)
{ {
struct ti_qspi_priv *priv = dev_get_priv(bus); struct ti_qspi_priv *priv = dev_get_priv(bus);
@ -648,4 +494,3 @@ U_BOOT_DRIVER(ti_qspi) = {
.probe = ti_qspi_probe, .probe = ti_qspi_probe,
.child_pre_probe = ti_qspi_child_pre_probe, .child_pre_probe = ti_qspi_child_pre_probe,
}; };
#endif /* CONFIG_DM_SPI */

6
include/configs/am43xx_evm.h
View File

@ -120,12 +120,6 @@
#define CONFIG_ENV_OFFSET_REDUND 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x120000
#endif #endif
/* SPI */
#define CONFIG_TI_SPI_MMAP
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_QSPI_QUAD_SUPPORT
#define CONFIG_TI_EDMA3
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h> #include <environment/ti/dfu.h>
#include <environment/ti/mmc.h> #include <environment/ti/mmc.h>

5
include/configs/am57xx_evm.h
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@ -92,11 +92,6 @@
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */ /* SPI SPL */
#define CONFIG_TI_EDMA3
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* SPI */
#define CONFIG_TI_SPI_MMAP
#define CONFIG_QSPI_QUAD_SUPPORT
#endif /* __CONFIG_AM57XX_EVM_H */ #endif /* __CONFIG_AM57XX_EVM_H */

3
include/configs/cm_t43.h
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@ -53,9 +53,6 @@
#define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_XHCI_OMAP
#define CONFIG_AM437X_USB2PHY2_HOST #define CONFIG_AM437X_USB2PHY2_HOST
/* SPI Flash support */
#define CONFIG_TI_SPI_MMAP
/* Power */ /* Power */
#define CONFIG_POWER #define CONFIG_POWER
#define CONFIG_POWER_I2C #define CONFIG_POWER_I2C

5
include/configs/dra7xx_evm.h
View File

@ -72,10 +72,6 @@
#define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_TI #define CONFIG_PHY_TI
/* SPI */
#define CONFIG_TI_SPI_MMAP
#define CONFIG_QSPI_QUAD_SUPPORT
/* /*
* Default to using SPI for environment, etc. * Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB) * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
@ -98,7 +94,6 @@
#endif #endif
/* SPI SPL */ /* SPI SPL */
#define CONFIG_TI_EDMA3
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SUPPORT_EMMC_BOOT

3
scripts/config_whitelist.txt
View File

@ -1555,8 +1555,6 @@ CONFIG_QE
CONFIG_QEMU_MIPS CONFIG_QEMU_MIPS
CONFIG_QIXIS_I2C_ACCESS CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI CONFIG_QSPI
CONFIG_QSPI_QUAD_SUPPORT
CONFIG_QSPI_SEL_GPIO
CONFIG_QUOTA CONFIG_QUOTA
CONFIG_R7780MP CONFIG_R7780MP
CONFIG_R8A66597_BASE_ADDR CONFIG_R8A66597_BASE_ADDR
@ -4400,7 +4398,6 @@ CONFIG_THUNDERX
CONFIG_TIMESTAMP CONFIG_TIMESTAMP
CONFIG_TIZEN CONFIG_TIZEN
CONFIG_TI_KSNAV CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER CONFIG_TMU_TIMER
CONFIG_TPL_PAD_TO CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPM_TIS_BASE_ADDRESS