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rockchip: clk: Add rk3368 SARADC clock support

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The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
David Wu
2017-09-20 14:37:50 +08:00
committed by Philipp Tomsich
parent b375d84135
commit 615514c16d
2 changed files with 37 additions and 0 deletions
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5
arch/arm/include/asm/arch-rockchip/cru_rk3368.h
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@@ -89,6 +89,11 @@ enum {
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
/* CLKSEL_CON25 */
CLK_SARADC_DIV_CON_SHIFT = 8,
CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
CLK_SARADC_DIV_CON_WIDTH = 8,
/* CLKSEL43_CON */
GMAC_MUX_SEL_EXTCLK = BIT(8),