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rockchip: pinctrl: rk3399: add gmac io strength support

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GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Kever Yang
2017-04-20 16:15:34 +08:00
committed by Simon Glass
parent fd9884e292
commit 602778d3c7
2 changed files with 89 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/pinctrl/rockchip/pinctrl_rk3399.c
View File

@@ -244,6 +244,24 @@ static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
rk_clrsetreg(&grf->gpio3c_iomux,
GRF_GPIO3C1_SEL_MASK,
GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
/* Set drive strength for GMAC tx io, value 3 means 13mA */
rk_clrsetreg(&grf->gpio3_e[0],
GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
3 << GRF_GPIO3A0_E_SHIFT |
3 << GRF_GPIO3A1_E_SHIFT |
3 << GRF_GPIO3A4_E_SHIFT |
1 << GRF_GPIO3A5_E0_SHIFT);
rk_clrsetreg(&grf->gpio3_e[1],
GRF_GPIO3A5_E12_MASK,
1 << GRF_GPIO3A5_E12_SHIFT);
rk_clrsetreg(&grf->gpio3_e[2],
GRF_GPIO3B4_E_MASK,
3 << GRF_GPIO3B4_E_SHIFT);
rk_clrsetreg(&grf->gpio3_e[4],
GRF_GPIO3C1_E_MASK,
3 << GRF_GPIO3C1_E_SHIFT);
}
#endif