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ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-07-18 12:24:41 +02:00
parent 086511fc96
commit 60204d06ed
4 changed files with 23 additions and 52 deletions
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2
cpu/ppc4xx/interrupts.c
View File

@ -136,7 +136,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
set_evpr(0x00000000);
/*
*Call uic or xilinx_irq pic_enable
* Call uic or xilinx_irq pic_enable
*/
pic_enable();

41
cpu/ppc4xx/uic.c
View File

@ -59,27 +59,19 @@ DECLARE_GLOBAL_DATA_PTR;
void pic_enable(void)
{
#if (UIC_MAX > 1)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 2)
irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 3)
irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
#endif
}
/* Handler for UIC interrupt */
@ -147,21 +139,14 @@ void external_interrupt(struct pt_regs *regs)
void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicsr, UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1sr, UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2sr, UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3sr, UIC_MASK(vec));
#endif
}
/*
@ -172,38 +157,24 @@ void pic_irq_enable(unsigned int vec)
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
#endif
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
}
void pic_irq_disable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
#endif
}

10
drivers/serial/serial_xuartlite.c
View File

@ -56,8 +56,8 @@ void serial_putc(const char c)
{
if (c == '\n')
serial_putc('\r');
while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL);
out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
while (in_be32((void *)UARTLITE_STATUS) & SR_TX_FIFO_FULL);
out_be32((void *)UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
}
void serial_puts(const char * s)
@ -69,13 +69,13 @@ void serial_puts(const char * s)
int serial_getc(void)
{
while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
return in_be32(UARTLITE_RX_FIFO) & 0xff;
while (!(in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
return in_be32((void *)UARTLITE_RX_FIFO) & 0xff;
}
int serial_tstc(void)
{
return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
return (in_be32((void *)UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
}
#endif /* CONFIG_MICROBLZE */

22
include/asm-ppc/xilinx_irq.h
View File

@ -19,18 +19,18 @@
#ifndef XILINX_IRQ_H
#define XILINX_IRQ_H
#define intc XPAR_INTC_0_BASEADDR
#define ISR (intc+(0*4)) /* Interrupt Status Register */
#define IPR (intc+(1*4)) /* Interrupt Pending Register */
#define IER (intc+(2*4)) /* Interrupt Enable Register */
#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
#define IVR (intc+(6*4)) /* Interrupt Vector Register */
#define MER (intc+(7*4)) /* Master Enable Register */
#define intc XPAR_INTC_0_BASEADDR
#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
#define MER (intc + (7 * 4)) /* Master Enable Register */
#define IRQ_MASK(irq) (1<<(irq&0x1f))
#define IRQ_MASK(irq) (1 << (irq & 0x1f))
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#endif