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arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

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Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan 2018-05-18 22:05:25 +08:00 committed by Marek Vasut
parent 73175d04a9
commit 5fb033a336
1 changed files with 4 additions and 0 deletions
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4
arch/arm/mach-socfpga/misc.c
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@ -22,8 +22,10 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 = static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE; (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
#endif
struct bsel bsel_str[] = { struct bsel bsel_str[] = {
{ "rsvd", "Reserved", }, { "rsvd", "Reserved", },
@ -52,6 +54,7 @@ void enable_caches(void)
#endif #endif
} }
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void) void v7_outer_cache_enable(void)
{ {
/* Disable the L2 cache */ /* Disable the L2 cache */
@ -72,6 +75,7 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */ /* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
} }
#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)