arm64: zynqmp: Update tps53681 i2c address

TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address
is 7bit where c0h is 1100000 which is 0x60.

This will fix issues reported by make dtbs that 0xc0 is above 7bit regular
i2c address range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2022-06-15 11:56:55 +02:00 committed by Michal Simek
parent 0b0d433b6c
commit 5f5979f430
4 changed files with 8 additions and 8 deletions

View File

@ -260,9 +260,9 @@
reg = <0x45>;
shunt-resistor = <5000>;
};
tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
tps53681@60 { /* u53 - 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */
compatible = "ti,tps53681", "ti,tps53679";
reg = <0xc0>;
reg = <0x60>;
};
};
i2c@3 { /* fmc1 via JA2G */

View File

@ -247,9 +247,9 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
reg_vccint: tps53681@c0 { /* u69 */
reg_vccint: tps53681@60 { /* u69 - 0xc0 */
compatible = "ti,tps53681", "ti,tps53679";
reg = <0xc0>;
reg = <0x60>;
};
reg_vcc_pmc: tps544@7 { /* u80 */
compatible = "ti,tps544b25";

View File

@ -239,9 +239,9 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
reg_vccint: tps53681@c0 { /* u69 */
reg_vccint: tps53681@60 { /* u69 - 0xc0 */
compatible = "ti,tps53681", "ti,tps53679";
reg = <0xc0>;
reg = <0x60>;
};
reg_vcc_pmc: tps544@7 { /* u80 */
compatible = "ti,tps544b25";

View File

@ -239,9 +239,9 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
reg_vccint: tps53681@c0 { /* u69 */
reg_vccint: tps53681@60 { /* u69 - 0xc0 */
compatible = "ti,tps53681", "ti,tps53679";
reg = <0xc0>;
reg = <0x60>;
};
reg_vcc_pmc: tps544@7 { /* u80 */
compatible = "ti,tps544b25";