Merge tag 'for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for 2022.10 - new driver nuvoton, NPCM7xx from Jim Liu Fixes: - ast_i2c: Remove SCL direct drive mode from Eddie James - avoid dynamic stack use in dm_i2c_write bloat-o-meter drivers/i2c/i2c-uclass.o.{0,1} add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-144 (-144) Function old new delta dm_i2c_write 552 408 -144 Total: Before=3828, After=3684, chg -3.76% patch from Rasmus Villemoes
This commit is contained in:
commit
5eefa9344b
@ -447,6 +447,11 @@ config SYS_I2C_NEXELL
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have several I2C ports and all are provided, controlled by the
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device tree.
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config SYS_I2C_NPCM
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bool "Nuvoton NPCM I2C driver"
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help
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Support for Nuvoton I2C controller driver.
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config SYS_I2C_OCORES
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bool "ocores I2C driver"
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depends on DM_I2C
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@ -33,6 +33,7 @@ obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
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obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
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obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o
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obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
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obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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@ -77,7 +77,7 @@ static void ast_i2c_init_bus(struct udevice *dev)
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/* Enable Master Mode. Assuming single-master */
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writel(I2CD_MASTER_EN
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| I2CD_M_SDA_LOCK_EN
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| I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
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| I2CD_MULTI_MASTER_DIS,
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&priv->regs->fcr);
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/* Enable Interrupts */
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writel(I2CD_INTR_TX_ACK
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@ -168,6 +168,9 @@ int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
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struct udevice *bus = dev_get_parent(dev);
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struct dm_i2c_ops *ops = i2c_get_ops(bus);
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struct i2c_msg msg[1];
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uint8_t _buf[I2C_MAX_OFFSET_LEN + 64];
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uint8_t *buf = _buf;
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int ret;
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if (!ops->xfer)
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return -ENOSYS;
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@ -192,29 +195,20 @@ int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
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* need to allow space for the offset (up to 4 bytes) and the message
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* itself.
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*/
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if (len < 64) {
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uint8_t buf[I2C_MAX_OFFSET_LEN + len];
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i2c_setup_offset(chip, offset, buf, msg);
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msg->len += len;
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memcpy(buf + chip->offset_len, buffer, len);
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return ops->xfer(bus, msg, 1);
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} else {
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uint8_t *buf;
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int ret;
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if (len > sizeof(_buf) - I2C_MAX_OFFSET_LEN) {
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buf = malloc(I2C_MAX_OFFSET_LEN + len);
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if (!buf)
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return -ENOMEM;
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i2c_setup_offset(chip, offset, buf, msg);
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msg->len += len;
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memcpy(buf + chip->offset_len, buffer, len);
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ret = ops->xfer(bus, msg, 1);
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free(buf);
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return ret;
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}
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i2c_setup_offset(chip, offset, buf, msg);
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msg->len += len;
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memcpy(buf + chip->offset_len, buffer, len);
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ret = ops->xfer(bus, msg, 1);
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if (buf != _buf)
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free(buf);
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return ret;
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}
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int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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630
drivers/i2c/npcm-i2c.c
Normal file
630
drivers/i2c/npcm-i2c.c
Normal file
@ -0,0 +1,630 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <asm/arch/gcr.h>
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#define I2C_FREQ_100K 100000
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#define NPCM_I2C_TIMEOUT_MS 10
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#define NPCM7XX_I2CSEGCTL_INIT_VAL 0x0333F000
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#define NPCM8XX_I2CSEGCTL_INIT_VAL 0x9333F000
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/* SCLFRQ min/max field values */
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#define SCLFRQ_MIN 10
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#define SCLFRQ_MAX 511
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/* SMBCTL1 */
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#define SMBCTL1_START BIT(0)
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#define SMBCTL1_STOP BIT(1)
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#define SMBCTL1_INTEN BIT(2)
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#define SMBCTL1_ACK BIT(4)
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#define SMBCTL1_STASTRE BIT(7)
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/* SMBCTL2 */
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#define SMBCTL2_ENABLE BIT(0)
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/* SMBCTL3 */
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#define SMBCTL3_SCL_LVL BIT(7)
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#define SMBCTL3_SDA_LVL BIT(6)
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/* SMBCST */
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#define SMBCST_BB BIT(1)
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#define SMBCST_TGSCL BIT(5)
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/* SMBST */
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#define SMBST_XMIT BIT(0)
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#define SMBST_MASTER BIT(1)
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#define SMBST_STASTR BIT(3)
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#define SMBST_NEGACK BIT(4)
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#define SMBST_BER BIT(5)
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#define SMBST_SDAST BIT(6)
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/* SMBCST3 in bank0 */
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#define SMBCST3_EO_BUSY BIT(7)
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/* SMBFIF_CTS in bank1 */
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#define SMBFIF_CTS_CLR_FIFO BIT(6)
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#define SMBFIF_CTL_FIFO_EN BIT(4)
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#define SMBCTL3_BNK_SEL BIT(5)
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enum {
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I2C_ERR_NACK = 1,
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I2C_ERR_BER,
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I2C_ERR_TIMEOUT,
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};
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struct smb_bank0_regs {
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u8 addr3;
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u8 addr7;
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u8 addr4;
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u8 addr8;
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u16 addr5;
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u16 addr6;
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u8 cst2;
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u8 cst3;
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u8 ctl4;
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u8 ctl5;
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u8 scllt;
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u8 fif_ctl;
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u8 sclht;
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};
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struct smb_bank1_regs {
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u8 fif_cts;
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u8 fair_per;
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u16 txf_ctl;
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u32 t_out;
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u8 cst2;
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u8 cst3;
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u16 txf_sts;
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u16 rxf_sts;
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u8 rxf_ctl;
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};
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struct npcm_i2c_regs {
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u16 sda;
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u16 st;
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u16 cst;
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u16 ctl1;
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u16 addr;
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u16 ctl2;
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u16 addr2;
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u16 ctl3;
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union {
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struct smb_bank0_regs bank0;
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struct smb_bank1_regs bank1;
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};
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};
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struct npcm_i2c_bus {
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struct npcm_i2c_regs *reg;
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int num;
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u32 apb_clk;
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u32 freq;
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bool started;
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};
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static void npcm_dump_regs(struct npcm_i2c_bus *bus)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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printf("\n");
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printf("SMBST=0x%x\n", readb(®->st));
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printf("SMBCST=0x%x\n", readb(®->cst));
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printf("SMBCTL1=0x%x\n", readb(®->ctl1));
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printf("\n");
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}
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static int npcm_i2c_check_sda(struct npcm_i2c_bus *bus)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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ulong start_time;
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int err = I2C_ERR_TIMEOUT;
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u8 val;
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start_time = get_timer(0);
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/* wait SDAST to be 1 */
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while (get_timer(start_time) < NPCM_I2C_TIMEOUT_MS) {
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val = readb(®->st);
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if (val & SMBST_NEGACK) {
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err = I2C_ERR_NACK;
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break;
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}
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if (val & SMBST_BER) {
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err = I2C_ERR_BER;
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break;
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}
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if (val & SMBST_SDAST) {
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err = 0;
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break;
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}
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}
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if (err)
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printf("%s: err %d\n", __func__, err);
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return err;
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}
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static int npcm_i2c_send_start(struct npcm_i2c_bus *bus)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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ulong start_time;
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int err = I2C_ERR_TIMEOUT;
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/* Generate START condition */
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setbits_8(®->ctl1, SMBCTL1_START);
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start_time = get_timer(0);
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while (get_timer(start_time) < NPCM_I2C_TIMEOUT_MS) {
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if (readb(®->st) & SMBST_BER)
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return I2C_ERR_BER;
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if (readb(®->st) & SMBST_MASTER) {
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err = 0;
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break;
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}
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}
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bus->started = true;
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return err;
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}
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static int npcm_i2c_send_stop(struct npcm_i2c_bus *bus, bool wait)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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ulong start_time;
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int err = I2C_ERR_TIMEOUT;
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setbits_8(®->ctl1, SMBCTL1_STOP);
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/* Clear NEGACK, STASTR and BER bits */
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writeb(SMBST_STASTR | SMBST_NEGACK | SMBST_BER, ®->st);
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bus->started = false;
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if (!wait)
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return 0;
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start_time = get_timer(0);
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while (get_timer(start_time) < NPCM_I2C_TIMEOUT_MS) {
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if ((readb(®->ctl1) & SMBCTL1_STOP) == 0) {
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err = 0;
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break;
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}
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}
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if (err) {
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printf("%s: err %d\n", __func__, err);
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npcm_dump_regs(bus);
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}
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return err;
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}
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static void npcm_i2c_reset(struct npcm_i2c_bus *bus)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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debug("%s: module %d\n", __func__, bus->num);
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/* disable & enable SMB moudle */
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clrbits_8(®->ctl2, SMBCTL2_ENABLE);
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setbits_8(®->ctl2, SMBCTL2_ENABLE);
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/* clear BB and status */
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writeb(SMBCST_BB, ®->cst);
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writeb(0xff, ®->st);
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/* select bank 1 */
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setbits_8(®->ctl3, SMBCTL3_BNK_SEL);
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/* Clear all fifo bits */
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writeb(SMBFIF_CTS_CLR_FIFO, ®->bank1.fif_cts);
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/* select bank 0 */
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clrbits_8(®->ctl3, SMBCTL3_BNK_SEL);
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/* clear EOB bit */
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writeb(SMBCST3_EO_BUSY, ®->bank0.cst3);
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/* single byte mode */
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clrbits_8(®->bank0.fif_ctl, SMBFIF_CTL_FIFO_EN);
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/* set POLL mode */
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writeb(0, ®->ctl1);
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}
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static void npcm_i2c_recovery(struct npcm_i2c_bus *bus, u32 addr)
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{
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u8 val;
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int iter = 27;
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struct npcm_i2c_regs *reg = bus->reg;
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int err;
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val = readb(®->ctl3);
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/* Skip recovery, bus not stucked */
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if ((val & SMBCTL3_SCL_LVL) && (val & SMBCTL3_SDA_LVL))
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return;
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printf("Performing I2C bus %d recovery...\n", bus->num);
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/* SCL/SDA are not releaed, perform recovery */
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while (1) {
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/* toggle SCL line */
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writeb(SMBCST_TGSCL, ®->cst);
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udelay(20);
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val = readb(®->ctl3);
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if (val & SMBCTL3_SDA_LVL)
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break;
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if (iter-- == 0)
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break;
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}
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if (val & SMBCTL3_SDA_LVL) {
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writeb((u8)((addr << 1) & 0xff), ®->sda);
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err = npcm_i2c_send_start(bus);
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if (!err) {
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udelay(20);
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npcm_i2c_send_stop(bus, false);
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udelay(200);
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printf("I2C bus %d recovery completed\n",
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bus->num);
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} else {
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printf("%s: send START err %d\n", __func__, err);
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}
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} else {
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printf("Fail to recover I2C bus %d\n", bus->num);
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}
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npcm_i2c_reset(bus);
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}
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static int npcm_i2c_send_address(struct npcm_i2c_bus *bus, u8 addr,
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bool stall)
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{
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struct npcm_i2c_regs *reg = bus->reg;
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ulong start_time;
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u8 val;
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/* Stall After Start Enable */
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if (stall)
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setbits_8(®->ctl1, SMBCTL1_STASTRE);
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writeb(addr, ®->sda);
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if (stall) {
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start_time = get_timer(0);
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while (get_timer(start_time) < NPCM_I2C_TIMEOUT_MS) {
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if (readb(®->st) & SMBST_STASTR)
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break;
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if (readb(®->st) & SMBST_BER) {
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clrbits_8(®->ctl1, SMBCTL1_STASTRE);
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||||
return I2C_ERR_BER;
|
||||
}
|
||||
}
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||||
}
|
||||
|
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/* check ACK */
|
||||
val = readb(®->st);
|
||||
if (val & SMBST_NEGACK) {
|
||||
debug("NACK on addr 0x%x\n", addr >> 1);
|
||||
/* After a Stop condition, writing 1 to NEGACK clears it */
|
||||
return I2C_ERR_NACK;
|
||||
}
|
||||
if (val & SMBST_BER)
|
||||
return I2C_ERR_BER;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int npcm_i2c_read_bytes(struct npcm_i2c_bus *bus, u8 *data, int len)
|
||||
{
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
u8 val;
|
||||
int i;
|
||||
int err = 0;
|
||||
|
||||
if (len == 1) {
|
||||
/* bus should be stalled before receiving last byte */
|
||||
setbits_8(®->ctl1, SMBCTL1_ACK);
|
||||
|
||||
/* clear STASTRE if it is set */
|
||||
if (readb(®->ctl1) & SMBCTL1_STASTRE) {
|
||||
writeb(SMBST_STASTR, ®->st);
|
||||
clrbits_8(®->ctl1, SMBCTL1_STASTRE);
|
||||
}
|
||||
npcm_i2c_check_sda(bus);
|
||||
npcm_i2c_send_stop(bus, false);
|
||||
*data = readb(®->sda);
|
||||
/* this must be done to generate STOP condition */
|
||||
writeb(SMBST_NEGACK, ®->st);
|
||||
} else {
|
||||
for (i = 0; i < len; i++) {
|
||||
/*
|
||||
* When NEGACK bit is set to 1 after the transmission of a byte,
|
||||
* SDAST is not set to 1.
|
||||
*/
|
||||
if (i != (len - 1)) {
|
||||
err = npcm_i2c_check_sda(bus);
|
||||
} else {
|
||||
err = readb_poll_timeout(®->ctl1, val,
|
||||
!(val & SMBCTL1_ACK), 100000);
|
||||
if (err) {
|
||||
printf("wait nack timeout\n");
|
||||
err = I2C_ERR_TIMEOUT;
|
||||
npcm_dump_regs(bus);
|
||||
}
|
||||
}
|
||||
if (err && err != I2C_ERR_TIMEOUT)
|
||||
break;
|
||||
if (i == (len - 2)) {
|
||||
/* set NACK before last byte */
|
||||
setbits_8(®->ctl1, SMBCTL1_ACK);
|
||||
}
|
||||
if (i == (len - 1)) {
|
||||
/* last byte, send STOP condition */
|
||||
npcm_i2c_send_stop(bus, false);
|
||||
*data = readb(®->sda);
|
||||
writeb(SMBST_NEGACK, ®->st);
|
||||
break;
|
||||
}
|
||||
*data = readb(®->sda);
|
||||
data++;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int npcm_i2c_send_bytes(struct npcm_i2c_bus *bus, u8 *data, int len)
|
||||
{
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
u8 val;
|
||||
int i;
|
||||
int err = 0;
|
||||
|
||||
val = readb(®->st);
|
||||
if (val & SMBST_NEGACK)
|
||||
return I2C_ERR_NACK;
|
||||
else if (val & SMBST_BER)
|
||||
return I2C_ERR_BER;
|
||||
|
||||
/* clear STASTRE if it is set */
|
||||
if (readb(®->ctl1) & SMBCTL1_STASTRE)
|
||||
clrbits_8(®->ctl1, SMBCTL1_STASTRE);
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
err = npcm_i2c_check_sda(bus);
|
||||
if (err)
|
||||
break;
|
||||
writeb(*data, ®->sda);
|
||||
data++;
|
||||
}
|
||||
npcm_i2c_check_sda(bus);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int npcm_i2c_read(struct npcm_i2c_bus *bus, u32 addr, u8 *data,
|
||||
u32 len)
|
||||
{
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
int err;
|
||||
bool stall;
|
||||
|
||||
if (len <= 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* send START condition */
|
||||
err = npcm_i2c_send_start(bus);
|
||||
if (err) {
|
||||
debug("%s: send START err %d\n", __func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
stall = (len == 1) ? true : false;
|
||||
/* send address byte */
|
||||
err = npcm_i2c_send_address(bus, (u8)(addr << 1) | 0x1, stall);
|
||||
|
||||
if (!err && len)
|
||||
npcm_i2c_read_bytes(bus, data, len);
|
||||
|
||||
if (err == I2C_ERR_NACK) {
|
||||
/* clear NACK */
|
||||
writeb(SMBST_NEGACK, ®->st);
|
||||
}
|
||||
|
||||
if (err)
|
||||
debug("%s: err %d\n", __func__, err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int npcm_i2c_write(struct npcm_i2c_bus *bus, u32 addr, u8 *data,
|
||||
u32 len)
|
||||
{
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
int err;
|
||||
bool stall;
|
||||
|
||||
/* send START condition */
|
||||
err = npcm_i2c_send_start(bus);
|
||||
if (err) {
|
||||
debug("%s: send START err %d\n", __func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
stall = (len == 0) ? true : false;
|
||||
/* send address byte */
|
||||
err = npcm_i2c_send_address(bus, (u8)(addr << 1), stall);
|
||||
|
||||
if (!err && len)
|
||||
err = npcm_i2c_send_bytes(bus, data, len);
|
||||
|
||||
/* clear STASTRE if it is set */
|
||||
if (stall)
|
||||
clrbits_8(®->ctl1, SMBCTL1_STASTRE);
|
||||
|
||||
if (err)
|
||||
debug("%s: err %d\n", __func__, err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int npcm_i2c_xfer(struct udevice *dev,
|
||||
struct i2c_msg *msg, int nmsgs)
|
||||
{
|
||||
struct npcm_i2c_bus *bus = dev_get_priv(dev);
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
int ret = 0, err = 0;
|
||||
|
||||
if (nmsgs < 1 || nmsgs > 2) {
|
||||
printf("%s: commands not support\n", __func__);
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
/* clear ST register */
|
||||
writeb(0xFF, ®->st);
|
||||
|
||||
for ( ; nmsgs > 0; nmsgs--, msg++) {
|
||||
if (msg->flags & I2C_M_RD)
|
||||
err = npcm_i2c_read(bus, msg->addr, msg->buf,
|
||||
msg->len);
|
||||
else
|
||||
err = npcm_i2c_write(bus, msg->addr, msg->buf,
|
||||
msg->len);
|
||||
if (err) {
|
||||
debug("i2c_xfer: error %d\n", err);
|
||||
ret = -EREMOTEIO;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (bus->started)
|
||||
npcm_i2c_send_stop(bus, true);
|
||||
|
||||
if (err)
|
||||
npcm_i2c_recovery(bus, msg->addr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int npcm_i2c_init_clk(struct npcm_i2c_bus *bus, u32 bus_freq)
|
||||
{
|
||||
struct npcm_i2c_regs *reg = bus->reg;
|
||||
u32 freq = bus->apb_clk;
|
||||
u32 sclfrq;
|
||||
u8 hldt, val;
|
||||
|
||||
if (bus_freq > I2C_FREQ_100K) {
|
||||
printf("Support standard mode only\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* SCLFRQ = T(SCL)/4/T(CLK) = FREQ(CLK)/4/FREQ(SCL) */
|
||||
sclfrq = freq / (bus_freq * 4);
|
||||
if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (freq >= 40000000)
|
||||
hldt = 17;
|
||||
else if (freq >= 12500000)
|
||||
hldt = 15;
|
||||
else
|
||||
hldt = 7;
|
||||
|
||||
val = readb(®->ctl2) & 0x1;
|
||||
val |= (sclfrq & 0x7F) << 1;
|
||||
writeb(val, ®->ctl2);
|
||||
|
||||
/* clear 400K_MODE bit */
|
||||
val = readb(®->ctl3) & 0xc;
|
||||
val |= (sclfrq >> 7) & 0x3;
|
||||
writeb(val, ®->ctl3);
|
||||
|
||||
writeb(hldt, ®->bank0.ctl4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int npcm_i2c_set_bus_speed(struct udevice *dev,
|
||||
unsigned int speed)
|
||||
{
|
||||
struct npcm_i2c_bus *bus = dev_get_priv(dev);
|
||||
|
||||
return npcm_i2c_init_clk(bus, speed);
|
||||
}
|
||||
|
||||
static int npcm_i2c_probe(struct udevice *dev)
|
||||
{
|
||||
struct npcm_i2c_bus *bus = dev_get_priv(dev);
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
struct npcm_i2c_regs *reg;
|
||||
u32 i2csegctl_val = dev_get_driver_data(dev);
|
||||
struct clk clk;
|
||||
int ret;
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &clk);
|
||||
if (ret) {
|
||||
printf("%s: ret %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
bus->apb_clk = clk_get_rate(&clk);
|
||||
if (bus->apb_clk <= 0) {
|
||||
printf("%s: fail to get rate\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
clk_free(&clk);
|
||||
|
||||
bus->num = dev->seq_;
|
||||
bus->reg = dev_read_addr_ptr(dev);
|
||||
bus->freq = dev_read_u32_default(dev, "clock-frequency", 100000);
|
||||
bus->started = false;
|
||||
reg = bus->reg;
|
||||
|
||||
if (npcm_i2c_init_clk(bus, bus->freq)) {
|
||||
printf("%s: init_clk failed\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* set initial i2csegctl value */
|
||||
writel(i2csegctl_val, &gcr->i2csegctl);
|
||||
|
||||
/* enable SMB module */
|
||||
setbits_8(®->ctl2, SMBCTL2_ENABLE);
|
||||
|
||||
/* select register bank 0 */
|
||||
clrbits_8(®->ctl3, SMBCTL3_BNK_SEL);
|
||||
|
||||
/* single byte mode */
|
||||
clrbits_8(®->bank0.fif_ctl, SMBFIF_CTL_FIFO_EN);
|
||||
|
||||
/* set POLL mode */
|
||||
writeb(0, ®->ctl1);
|
||||
|
||||
printf("I2C bus %d ready. speed=%d, base=0x%x, apb=%u\n",
|
||||
bus->num, bus->freq, (u32)(uintptr_t)bus->reg, bus->apb_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_i2c_ops nuvoton_i2c_ops = {
|
||||
.xfer = npcm_i2c_xfer,
|
||||
.set_bus_speed = npcm_i2c_set_bus_speed,
|
||||
};
|
||||
|
||||
static const struct udevice_id nuvoton_i2c_of_match[] = {
|
||||
{ .compatible = "nuvoton,npcm845-i2c", .data = NPCM8XX_I2CSEGCTL_INIT_VAL},
|
||||
{ .compatible = "nuvoton,npcm750-i2c", .data = NPCM7XX_I2CSEGCTL_INIT_VAL},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(npcm_i2c_bus) = {
|
||||
.name = "npcm-i2c",
|
||||
.id = UCLASS_I2C,
|
||||
.of_match = nuvoton_i2c_of_match,
|
||||
.probe = npcm_i2c_probe,
|
||||
.priv_auto = sizeof(struct npcm_i2c_bus),
|
||||
.ops = &nuvoton_i2c_ops,
|
||||
};
|
Loading…
Reference in New Issue
Block a user