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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD
2014-06-08 09:14:19 +02:00
parent e6607cffef 83bad1026b
commit 5ed28948a3
51 changed files with 623 additions and 154 deletions
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20
arch/arm/cpu/armv7/am33xx/board.c
View File

@@ -143,6 +143,19 @@ int arch_misc_init(void)
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* In the case of non-SPL based booting we'll want to call these
* functions a tiny bit later as it will require gd to be set and cleared
* and that's not true in s_init in this case so we cannot do it there.
*/
int board_early_init_f(void)
{
prcm_init();
set_mux_conf_regs();
return 0;
}
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
@@ -224,7 +237,7 @@ void s_init(void)
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
#ifdef CONFIG_NOR_BOOT
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
@@ -232,13 +245,14 @@ void s_init(void)
gd = &gdata;
preloader_console_init();
#endif
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
#ifdef CONFIG_SPL_BUILD
board_early_init_f();
sdram_init();
#endif
}
#endif

11
arch/arm/cpu/armv7/am33xx/clock.c
View File

@@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
};
}
/*
* Before scaling up the clocks we need to have the PMIC scale up the
* voltages first. This will be dependent on which PMIC is in use
* and in some cases we may not be scaling things up at all and thus not
* need to do anything here.
*/
__weak void scale_vcores(void)
{
}
void prcm_init()
{
enable_basic_clocks();
scale_vcores();
setup_dplls();
}

9
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View File

@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
void setup_clocks_for_console(void)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(&cmwkup->wkup_uart0ctrl);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
}
}
void enable_basic_clocks(void)

4
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
sdram_init();
#endif
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,

9
arch/arm/cpu/armv7/keystone/init.c
View File

@@ -8,6 +8,7 @@
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
@@ -30,6 +31,14 @@ int arch_cpu_init(void)
share_all_segments(11); /* PCIE */
#endif
/*
* just initialise the COM2 port so that TI specific
* UART register PWREMU_MGMT is initialized. Linux UART
* driver doesn't handle this.
*/
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
return 0;
}

12
arch/arm/cpu/armv7/omap3/mem.c
View File

@@ -21,17 +21,6 @@
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
SMNAND_GPMC_CONFIG1,
SMNAND_GPMC_CONFIG2,
SMNAND_GPMC_CONFIG3,
SMNAND_GPMC_CONFIG4,
SMNAND_GPMC_CONFIG5,
SMNAND_GPMC_CONFIG6,
0,
};
#else
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)

1
arch/arm/include/asm/arch-am33xx/clock.h
View File

@@ -107,6 +107,7 @@ const struct dpll_params *get_dpll_mpu_params(void);
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
void scale_vcores(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);

33
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@@ -26,7 +26,17 @@
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
#define TCLR_CE BIT(6) /* compare mode enable */
#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
#define TCLR_TCM BIT(8) /* edge detection of input pin*/
#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
#define TCLR_CAPTMODE BIT(13) /* capture mode */
#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
#define TCFG_RESET BIT(0) /* software reset */
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
/* device type */
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
@@ -87,7 +97,8 @@ struct cm_wkuppll {
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int resv2[4];
unsigned int timer0clkctrl; /* offset 0x10 */
unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
unsigned int resv3[2];
unsigned int clkseldpllmpu; /* offset 0x2c */
@@ -121,7 +132,9 @@ struct cm_wkuppll {
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
unsigned int wkup_adctscctrl; /* offset 0xBC */
unsigned int resv12[6];
unsigned int resv12;
unsigned int timer1clkctrl; /* offset 0xC4 */
unsigned int resv13[4];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
@@ -178,7 +191,9 @@ struct cm_perpll {
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv8[4];
unsigned int resv8[2];
unsigned int timer5clkctrl; /* offset 0xEC */
unsigned int timer6clkctrl; /* offset 0xF0 */
unsigned int mmc1clkctrl; /* offset 0xF4 */
unsigned int mmc2clkctrl; /* offset 0xF8 */
unsigned int resv9[8];
@@ -191,9 +206,17 @@ struct cm_perpll {
/* Encapsulating Display pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int resv1;
unsigned int clktimer7clk; /* offset 0x04 */
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clktimer3clk; /* offset 0x0C */
unsigned int clktimer4clk; /* offset 0x10 */
unsigned int resv2;
unsigned int clktimer5clk; /* offset 0x18 */
unsigned int clktimer6clk; /* offset 0x1C */
unsigned int resv3[2];
unsigned int clktimer1clk; /* offset 0x28 */
unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
#else

2
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
View File

@@ -115,8 +115,6 @@
#define K2HK_LPSC_ARM_SREFLEX 51
#define K2HK_LPSC_TETRIS 52
#define K2HK_UART0_BASE 0x02530c00
/* DDR3A definitions */
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000

3
arch/arm/include/asm/arch-keystone/hardware.h
View File

@@ -142,6 +142,9 @@ struct ddr3_emif_config {
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif

8
arch/arm/include/asm/arch-omap3/mem.h
View File

@@ -354,14 +354,6 @@ enum {
#define GPMC_CS_ENABLE 0x1
#define SMNAND_GPMC_CONFIG1 0x00000800
#define SMNAND_GPMC_CONFIG2 0x00141400
#define SMNAND_GPMC_CONFIG3 0x00141400
#define SMNAND_GPMC_CONFIG4 0x0F010F01
#define SMNAND_GPMC_CONFIG5 0x010C1414
#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
#define SMNAND_GPMC_CONFIG7 0x00000C44
#define M_NAND_GPMC_CONFIG1 0x00001800
#define M_NAND_GPMC_CONFIG2 0x00141400
#define M_NAND_GPMC_CONFIG3 0x00141400