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rockchip: sdram_common: add common dram_init_banksize

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dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-07-22 20:02:02 +08:00
parent 54f17fa05d
commit 5eb9a78fcd
9 changed files with 66 additions and 82 deletions
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13
arch/arm/mach-rockchip/rk3128-board.c
View File

@ -41,19 +41,6 @@ int board_init(void)
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0xe00000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{

3
arch/arm/mach-rockchip/rk3128/rk3128.c
View File

@ -2,6 +2,9 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_cpu_init(void)
{

13
arch/arm/mach-rockchip/rk322x-board.c
View File

@ -45,19 +45,6 @@ int board_init(void)
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 0x200000 for OPTEE */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x200000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{

15
arch/arm/mach-rockchip/rk3288/rk3288.c
View File

@ -67,18 +67,3 @@ void board_debug_uart_init(void)
GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
#define PMU_BASE 0xff730000
int dram_init_banksize(void)
{
struct rk3288_pmu *const pmu = (void *)PMU_BASE;
size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = size;
return 0;
}
#endif

11
arch/arm/mach-rockchip/rk3328/rk3328.c
View File

@ -44,17 +44,6 @@ static struct mm_region rk3328_mem_map[] = {
struct mm_region *mem_map = rk3328_mem_map;
int dram_init_banksize(void)
{
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
return 0;
}
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */

11
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@ -58,17 +58,6 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
};
int dram_init_banksize(void)
{
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
return 0;
}
#ifdef CONFIG_ARCH_EARLY_INIT_R
static int mcu_init(void)
{

11
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@ -78,17 +78,6 @@ void rockchip_stimer_init(void)
}
#endif
int dram_init_banksize(void)
{
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
return 0;
}
int arch_cpu_init(void)
{

63
arch/arm/mach-rockchip/sdram_common.c
View File

@ -11,6 +11,69 @@
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
struct tos_parameter_t {
u32 version;
u32 checksum;
struct {
char name[8];
s64 phy_addr;
u32 size;
u32 flags;
} tee_mem;
struct {
char name[8];
s64 phy_addr;
u32 size;
u32 flags;
} drm_mem;
s64 reserve[8];
};
int dram_init_banksize(void)
{
size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
gd->ram_top);
#ifdef CONFIG_ARM64
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#else
#ifdef CONFIG_SPL_OPTEE
struct tos_parameter_t *tos_parameter;
tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ top - gd->bd->bi_dram[1].start;
} else {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ top - gd->bd->bi_dram[1].start;
}
#else
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif
return 0;
}
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;

8
board/rockchip/evb_rv1108/evb_rv1108.c
View File

@ -59,11 +59,3 @@ int dram_init(void)
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0x60000000;
gd->bd->bi_dram[0].size = 0x8000000;
return 0;
}