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ARM: meson-g12a: Handle 4GiB DRAM size

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When configured with 4GiB DRAM size, only 3.8GiB is available, the
I/O beeing mapped in the last 256MiB of the first 4GiB physical memory/

First fixup the mm_region to handle the first 3.8GiB as memory and the
last 256MiB as I/O.

Then limit the real memory reported by the firmware to the available
physical space, 3.8GiB aligned with the mm_region memory zone size.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
This commit is contained in:
Neil Armstrong 2019-07-22 11:32:50 +02:00
parent 0d84acb00a
commit 5e5db096a3
1 changed files with 7 additions and 6 deletions

13
arch/arm/mach-meson/board-g12a.c
View File

@ -62,21 +62,21 @@ void meson_init_reserved_memory(void *fdt)
phys_size_t get_effective_memsize(void) phys_size_t get_effective_memsize(void)
{ {
/* Size is reported in MiB, convert it in bytes */ /* Size is reported in MiB, convert it in bytes */
return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M; >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
} }
static struct mm_region g12a_mem_map[] = { static struct mm_region g12a_mem_map[] = {
{ {
.virt = 0x0UL, .virt = 0x0UL,
.phys = 0x0UL, .phys = 0x0UL,
.size = 0x80000000UL, .size = 0xf5000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE PTE_BLOCK_INNER_SHARE
}, { }, {
.virt = 0xf0000000UL, .virt = 0xf5000000UL,
.phys = 0xf0000000UL, .phys = 0xf5000000UL,
.size = 0x10000000UL, .size = 0x0b000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -129,6 +129,7 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
G12A_ETH_REG_0_TX_RATIO(4) | G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN | G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN); G12A_ETH_REG_0_CLK_EN);
g12a_enable_external_mdio();
break; break;
case PHY_INTERFACE_MODE_RMII: case PHY_INTERFACE_MODE_RMII: