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powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init

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Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-24 23:36:17 -06:00
parent aa8d3fb8f4
commit 5cfbc458d4
3 changed files with 28 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
board/freescale/corenet_ds/ddr.c
View File

@ -31,19 +31,21 @@ extern fixed_ddr_parm_t fixed_ddr_parm_1[];
phys_size_t fixed_sdram(void)
{
int i;
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
unsigned int lawbar1_target_id;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
(sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
@ -53,7 +55,7 @@ phys_size_t fixed_sdram(void)
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;

24
board/freescale/corenet_ds/p4080ds_ddr.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -9,12 +9,6 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#define DATARATE_800MHZ 800000000
#define DATARATE_900MHZ 900000000
#define DATARATE_1000MHZ 1000000000
#define DATARATE_1200MHZ 1200000000
#define DATARATE_1300MHZ 1300000000
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
@ -340,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
{800, 900, &ddr_cfg_regs_800},
{900, 1000, &ddr_cfg_regs_900},
{1000, 1200, &ddr_cfg_regs_1000},
{1200, 1300, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
{800, 900, &ddr_cfg_regs_800_2nd},
{900, 1000, &ddr_cfg_regs_900_2nd},
{1000, 1200, &ddr_cfg_regs_1000_2nd},
{1200, 1300, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};

25
board/freescale/p1_p2_rdb/ddr.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009, 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -33,11 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
#define DATARATE_400MHZ 400000000
#define DATARATE_533MHZ 533333333
#define DATARATE_667MHZ 666666666
#define DATARATE_800MHZ 800000000
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
@ -204,27 +199,29 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
phys_size_t fixed_sdram (void)
{
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
strmhz(buf, ddr_freq));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
else if(ddr_freq_mhz <= 533)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
else if(ddr_freq_mhz <= 667)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
strmhz(buf, ddr_freq));
cpu = gd->cpu;
/* P1020 and it's derivatives support max 32bit DDR width */