mx53loco: Convert to driver model
Make the conversion to driver model as it is mandatory. Remove the SATA support for now as the i.MX53 support has not been added yet. Signed-off-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Fabio Estevam
committed by
Stefano Babic
Stefano Babic
parent
a48c22bc52
commit
5c8db4922d
@@ -18,10 +18,8 @@
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#include <env.h>
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#include <linux/errno.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <input.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/gpio.h>
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#include <power/pmic.h>
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@@ -62,127 +60,6 @@ static void setup_iomux_uart(void)
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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/* request VBUS power enable pin, GPIO7_8 */
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imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
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gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
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gpio_direction_input(IMX_GPIO_NR(3, 11));
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imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
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gpio_direction_input(IMX_GPIO_NR(3, 13));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
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return ret;
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(struct bd_info *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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MX53_PAD_EIM_DA13__GPIO3_13,
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
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SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
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MX53_PAD_EIM_DA11__GPIO3_11,
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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@@ -327,7 +204,6 @@ static void clock_1GHz(void)
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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setup_iomux_lcd();
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return 0;
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