Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
5c8d5b6fc1
@ -27,6 +27,7 @@
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#include <miiphy.h>
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#include <cpsw.h>
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#include <asm/errno.h>
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#include <linux/compiler.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/musb.h>
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@ -137,6 +138,16 @@ int arch_misc_init(void)
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}
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
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/*
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* This function is the place to do per-board things such as ramp up the
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* MPU clock frequency.
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*/
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__weak void am33xx_spl_board_init(void)
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{
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
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.cm_div_m2_dpll = CM_WKUP + 0xA0,
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};
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const struct dpll_params dpll_mpu = {
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struct dpll_params dpll_mpu_opp100 = {
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CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core = {
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const struct dpll_params dpll_core_opp100 = {
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1000, OSC-1, -1, -1, 10, 8, 4};
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const struct dpll_params dpll_mpu = {
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MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core = {
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50, OSC-1, -1, -1, 1, 1, 1};
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const struct dpll_params dpll_per = {
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960, OSC-1, 5, -1, -1, -1, -1};
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@ -17,6 +17,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <power/tps65910.h>
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struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
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@ -119,3 +120,59 @@ int print_cpuinfo(void)
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#ifdef CONFIG_AM33XX
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int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
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{
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int sil_rev;
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sil_rev = readl(&cdev->deviceid) >> 28;
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if (sil_rev == 1)
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/* PG 2.0, efuse may not be set. */
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return MPUPLL_M_800;
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else if (sil_rev >= 2) {
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/* Check what the efuse says our max speed is. */
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int efuse_arm_mpu_max_freq;
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efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
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switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
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case AM335X_ZCZ_1000:
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return MPUPLL_M_1000;
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case AM335X_ZCZ_800:
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return MPUPLL_M_800;
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case AM335X_ZCZ_720:
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return MPUPLL_M_720;
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case AM335X_ZCZ_600:
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case AM335X_ZCE_600:
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return MPUPLL_M_600;
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case AM335X_ZCZ_300:
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case AM335X_ZCE_300:
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return MPUPLL_M_300;
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}
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}
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/* PG 1.0 or otherwise unknown, use the PG1.0 max */
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return MPUPLL_M_720;
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}
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int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
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{
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/* For PG2.1 and later, we have one set of values. */
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if (sil_rev >= 2) {
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switch (frequency) {
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case MPUPLL_M_1000:
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return TPS65910_OP_REG_SEL_1_3_2_5;
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case MPUPLL_M_800:
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return TPS65910_OP_REG_SEL_1_2_6;
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case MPUPLL_M_720:
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return TPS65910_OP_REG_SEL_1_2_0;
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case MPUPLL_M_600:
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case MPUPLL_M_300:
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return TPS65910_OP_REG_SEL_1_1_3;
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}
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}
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/* Default to PG1.0/PG2.0 values. */
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return TPS65910_OP_REG_SEL_1_1_3;
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}
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#endif
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@ -76,6 +76,9 @@ void spl_board_init(void)
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#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
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arch_misc_init();
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#endif
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#ifdef CONFIG_AM33XX
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am33xx_spl_board_init();
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#endif
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}
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int board_mmc_init(bd_t *bis)
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@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
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val = optimize_vcore_voltage(&vcores->iva);
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do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
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/* Configure LDO SRAM "magic" bits */
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writel(2, (*prcm)->prm_sldo_core_setup);
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writel(2, (*prcm)->prm_sldo_mpu_setup);
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writel(2, (*prcm)->prm_sldo_mm_setup);
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}
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}
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static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
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@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
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.prm_vc_val_bypass = 0x4ae07ba0,
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.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
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.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
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.prm_sldo_core_setup = 0x4ae07bc4,
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.prm_sldo_core_ctrl = 0x4ae07bc8,
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.prm_sldo_mpu_setup = 0x4ae07bcc,
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.prm_sldo_mpu_ctrl = 0x4ae07bd0,
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.prm_sldo_mm_setup = 0x4ae07bd4,
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.prm_sldo_mm_ctrl = 0x4ae07bd8,
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/* SCRM stuff, used by some boards */
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.scrm_auxclk0 = 0x4ae0a310,
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@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
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.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
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.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
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.prm_sldo_core_setup = 0x4ae07cc4,
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.prm_sldo_core_ctrl = 0x4ae07cc8,
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.prm_sldo_mpu_setup = 0x4ae07ccc,
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.prm_sldo_mpu_ctrl = 0x4ae07cd0,
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.prm_sldo_mm_setup = 0x4ae07cd4,
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.prm_sldo_mm_ctrl = 0x4ae07cd8,
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.prm_abbldo_mpu_setup = 0x4ae07cdc,
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.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
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@ -11,9 +11,17 @@
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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/* MAIN PLL Fdll supported frequencies */
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#define MPUPLL_M_1000 1000
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#define MPUPLL_M_800 800
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#define MPUPLL_M_720 720
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#define MPUPLL_M_600 600
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#define MPUPLL_M_550 550
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#define MPUPLL_M_300 300
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/* MAIN PLL Fdll = 550 MHz, by default */
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#ifndef CONFIG_SYS_MPUCLK
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#define CONFIG_SYS_MPUCLK 550
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#define CONFIG_SYS_MPUCLK MPUPLL_M_550
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#endif
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#define UART_RESET (0x1 << 1)
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@ -21,5 +29,7 @@
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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extern void enable_dmm_clocks(void);
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extern const struct dpll_params dpll_core_opp100;
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extern struct dpll_params dpll_mpu_opp100;
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#endif /* endif _CLOCKS_AM33XX_H_ */
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@ -38,6 +38,16 @@
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#define AM335X 0xB944
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#define TI81XX 0xB81E
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#define DEVICE_ID (CTRL_BASE + 0x0600)
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#define DEVICE_ID_MASK 0x1FFF
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/* MPU max frequencies */
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#define AM335X_ZCZ_300 0x1FEF
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#define AM335X_ZCZ_600 0x1FAF
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#define AM335X_ZCZ_720 0x1F2F
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#define AM335X_ZCZ_800 0x1E2F
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#define AM335X_ZCZ_1000 0x1C2F
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#define AM335X_ZCE_300 0x1FDF
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#define AM335X_ZCE_600 0x1F9F
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/* This gives the status of the boot mode pins on the evm */
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#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
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@ -509,6 +519,8 @@ struct ctrl_dev {
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unsigned int macid1h; /* offset 0x3c */
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unsigned int resv4[4];
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unsigned int miisel; /* offset 0x50 */
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unsigned int resv5[106];
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unsigned int efuse_sma; /* offset 0x1FC */
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};
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/* gmii_sel register defines */
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@ -10,6 +10,7 @@
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/arch/cpu.h>
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#define BOARD_REV_ID 0x0
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@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
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#ifdef CONFIG_NOR_BOOT
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void enable_norboot_pin_mux(void);
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#endif
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void am33xx_spl_board_init(void);
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int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
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int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
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#endif
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@ -310,12 +310,6 @@ struct prcm_regs {
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u32 prm_vc_val_bypass;
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u32 prm_vc_cfg_i2c_mode;
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u32 prm_vc_cfg_i2c_clk;
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u32 prm_sldo_core_setup;
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u32 prm_sldo_core_ctrl;
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u32 prm_sldo_mpu_setup;
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u32 prm_sldo_mpu_ctrl;
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u32 prm_sldo_mm_setup;
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u32 prm_sldo_mm_ctrl;
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u32 prm_abbldo_mpu_setup;
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u32 prm_abbldo_mpu_ctrl;
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@ -26,6 +26,8 @@
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -244,6 +246,150 @@ const struct dpll_params dpll_ddr_evm_sk = {
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const struct dpll_params dpll_ddr_bone_black = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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struct am335x_baseboard_id header;
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int mpu_vdd;
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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if (board_is_bone(&header) || board_is_bone_lt(&header)) {
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/* BeagleBone PMIC Code */
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int usb_cur_lim;
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/*
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* Only perform PMIC configurations if board rev > A1
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* on Beaglebone White
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*/
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if (board_is_bone(&header) && !strncmp(header.version,
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"00A1", 4))
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return;
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if (i2c_probe(TPS65217_CHIP_PM))
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return;
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/*
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* On Beaglebone White we need to ensure we have AC power
|
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* before increasing the frequency.
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*/
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if (board_is_bone(&header)) {
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uchar pmic_status_reg;
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if (tps65217_reg_read(TPS65217_STATUS,
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&pmic_status_reg))
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return;
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if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
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puts("No AC power, disabling frequency switch\n");
|
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return;
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}
|
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}
|
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|
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/*
|
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* Override what we have detected since we know if we have
|
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* a Beaglebone Black it supports 1GHz.
|
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*/
|
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if (board_is_bone_lt(&header))
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dpll_mpu_opp100.m = MPUPLL_M_1000;
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|
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/*
|
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* Increase USB current limit to 1300mA or 1800mA and set
|
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* the MPU voltage controller as needed.
|
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*/
|
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if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
|
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
|
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
|
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} else {
|
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
|
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
|
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}
|
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|
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
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TPS65217_POWER_PATH,
|
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usb_cur_lim,
|
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TPS65217_USB_INPUT_CUR_LIMIT_MASK))
|
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puts("tps65217_reg_write failure\n");
|
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|
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/* Set DCDC3 (CORE) voltage to 1.125V */
|
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
|
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
|
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puts("tps65217_voltage_update failure\n");
|
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return;
|
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}
|
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|
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/* Set CORE Frequencies to OPP100 */
|
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
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|
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/* Set DCDC2 (MPU) voltage */
|
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if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
|
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puts("tps65217_voltage_update failure\n");
|
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return;
|
||||
}
|
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|
||||
/*
|
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* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
|
||||
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
|
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*/
|
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if (board_is_bone(&header)) {
|
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS1,
|
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TPS65217_LDO_VOLTAGE_OUT_3_3,
|
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TPS65217_LDO_MASK))
|
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puts("tps65217_reg_write failure\n");
|
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} else {
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
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TPS65217_DEFLS1,
|
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TPS65217_LDO_VOLTAGE_OUT_1_8,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
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}
|
||||
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS2,
|
||||
TPS65217_LDO_VOLTAGE_OUT_3_3,
|
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TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
} else {
|
||||
int sil_rev;
|
||||
|
||||
/*
|
||||
* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
|
||||
* MPU frequencies we support we use a CORE voltage of
|
||||
* 1.1375V. For MPU voltage we need to switch based on
|
||||
* the frequency we are running at.
|
||||
*/
|
||||
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Depending on MPU clock and PG we will need a different
|
||||
* VDD to drive at that speed.
|
||||
*/
|
||||
sil_rev = readl(&cdev->deviceid) >> 28;
|
||||
mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
|
||||
dpll_mpu_opp100.m);
|
||||
|
||||
/* Tell the TPS65910 to use i2c */
|
||||
tps65910_set_i2c_control();
|
||||
|
||||
/* First update MPU voltage. */
|
||||
if (tps65910_voltage_update(MPU, mpu_vdd))
|
||||
return;
|
||||
|
||||
/* Second, update the CORE voltage. */
|
||||
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
|
||||
return;
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
}
|
||||
|
||||
/* Set MPU Frequency to what we detected now that voltages are set */
|
||||
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
struct am335x_baseboard_id header;
|
||||
|
||||
@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
|
||||
static void cpsw_slave_update_link(struct cpsw_slave *slave,
|
||||
struct cpsw_priv *priv, int *link)
|
||||
{
|
||||
struct phy_device *phy = priv->phydev;
|
||||
struct phy_device *phy;
|
||||
u32 mac_control = 0;
|
||||
|
||||
phy = priv->phydev;
|
||||
|
||||
if (!phy)
|
||||
return;
|
||||
|
||||
phy_startup(phy);
|
||||
*link = phy->link;
|
||||
|
||||
@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
|
||||
dev,
|
||||
slave->data->phy_if);
|
||||
|
||||
if (!phydev)
|
||||
return -1;
|
||||
|
||||
phydev->supported &= supported;
|
||||
phydev->advertising = phydev->supported;
|
||||
|
||||
|
||||
@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
|
||||
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
|
||||
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
|
||||
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
|
||||
COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
|
||||
COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
|
||||
109
drivers/power/pmic/pmic_tps65217.c
Normal file
109
drivers/power/pmic/pmic_tps65217.c
Normal file
@ -0,0 +1,109 @@
|
||||
/*
|
||||
* (C) Copyright 2011-2013
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <power/tps65217.h>
|
||||
|
||||
/**
|
||||
* tps65217_reg_read() - Generic function that can read a TPS65217 register
|
||||
* @src_reg: Source register address
|
||||
* @src_val: Address of destination variable
|
||||
* @return: 0 for success, not 0 on failure.
|
||||
*/
|
||||
int tps65217_reg_read(uchar src_reg, uchar *src_val)
|
||||
{
|
||||
return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
|
||||
* register or bit field regardless of protection
|
||||
* level.
|
||||
*
|
||||
* @prot_level: Register password protection. Use
|
||||
* TPS65217_PROT_LEVEL_NONE,
|
||||
* TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
|
||||
* @dest_reg: Register address to write.
|
||||
* @dest_val: Value to write.
|
||||
* @mask: Bit mask (8 bits) to be applied. Function will only
|
||||
* change bits that are set in the bit mask.
|
||||
*
|
||||
* @return: 0 for success, not 0 on failure, as per the i2c API
|
||||
*/
|
||||
int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
|
||||
uchar mask)
|
||||
{
|
||||
uchar read_val;
|
||||
uchar xor_reg;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* If we are affecting only a bit field, read dest_reg and apply the
|
||||
* mask
|
||||
*/
|
||||
if (mask != TPS65217_MASK_ALL_BITS) {
|
||||
ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
read_val &= (~mask);
|
||||
read_val |= (dest_val & mask);
|
||||
dest_val = read_val;
|
||||
}
|
||||
|
||||
if (prot_level > 0) {
|
||||
xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
|
||||
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
|
||||
&xor_reg, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (prot_level == TPS65217_PROT_LEVEL_2) {
|
||||
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
|
||||
&xor_reg, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* tps65217_voltage_update() - Function to change a voltage level, as this
|
||||
* is a multi-step process.
|
||||
* @dc_cntrl_reg: DC voltage control register to change.
|
||||
* @volt_sel: New value for the voltage register
|
||||
* @return: 0 for success, not 0 on failure.
|
||||
*/
|
||||
int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
|
||||
{
|
||||
if ((dc_cntrl_reg != TPS65217_DEFDCDC1) &&
|
||||
(dc_cntrl_reg != TPS65217_DEFDCDC2) &&
|
||||
(dc_cntrl_reg != TPS65217_DEFDCDC3))
|
||||
return 1;
|
||||
|
||||
/* set voltage level */
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
|
||||
TPS65217_MASK_ALL_BITS))
|
||||
return 1;
|
||||
|
||||
/* set GO bit to initiate voltage transition */
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW,
|
||||
TPS65217_DCDC_GO, TPS65217_DCDC_GO))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
83
drivers/power/pmic/pmic_tps65910.c
Normal file
83
drivers/power/pmic/pmic_tps65910.c
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* (C) Copyright 2011-2013
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <power/tps65910.h>
|
||||
|
||||
/*
|
||||
* tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
|
||||
* interface.
|
||||
* @return: 0 on success, not 0 on failure
|
||||
*/
|
||||
int tps65910_set_i2c_control(void)
|
||||
{
|
||||
int ret;
|
||||
uchar buf;
|
||||
|
||||
/* VDD1/2 voltage selection register access by control i/f */
|
||||
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
|
||||
&buf, 1);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
|
||||
|
||||
return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
|
||||
&buf, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* tps65910_voltage_update() - Voltage switching for MPU frequency switching.
|
||||
* @module: mpu - 0, core - 1
|
||||
* @vddx_op_vol_sel: vdd voltage to set
|
||||
* @return: 0 on success, not 0 on failure
|
||||
*/
|
||||
int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
|
||||
{
|
||||
uchar buf;
|
||||
unsigned int reg_offset;
|
||||
int ret;
|
||||
|
||||
if (module == MPU)
|
||||
reg_offset = TPS65910_VDD1_OP_REG;
|
||||
else
|
||||
reg_offset = TPS65910_VDD2_OP_REG;
|
||||
|
||||
/* Select VDDx OP */
|
||||
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
buf &= ~TPS65910_OP_REG_CMD_MASK;
|
||||
|
||||
ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Configure VDDx OP Voltage */
|
||||
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
buf &= ~TPS65910_OP_REG_SEL_MASK;
|
||||
buf |= vddx_op_vol_sel;
|
||||
|
||||
ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -170,6 +170,7 @@
|
||||
"run mmcboot;" \
|
||||
"setenv mmcdev 1; " \
|
||||
"setenv bootpart 1:2; " \
|
||||
"setenv mmcroot /dev/mmcblk1p2 ro; " \
|
||||
"run mmcboot;" \
|
||||
"run nandboot;"
|
||||
|
||||
@ -189,8 +190,13 @@
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
|
||||
/* PMIC support */
|
||||
#define CONFIG_POWER_TPS65217
|
||||
#define CONFIG_POWER_TPS65910
|
||||
|
||||
/* SPL */
|
||||
#ifndef CONFIG_NOR_BOOT
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
|
||||
/* CPSW support */
|
||||
|
||||
@ -14,7 +14,13 @@
|
||||
|
||||
#define CONFIG_DRA7XX
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE /* For now. */
|
||||
/* MMC ENV related defines */
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
|
||||
#define CONFIG_ENV_OFFSET 0xE0000
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
|
||||
#define CONSOLEDEV "ttyO0"
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
@ -201,6 +201,7 @@
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
/*
|
||||
* Place the image at the start of the ROM defined image space.
|
||||
* We limit our size to the ROM-defined downloaded image area, and use the
|
||||
|
||||
83
include/power/tps65217.h
Normal file
83
include/power/tps65217.h
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* (C) Copyright 2011-2013
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* For more details, please see the TRM at http://www.ti.com/product/tps65217a
|
||||
*/
|
||||
|
||||
#ifndef __POWER_TPS65217_H__
|
||||
#define __POWER_TPS65217_H__
|
||||
|
||||
/* I2C chip address */
|
||||
#define TPS65217_CHIP_PM 0x24
|
||||
|
||||
/* Registers */
|
||||
enum {
|
||||
TPS65217_CHIPID = 0x00,
|
||||
TPS65217_POWER_PATH,
|
||||
TPS65217_INTERRUPT,
|
||||
TPS65217_CHGCONFIG0,
|
||||
TPS65217_CHGCONFIG1,
|
||||
TPS65217_CHGCONFIG2,
|
||||
TPS65217_CHGCONFIG3,
|
||||
TPS65217_WLEDCTRL1,
|
||||
TPS65217_WLEDCTRL2,
|
||||
TPS65217_MUXCTRL,
|
||||
TPS65217_STATUS,
|
||||
TPS65217_PASSWORD,
|
||||
TPS65217_PGOOD,
|
||||
TPS65217_DEFPG,
|
||||
TPS65217_DEFDCDC1,
|
||||
TPS65217_DEFDCDC2,
|
||||
TPS65217_DEFDCDC3,
|
||||
TPS65217_DEFSLEW,
|
||||
TPS65217_DEFLDO1,
|
||||
TPS65217_DEFLDO2,
|
||||
TPS65217_DEFLS1,
|
||||
TPS65217_DEFLS2,
|
||||
TPS65217_ENABLE,
|
||||
TPS65217_DEFUVLO,
|
||||
TPS65217_SEQ1,
|
||||
TPS65217_SEQ2,
|
||||
TPS65217_SEQ3,
|
||||
TPS65217_SEQ4,
|
||||
TPS65217_SEQ5,
|
||||
TPS65217_SEQ6,
|
||||
TPS65217_PMIC_NUM_OF_REGS,
|
||||
};
|
||||
|
||||
#define TPS65217_PROT_LEVEL_NONE 0x00
|
||||
#define TPS65217_PROT_LEVEL_1 0x01
|
||||
#define TPS65217_PROT_LEVEL_2 0x02
|
||||
|
||||
#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00
|
||||
#define TPS65217_PASSWORD_UNLOCK 0x7D
|
||||
|
||||
#define TPS65217_DCDC_GO 0x80
|
||||
|
||||
#define TPS65217_MASK_ALL_BITS 0xFF
|
||||
|
||||
#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03
|
||||
#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00
|
||||
#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01
|
||||
#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
|
||||
#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
|
||||
|
||||
#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
|
||||
#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
|
||||
#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
|
||||
|
||||
#define TPS65217_LDO_MASK 0x1F
|
||||
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
|
||||
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
|
||||
|
||||
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
|
||||
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
|
||||
|
||||
int tps65217_reg_read(uchar src_reg, uchar *src_val);
|
||||
int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
|
||||
uchar mask);
|
||||
int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
|
||||
#endif /* __POWER_TPS65217_H__ */
|
||||
77
include/power/tps65910.h
Normal file
77
include/power/tps65910.h
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* (C) Copyright 2011-2013
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* For more details, please see the TRM at http://www.ti.com/product/tps65910
|
||||
*/
|
||||
#ifndef __POWER_TPS65910_H__
|
||||
#define __POWER_TPS65910_H__
|
||||
|
||||
#define MPU 0
|
||||
#define CORE 1
|
||||
|
||||
#define TPS65910_SR_I2C_ADDR 0x12
|
||||
#define TPS65910_CTRL_I2C_ADDR 0x2D
|
||||
|
||||
/* PMIC Register offsets */
|
||||
enum {
|
||||
TPS65910_VDD1_REG = 0x21,
|
||||
TPS65910_VDD1_OP_REG = 0x22,
|
||||
TPS65910_VDD2_REG = 0x24,
|
||||
TPS65910_VDD2_OP_REG = 0x25,
|
||||
TPS65910_DEVCTRL_REG = 0x3F,
|
||||
};
|
||||
|
||||
/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
|
||||
#define TPS65910_VGAIN_SEL_MASK (0x3 << 6)
|
||||
#define TPS65910_ILMAX_MASK (0x1 << 5)
|
||||
#define TPS65910_TSTEP_MASK (0x7 << 2)
|
||||
#define TPS65910_ST_MASK (0x3)
|
||||
|
||||
#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6)
|
||||
#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6)
|
||||
#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6)
|
||||
#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6)
|
||||
|
||||
#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5)
|
||||
#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5)
|
||||
|
||||
#define TPS65910_REG_TSTEP_ (0x0 << 2)
|
||||
#define TPS65910_REG_TSTEP_12_5 (0x1 << 2)
|
||||
#define TPS65910_REG_TSTEP_9_4 (0x2 << 2)
|
||||
#define TPS65910_REG_TSTEP_7_5 (0x3 << 2)
|
||||
#define TPS65910_REG_TSTEP_6_25 (0x4 << 2)
|
||||
#define TPS65910_REG_TSTEP_4_7 (0x5 << 2)
|
||||
#define TPS65910_REG_TSTEP_3_12 (0x6 << 2)
|
||||
#define TPS65910_REG_TSTEP_2_5 (0x7 << 2)
|
||||
|
||||
#define TPS65910_REG_ST_OFF (0x0)
|
||||
#define TPS65910_REG_ST_ON_HI_POW (0x1)
|
||||
#define TPS65910_REG_ST_OFF_1 (0x2)
|
||||
#define TPS65910_REG_ST_ON_LOW_POW (0x3)
|
||||
|
||||
|
||||
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
|
||||
#define TPS65910_OP_REG_SEL (0x7F)
|
||||
|
||||
#define TPS65910_OP_REG_CMD_MASK (0x1 << 7)
|
||||
#define TPS65910_OP_REG_CMD_OP (0x0 << 7)
|
||||
#define TPS65910_OP_REG_CMD_SR (0x1 << 7)
|
||||
|
||||
#define TPS65910_OP_REG_SEL_MASK (0x7F)
|
||||
#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
|
||||
#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
|
||||
#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
|
||||
#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
|
||||
#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */
|
||||
|
||||
/* Device control register . (DEVCTRL_REG) */
|
||||
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
|
||||
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
|
||||
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
|
||||
|
||||
int tps65910_set_i2c_control(void);
|
||||
int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
|
||||
#endif /* __POWER_TPS65910_H__ */
|
||||
@ -87,7 +87,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
|
||||
LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
|
||||
LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
|
||||
LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
|
||||
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
|
||||
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \
|
||||
drivers/power/pmic/libpmic.o
|
||||
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
|
||||
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
|
||||
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
|
||||
|
||||
Loading…
Reference in New Issue
Block a user