net: fec_mxc: allow use with cache enabled
Ensure that transmit and receive buffers are cache-line aligned. Invalidate cache for each packet as received, update receive buffer descriptors one cache line at a time, flush cache before transmitting. Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Eric Nelson
Albert ARIBAUD
parent
2c4b3c19a1
commit
5c1ad3e6f8
@ -38,16 +38,28 @@ DECLARE_GLOBAL_DATA_PTR;
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#error "CONFIG_MII has to be defined!"
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#endif
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#ifndef CONFIG_FEC_XCV_TYPE
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#define CONFIG_FEC_XCV_TYPE MII100
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#ifndef CONFIG_FEC_XCV_TYPE
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#define CONFIG_FEC_XCV_TYPE MII100
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#endif
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/*
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* The i.MX28 operates with packets in big endian. We need to swap them before
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* sending and after receiving.
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*/
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#ifdef CONFIG_MX28
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#define CONFIG_FEC_MXC_SWAP_PACKET
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#ifdef CONFIG_MX28
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#define CONFIG_FEC_MXC_SWAP_PACKET
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#endif
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#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
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/* Check various alignment issues at compile time */
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#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
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#error "ARCH_DMA_MINALIGN must be multiple of 16!"
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#endif
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#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
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(PKTALIGN % ARCH_DMA_MINALIGN != 0))
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#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
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#endif
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#undef DEBUG
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@ -59,7 +71,7 @@ struct nbuf {
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uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
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};
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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static void swap_packet(uint32_t *packet, int length)
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{
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int i;
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@ -259,43 +271,52 @@ static int fec_tx_task_disable(struct fec_priv *fec)
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* Initialize receive task's buffer descriptors
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* @param[in] fec all we know about the device yet
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* @param[in] count receive buffer count to be allocated
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* @param[in] size size of each receive buffer
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* @param[in] dsize desired size of each receive buffer
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* @return 0 on success
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*
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* For this task we need additional memory for the data buffers. And each
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* data buffer requires some alignment. Thy must be aligned to a specific
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* boundary each (DB_DATA_ALIGNMENT).
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* boundary each.
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*/
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static int fec_rbd_init(struct fec_priv *fec, int count, int size)
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static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
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{
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int ix;
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uint32_t p = 0;
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uint32_t size;
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int i;
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/* reserve data memory and consider alignment */
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if (fec->rdb_ptr == NULL)
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fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
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p = (uint32_t)fec->rdb_ptr;
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if (!p) {
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puts("fec_mxc: not enough malloc memory\n");
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return -ENOMEM;
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}
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memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
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p += DB_DATA_ALIGNMENT-1;
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p &= ~(DB_DATA_ALIGNMENT-1);
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for (ix = 0; ix < count; ix++) {
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writel(p, &fec->rbd_base[ix].data_pointer);
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p += size;
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writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
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writew(0, &fec->rbd_base[ix].data_length);
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}
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/*
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* mark the last RBD to close the ring
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* Allocate memory for the buffers. This allocation respects the
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* alignment
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*/
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
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size = roundup(dsize, ARCH_DMA_MINALIGN);
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for (i = 0; i < count; i++) {
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uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
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if (data_ptr == 0) {
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uint8_t *data = memalign(ARCH_DMA_MINALIGN,
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size);
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if (!data) {
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printf("%s: error allocating rxbuf %d\n",
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__func__, i);
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goto err;
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}
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writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
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} /* needs allocation */
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writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
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writew(0, &fec->rbd_base[i].data_length);
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}
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/* Mark the last RBD to close the ring. */
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
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fec->rbd_index = 0;
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return 0;
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err:
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for (; i >= 0; i--) {
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uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
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free((void *)data_ptr);
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}
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return -ENOMEM;
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}
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/**
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@ -312,9 +333,13 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size)
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*/
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static void fec_tbd_init(struct fec_priv *fec)
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{
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unsigned addr = (unsigned)fec->tbd_base;
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unsigned size = roundup(2 * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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writew(0x0000, &fec->tbd_base[0].status);
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writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
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fec->tbd_index = 0;
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flush_dcache_range(addr, addr+size);
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}
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/**
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@ -324,16 +349,10 @@ static void fec_tbd_init(struct fec_priv *fec)
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*/
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static void fec_rbd_clean(int last, struct fec_bd *pRbd)
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{
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/*
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* Reset buffer descriptor as empty
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*/
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unsigned short flags = FEC_RBD_EMPTY;
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if (last)
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
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else
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writew(FEC_RBD_EMPTY, &pRbd->status);
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/*
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* no data in it
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*/
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flags |= FEC_RBD_WRAP;
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writew(flags, &pRbd->status);
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writew(0, &pRbd->data_length);
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}
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@ -387,12 +406,25 @@ static int fec_open(struct eth_device *edev)
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{
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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int speed;
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uint32_t addr, size;
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int i;
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debug("fec_open: fec_open(dev)\n");
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/* full-duplex, heartbeat disabled */
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writel(1 << 2, &fec->eth->x_cntrl);
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fec->rbd_index = 0;
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/* Invalidate all descriptors */
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for (i = 0; i < FEC_RBD_NUM - 1; i++)
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fec_rbd_clean(0, &fec->rbd_base[i]);
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fec_rbd_clean(1, &fec->rbd_base[i]);
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/* Flush the descriptors into RAM */
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size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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addr = (uint32_t)fec->rbd_base;
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flush_dcache_range(addr, addr + size);
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#ifdef FEC_QUIRK_ENET_MAC
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/* Enable ENET HW endian SWAP */
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writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
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@ -478,38 +510,55 @@ static int fec_open(struct eth_device *edev)
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static int fec_init(struct eth_device *dev, bd_t* bd)
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{
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uint32_t base;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
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uint32_t rcntrl;
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int i;
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uint32_t size;
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int i, ret;
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/* Initialize MAC address */
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fec_set_hwaddr(dev);
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/*
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* reserve memory for both buffer descriptor chains at once
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* Datasheet forces the startaddress of each chain is 16 byte
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* aligned
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* Allocate transmit descriptors, there are two in total. This
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* allocation respects cache alignment.
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*/
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if (fec->base_ptr == NULL)
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fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
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sizeof(struct fec_bd) + DB_ALIGNMENT);
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base = (uint32_t)fec->base_ptr;
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if (!base) {
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puts("fec_mxc: not enough malloc memory\n");
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return -ENOMEM;
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if (!fec->tbd_base) {
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size = roundup(2 * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
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if (!fec->tbd_base) {
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ret = -ENOMEM;
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goto err1;
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}
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memset(fec->tbd_base, 0, size);
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fec_tbd_init(fec);
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flush_dcache_range((unsigned)fec->tbd_base, size);
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}
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memset((void *)base, 0, (2 + FEC_RBD_NUM) *
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sizeof(struct fec_bd) + DB_ALIGNMENT);
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base += (DB_ALIGNMENT-1);
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base &= ~(DB_ALIGNMENT-1);
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fec->rbd_base = (struct fec_bd *)base;
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base += FEC_RBD_NUM * sizeof(struct fec_bd);
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fec->tbd_base = (struct fec_bd *)base;
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/*
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* Allocate receive descriptors. This allocation respects cache
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* alignment.
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*/
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if (!fec->rbd_base) {
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size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
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if (!fec->rbd_base) {
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ret = -ENOMEM;
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goto err2;
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}
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memset(fec->rbd_base, 0, size);
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/*
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* Initialize RxBD ring
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*/
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if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
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ret = -ENOMEM;
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goto err3;
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}
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flush_dcache_range((unsigned)fec->rbd_base,
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(unsigned)fec->rbd_base + size);
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}
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/*
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* Set interrupt mask register
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@ -566,23 +615,19 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
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writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
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/*
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* Initialize RxBD/TxBD rings
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*/
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if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
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free(fec->base_ptr);
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fec->base_ptr = NULL;
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return -ENOMEM;
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}
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fec_tbd_init(fec);
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#ifndef CONFIG_PHYLIB
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if (fec->xcv_type != SEVENWIRE)
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miiphy_restart_aneg(dev);
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#endif
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fec_open(dev);
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return 0;
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err3:
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free(fec->rbd_base);
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err2:
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free(fec->tbd_base);
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err1:
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return ret;
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}
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/**
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@ -631,9 +676,11 @@ static void fec_halt(struct eth_device *dev)
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* @param[in] length Data count in bytes
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* @return 0 on success
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*/
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static int fec_send(struct eth_device *dev, volatile void* packet, int length)
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static int fec_send(struct eth_device *dev, volatile void *packet, int length)
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{
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unsigned int status;
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uint32_t size;
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uint32_t addr;
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/*
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* This routine transmits one frame. This routine only accepts
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@ -650,15 +697,21 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
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}
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/*
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* Setup the transmit buffer
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* Note: We are always using the first buffer for transmission,
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* the second will be empty and only used to stop the DMA engine
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* Setup the transmit buffer. We are always using the first buffer for
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* transmission, the second will be empty and only used to stop the DMA
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* engine. We also flush the packet to RAM here to avoid cache trouble.
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*/
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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swap_packet((uint32_t *)packet, length);
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#endif
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addr = (uint32_t)packet;
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size = roundup(length, ARCH_DMA_MINALIGN);
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flush_dcache_range(addr, addr + size);
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writew(length, &fec->tbd_base[fec->tbd_index].data_length);
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writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
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writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
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/*
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* update BD's status now
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* This block:
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@ -671,17 +724,31 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
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status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
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writew(status, &fec->tbd_base[fec->tbd_index].status);
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/*
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* Flush data cache. This code flushes both TX descriptors to RAM.
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* After this code, the descriptors will be safely in RAM and we
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* can start DMA.
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*/
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size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
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addr = (uint32_t)fec->tbd_base;
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flush_dcache_range(addr, addr + size);
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/*
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* Enable SmartDMA transmit task
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*/
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fec_tx_task_enable(fec);
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/*
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* wait until frame is sent .
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* Wait until frame is sent. On each turn of the wait cycle, we must
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* invalidate data cache to see what's really in RAM. Also, we need
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* barrier here.
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*/
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invalidate_dcache_range(addr, addr + size);
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while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
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udelay(1);
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invalidate_dcache_range(addr, addr + size);
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}
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debug("fec_send: status 0x%x index %d\n",
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readw(&fec->tbd_base[fec->tbd_index].status),
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fec->tbd_index);
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@ -707,6 +774,8 @@ static int fec_recv(struct eth_device *dev)
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int frame_length, len = 0;
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struct nbuf *frame;
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uint16_t bd_status;
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uint32_t addr, size;
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int i;
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uchar buff[FEC_MAX_PKT_SIZE];
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/*
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@ -737,8 +806,23 @@ static int fec_recv(struct eth_device *dev)
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}
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/*
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* ensure reading the right buffer status
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* Read the buffer status. Before the status can be read, the data cache
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* must be invalidated, because the data in RAM might have been changed
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* by DMA. The descriptors are properly aligned to cachelines so there's
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* no need to worry they'd overlap.
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*
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* WARNING: By invalidating the descriptor here, we also invalidate
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* the descriptors surrounding this one. Therefore we can NOT change the
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* contents of this descriptor nor the surrounding ones. The problem is
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* that in order to mark the descriptor as processed, we need to change
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* the descriptor. The solution is to mark the whole cache line when all
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* descriptors in the cache line are processed.
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*/
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addr = (uint32_t)rbd;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
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invalidate_dcache_range(addr, addr + size);
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bd_status = readw(&rbd->status);
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debug("fec_recv: status 0x%x\n", bd_status);
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@ -750,10 +834,17 @@ static int fec_recv(struct eth_device *dev)
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*/
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frame = (struct nbuf *)readl(&rbd->data_pointer);
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frame_length = readw(&rbd->data_length) - 4;
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/*
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* Invalidate data cache over the buffer
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*/
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addr = (uint32_t)frame;
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size = roundup(frame_length, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(addr, addr + size);
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/*
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* Fill the buffer and pass it to upper layers
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*/
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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swap_packet((uint32_t *)frame->data, frame_length);
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#endif
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memcpy(buff, frame->data, frame_length);
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@ -765,11 +856,25 @@ static int fec_recv(struct eth_device *dev)
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(ulong)rbd->data_pointer,
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bd_status);
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}
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/*
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* free the current buffer, restart the engine
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* and move forward to the next buffer
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* Free the current buffer, restart the engine and move forward
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* to the next buffer. Here we check if the whole cacheline of
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* descriptors was already processed and if so, we mark it free
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* as whole.
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*/
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fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
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size = RXDESC_PER_CACHELINE - 1;
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if ((fec->rbd_index & size) == size) {
|
||||
i = fec->rbd_index - size;
|
||||
addr = (uint32_t)&fec->rbd_base[i];
|
||||
for (; i <= fec->rbd_index ; i++) {
|
||||
fec_rbd_clean(i == (FEC_RBD_NUM - 1),
|
||||
&fec->rbd_base[i]);
|
||||
}
|
||||
flush_dcache_range(addr,
|
||||
addr + ARCH_DMA_MINALIGN);
|
||||
}
|
||||
|
||||
fec_rx_task_enable(fec);
|
||||
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
|
||||
}
|
||||
@ -866,7 +971,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
|
||||
bus->read = fec_phy_read;
|
||||
bus->write = fec_phy_write;
|
||||
sprintf(bus->name, edev->name);
|
||||
#ifdef CONFIG_MX28
|
||||
#ifdef CONFIG_MX28
|
||||
/*
|
||||
* The i.MX28 has two ethernet interfaces, but they are not equal.
|
||||
* Only the first one can access the MDIO bus.
|
||||
@ -901,7 +1006,7 @@ err1:
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_FEC_MXC_MULTI
|
||||
#ifndef CONFIG_FEC_MXC_MULTI
|
||||
int fecmxc_initialize(bd_t *bd)
|
||||
{
|
||||
int lout = 1;
|
||||
|
||||
@ -233,22 +233,6 @@ struct ethernet_regs {
|
||||
#define MIIGSK_ENR_EN (1 << 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Descriptor buffer alignment
|
||||
*
|
||||
* i.MX27 requires a 16 byte alignment (but for the first element only)
|
||||
*/
|
||||
#define DB_ALIGNMENT 16
|
||||
|
||||
/**
|
||||
* @brief Data buffer alignment
|
||||
*
|
||||
* i.MX27 requires a four byte alignment for transmit and 16 bits
|
||||
* alignment for receive so take 16
|
||||
* Note: Valid for member data_pointer in struct buffer_descriptor
|
||||
*/
|
||||
#define DB_DATA_ALIGNMENT 16
|
||||
|
||||
/**
|
||||
* @brief Receive & Transmit Buffer Descriptor definitions
|
||||
*
|
||||
@ -282,8 +266,7 @@ struct fec_priv {
|
||||
struct fec_bd *tbd_base; /* TBD ring */
|
||||
int tbd_index; /* next transmit BD to write */
|
||||
bd_t *bd;
|
||||
void *rdb_ptr;
|
||||
void *base_ptr;
|
||||
uint8_t *tdb_ptr;
|
||||
int dev_id;
|
||||
int phy_id;
|
||||
struct mii_dev *bus;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user