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powerpc, 8xx: remove support for 8xx

Browse Source 
There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8xx,
so remove it (with a heavy heart, knowing that I remove
here the root of U-Boot).

Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
2017-06-07 17:33:09 +02:00
committed by Tom Rini
parent 4a30a93929
commit 5b8e76c35e
143 changed files with 45 additions and 21631 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/block/ide.c
View File

@@ -770,10 +770,6 @@ void ide_init(void)
unsigned char c;
int i, bus;
#ifdef CONFIG_IDE_8xx_PCCARD
extern int ide_devices_found; /* Initialized in check_ide_device() */
#endif /* CONFIG_IDE_8xx_PCCARD */
#ifdef CONFIG_IDE_PREINIT
WATCHDOG_RESET();
@@ -812,13 +808,6 @@ void ide_init(void)
bus * (CONFIG_SYS_IDE_MAXDEVICE /
CONFIG_SYS_IDE_MAXBUS);
#ifdef CONFIG_IDE_8xx_PCCARD
/* Skip non-ide devices from probing */
if ((ide_devices_found & (1 << bus)) == 0) {
ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
continue;
}
#endif
printf("Bus %d: ", bus);
ide_bus_ok[bus] = 0;

1
drivers/block/sil680.c
View File

@@ -18,7 +18,6 @@
* #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
*
* #define CONFIG_IDE
* #undef CONFIG_IDE_8xx_DIRECT
* #undef CONFIG_IDE_LED
* #undef CONFIG_IDE_RESET
* #define CONFIG_IDE_PREINIT

5
drivers/bootcount/bootcount.c
View File

@@ -24,11 +24,6 @@
#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
#endif /* defined(CONFIG_MPC512X) */
#if defined(CONFIG_8xx)
#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \
CPM_BOOTCOUNT_ADDR)
#endif /* defined(CONFIG_8xx) */
#if defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)

11
drivers/i2c/i2c_core.c
View File

@@ -323,11 +323,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)
{
uint8_t buf;
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
/* maybe it is now the time for it ... */
i2c_set_bus_num(i2c_get_bus_num());
#endif
i2c_read(addr, reg, 1, &buf, 1);
#ifdef DEBUG
@@ -340,12 +335,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg)
void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val)
{
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
/* maybe it is now the time for it ... */
i2c_set_bus_num(i2c_get_bus_num());
#endif
#ifdef DEBUG
printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n",
__func__, i2c_get_bus_num(), addr, reg, val);

3
drivers/i2c/soft_i2c.c
View File

@@ -97,9 +97,6 @@ DECLARE_GLOBAL_DATA_PTR;
# if defined(CONFIG_MPC8260)
# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = \
ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
# elif defined(CONFIG_8xx)
# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = \
(immap_t *)CONFIG_SYS_IMMR;
# else
# define I2C_SOFT_DECLARATIONS
# endif

1
drivers/net/4xx_enet.c
View File

@@ -67,7 +67,6 @@
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <commproc.h>
#include <asm/ppc4xx.h>
#include <asm/ppc4xx-emac.h>
#include <asm/ppc4xx-mal.h>

2
drivers/pcmcia/Makefile
View File

@@ -5,7 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o
obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
obj-y += tqm8xx_pcmcia.o
obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o

258
drivers/pcmcia/mpc8xx_pcmcia.c
View File

@@ -1,258 +0,0 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include <linux/compiler.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA)
#if defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device (int slot);
#endif
extern int pcmcia_hardware_enable (int slot);
extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
#if defined(CONFIG_CMD_PCMCIA)
extern int pcmcia_hardware_disable(int slot);
#endif
static u_int m8xx_get_graycode(u_int size);
#if 0 /* Disabled */
static u_int m8xx_get_speed(u_int ns, u_int is_io);
#endif
/* look up table for pgcrx registers */
u_int *pcmcia_pgcrx[2] = {
&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,
&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,
};
/*
* Search this table to see if the windowsize is
* supported...
*/
#define M8XX_SIZES_NO 32
static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
0x00000080, 0x00000040, 0x00000010, 0x00000020,
0x00008000, 0x00004000, 0x00001000, 0x00002000,
0x00000100, 0x00000200, 0x00000800, 0x00000400,
0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x01000000, 0x02000000, 0xffffffff, 0x04000000,
0x00010000, 0x00020000, 0x00080000, 0x00040000,
0x00800000, 0x00400000, 0x00100000, 0x00200000 };
/* -------------------------------------------------------------------- */
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \
| PCMCIA_SST(4) \
| PCMCIA_SL(9))
/* -------------------------------------------------------------------- */
int pcmcia_on (void)
{
u_long reg, base;
pcmcia_win_t *win;
u_int rc, slot;
__maybe_unused u_int slotbit;
int i;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* intialize the fixed memory windows */
win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
base = CONFIG_SYS_PCMCIA_MEM_ADDR;
if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {
printf ("Cannot set window size to 0x%08x\n",
CONFIG_SYS_PCMCIA_MEM_SIZE);
return (1);
}
slotbit = PCMCIA_SLOT_x;
for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
win->br = base;
#if (PCMCIA_SOCKETS_NO == 2)
if (i == 4) /* Another slot starting from win 4 */
slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
#endif
switch (i) {
#ifdef CONFIG_IDE_8xx_PCCARD
case 4:
case 0: { /* map attribute memory */
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
| PCMCIA_PRS_ATTR
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
case 5:
case 1: { /* map I/O window for data reg */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_16
| PCMCIA_PRS_IO
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
case 6:
case 2: { /* map I/O window for cmd/ctrl reg block */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_8
| PCMCIA_PRS_IO
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
#endif /* CONFIG_IDE_8xx_PCCARD */
default: /* set to not valid */
win->or = 0;
break;
}
debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
i, win->br, win->or);
base += CONFIG_SYS_PCMCIA_MEM_SIZE;
++win;
}
for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
/* turn off voltage */
if ((rc = pcmcia_voltage_set(slot, 0, 0)))
continue;
/* Enable external hardware */
if ((rc = pcmcia_hardware_enable(slot)))
continue;
#ifdef CONFIG_IDE_8xx_PCCARD
if ((rc = check_ide_device(i)))
continue;
#endif
}
return rc;
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_off (void)
{
int i;
pcmcia_win_t *win;
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* clear interrupt state, and disable interrupts */
((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
/* turn off interrupt and disable CxOE */
PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
/* turn off memory windows */
win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
/* disable memory window */
win->or = 0;
++win;
}
/* turn off voltage */
pcmcia_voltage_set(_slot_, 0, 0);
/* disable external hardware */
printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
pcmcia_hardware_disable(_slot_);
return 0;
}
#endif
static u_int m8xx_get_graycode(u_int size)
{
u_int k;
for (k = 0; k < M8XX_SIZES_NO; k++) {
if(m8xx_size_to_gray[k] == size)
break;
}
if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
k = -1;
return k;
}
#if 0
static u_int m8xx_get_speed(u_int ns, u_int is_io)
{
u_int reg, clocks, psst, psl, psht;
if(!ns) {
/*
* We get called with IO maps setup to 0ns
* if not specified by the user.
* They should be 255ns.
*/
if(is_io)
ns = 255;
else
ns = 100; /* fast memory if 0 */
}
/*
* In PSST, PSL, PSHT fields we tell the controller
* timing parameters in CLKOUT clock cycles.
* CLKOUT is the same as GCLK2_50.
*/
/* how we want to adjust the timing - in percent */
#define ADJ 180 /* 80 % longer accesstime - to be sure */
clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
clocks = (clocks * ADJ) / (100*1000);
if(clocks >= PCMCIA_BMT_LIMIT) {
DEBUG(0, "Max access time limit reached\n");
clocks = PCMCIA_BMT_LIMIT-1;
}
psst = clocks / 7; /* setup time */
psht = clocks / 7; /* hold time */
psl = (clocks * 5) / 7; /* strobe length */
psst += clocks - (psst + psht + psl);
reg = psst << 12;
reg |= psl << 7;
reg |= psht << 16;
return reg;
}
#endif /* 0 */
#endif /* CONFIG_PCMCIA */

254
drivers/pcmcia/tqm8xx_pcmcia.c
View File

@@ -1,254 +0,0 @@
/* -------------------------------------------------------------------- */
/* TQM8xxL Boards by TQ Components */
/* SC8xx Boards by SinoVee Microsystems */
/* -------------------------------------------------------------------- */
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_8xx
#include <mpc8xx.h>
#endif
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA) \
&& defined(CONFIG_TQM8xxL)
#if defined(CONFIG_TQM8xxL)
#define PCMCIA_BOARD_MSG "TQM8xxL"
#endif
static inline void power_config(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable
*/
clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 | 0x0004);
clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 | 0x0004);
}
static inline void power_off(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 | 0x0004);
}
static inline void power_on_5_0(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004);
setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
static inline void power_on_3_3(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);
setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
/*
* Function to retrieve the PIPR register, used for debuging purposes.
*/
static inline uint32_t debug_get_pipr(void)
{
uint32_t pipr = 0;
#ifdef DEBUG
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
#endif
return pipr;
}
static inline int check_card_is_absent(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
return pipr & (0x18000000 >> (slot << 4));
}
#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
int pcmcia_hardware_enable(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
uint reg, mask;
debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
/* Set DBGC to 00 */
clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11);
/* Clear interrupt state, and disable interrupts */
out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot));
clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot));
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= NSCU_GCRX_CXOE;
PCMCIA_PGCRX(slot) = reg;
udelay(500);
power_config(slot);
power_off(slot);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
reg = debug_get_pipr();
debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
&immap->im_pcmcia.pcmc_pipr, reg);
if (check_card_is_absent(slot)) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = in_be32(&immap->im_pcmcia.pcmc_pipr);
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg & PCMCIA_VS1(slot)) ? "n" : "ff",
(reg & PCMCIA_VS2(slot)) ? "n" : "ff");
if ((reg & mask) == mask) {
power_on_5_0(slot);
puts (" 5.0V card found: ");
} else {
power_on_3_3(slot);
puts (" 3.3V card found: ");
}
#if 0
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
cp->cp_pbdir &= ~(0x0020 | 0x0010);
cp->cp_pbpar &= ~(0x0020 | 0x0010);
udelay(500000);
#endif
udelay(1000);
debug("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
reg &= ~NSCU_GCRX_CXOE;
PCMCIA_PGCRX(slot) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug("# hardware_enable done\n");
return (0);
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
u_long reg;
debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
/* remove all power */
power_off(slot);
debug("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(10000);
return (0);
}
#endif
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
u_long reg;
uint32_t pipr = 0;
debug("voltage_set: " PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
reg |= NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug("PCMCIA power OFF\n");
power_config(slot);
power_off(slot);
switch(vcc) {
case 0: break;
case 33: power_on_3_3(slot); break;
case 50: power_on_5_0(slot); break;
default: goto done;
}
/* Checking supported voltages */
pipr = debug_get_pipr();
debug("PIPR: 0x%x --> %s\n", pipr,
(pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
if (vcc)
debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
else
debug("PCMCIA powered down\n");
done:
debug("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
reg &= ~NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
return 0;
}
#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */

1
drivers/rtc/Makefile
View File

@@ -39,7 +39,6 @@ obj-$(CONFIG_RTC_MCP79411) += ds1307.o
obj-$(CONFIG_MCFRTC) += mcfrtc.o
obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
obj-$(CONFIG_RTC_MV) += mvrtc.o
obj-$(CONFIG_RTC_MX27) += mx27rtc.o
obj-$(CONFIG_RTC_MXS) += mxsrtc.o

60
drivers/rtc/mpc8xx.c
View File

@@ -1,60 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Date & Time support for internal RTC of MPC8xx
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
ulong tim;
tim = immr->im_sit.sit_rtc;
rtc_to_tm(tim, tmp);
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
ulong tim;
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
tim = rtc_mktime(tmp);
immr->im_sitk.sitk_rtck = KAPWR_KEY;
immr->im_sit.sit_rtc = tim;
return 0;
}
void rtc_reset (void)
{
return; /* nothing to do */
}
#endif

1
drivers/usb/gadget/Makefile
View File

@@ -41,7 +41,6 @@ ifdef CONFIG_USB_DEVICE
obj-y += core.o
obj-y += ep0.o
obj-$(CONFIG_DW_UDC) += designware_udc.o
obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
endif
endif

1386
drivers/usb/gadget/mpc8xx_udc.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/video/Makefile
View File

@@ -29,7 +29,6 @@ obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
obj-$(CONFIG_L5F31188) += l5f31188.o
obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
obj-$(CONFIG_S6E8AX0) += s6e8ax0.o

400
drivers/video/mpc8xx_lcd.c
View File

@@ -1,400 +0,0 @@
/*
* (C) Copyright 2001-2002
* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
/************************************************************************/
/* ** HEADER FILES */
/************************************************************************/
/* #define DEBUG */
#include <config.h>
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <stdarg.h>
#include <lcdvideo.h>
#include <linux/types.h>
#include <stdio_dev.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
#include <lcd.h>
#ifdef CONFIG_LCD
/************************************************************************/
/* ** CONFIG STUFF -- should be moved to board config file */
/************************************************************************/
#ifndef CONFIG_LCD_INFO
#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
#endif
/*----------------------------------------------------------------------*/
#ifdef CONFIG_KYOCERA_KCS057QV1AJ
/*
* Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
*/
#define LCD_BPP LCD_COLOR4
vidinfo_t panel_info = {
640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
/*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SP19X001_Z1A
/*
* Hitachi SP19X001-. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HITACHI_SP19X001_Z1A */
/*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------*/
#ifdef CONFIG_NEC_NL6448AC33
/*
* NEC NL6448AC33-18. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448AC33 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_NEC_NL6448BC20
/*
* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC20 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_NEC_NL6448BC33_54
/*
* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC33_54 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LQ104V7DS01
/*
* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 25, 1, 0, 33
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ104V7DS01 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_16x9
/*
* Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
* not sure what it is.......
*/
vidinfo_t panel_info = {
320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
};
#endif /* CONFIG_SHARP_16x9 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LQ057Q3DC02
/*
* Sharp LQ057Q3DC02 display. Active, color, single scan.
*/
#undef LCD_DF
#define LCD_DF 12
vidinfo_t panel_info = {
320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ057Q3DC02 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LQ64D341
/*
* Sharp LQ64D341 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 128, 16, 0, 32
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ64D341 */
#ifdef CONFIG_SHARP_LQ065T9DR51U
/*
* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
*/
vidinfo_t panel_info = {
400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 248, 4, 0, 35
/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ065T9DR51U */
#ifdef CONFIG_SHARP_LQ084V1DG21
/*
* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ084V1DG21 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HLD1045
/*
* HLD1045 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HLD1045 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_PRIMEVIEW_V16C6448AC
/*
* Prime View V16C6448AC
*/
vidinfo_t panel_info = {
640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 35
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_OPTREX_BW
/*
* Optrex CBL50840-2 NF-FW 99 22 M5
* or
* Hitachi LMG6912RPFC-00T
* or
* Hitachi SP14Q002
*
* 320x240. Black & white.
*/
#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
/* 1 - 4 grey levels, 2 bpp */
/* 2 - 16 grey levels, 4 bpp */
vidinfo_t panel_info = {
320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
};
#endif /* CONFIG_OPTREX_BW */
/************************************************************************/
/* ----------------- chipset specific functions ----------------------- */
/************************************************************************/
/*
* Calculate fb size for VIDEOLFB_ATAG.
*/
ulong calc_fbsize (void)
{
ulong size;
int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
size = line_length * panel_info.vl_row;
return size;
}
void lcd_ctrl_init (void *lcdbase)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
uint lccrtmp;
uint lchcr_hpc_tmp;
/* Initialize the LCD control register according to the LCD
* parameters defined. We do everything here but enable
* the controller.
*/
lccrtmp = LCDBIT (LCCR_BNUM_BIT,
(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
#if 0
lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
lccrtmp |= LCCR_EIEN;
#endif
lcdp->lcd_lccr = lccrtmp;
lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
/* Initialize LCD controller bus priorities.
*/
immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
/* set SHFT/CLOCK division factor 4
* This needs to be set based upon display type and processor
* speed. The TFT displays run about 20 to 30 MHz.
* I was running 64 MHz processor speed.
* The value for this divider must be chosen so the result is
* an integer of the processor speed (i.e., divide by 3 with
* 64 MHz would be bad).
*/
immr->im_clkrst.car_sccr &= ~0x1F;
immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
/* Enable LCD on port D.
*/
immr->im_ioport.iop_pdpar |= 0x1FFF;
immr->im_ioport.iop_pddir |= 0x1FFF;
/* Enable LCD_A/B/C on port B.
*/
immr->im_cpm.cp_pbpar |= 0x00005001;
immr->im_cpm.cp_pbdir |= 0x00005001;
/* Load the physical address of the linear frame buffer
* into the LCD controller.
* BIG NOTE: This has to be modified to load A and B depending
* upon the split mode of the LCD.
*/
lcdp->lcd_lcfaa = (ulong)lcdbase;
lcdp->lcd_lcfba = (ulong)lcdbase;
/* MORE HACKS...This must be updated according to 823 manual
* for different panels.
* Udi Finkelstein - done - see below:
* Note: You better not try unsupported combinations such as
* 4-bit wide passive dual scan LCD at 4/8 Bit color.
*/
lchcr_hpc_tmp =
(panel_info.vl_col *
(panel_info.vl_tft ? 8 :
(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
/* use << to mult by: single scan = 1, dual scan = 2 */
panel_info.vl_splt) *
(panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
lcdp->lcd_lchcr = LCHCR_BO |
LCDBIT (LCHCR_AT_BIT, 4) |
LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
panel_info.vl_wbl;
lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
panel_info.vl_wbf;
}
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
unsigned short colreg, *cmap_ptr;
cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
colreg = ((red & 0x0F) << 8) |
((green & 0x0F) << 4) |
(blue & 0x0F) ;
*cmap_ptr = colreg;
debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
regno, &(cp->lcd_cmap[regno * 2]),
red, green, blue,
cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
}
#endif /* LCD_COLOR8 */
/*----------------------------------------------------------------------*/
ushort *configuration_get_cmap(void)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
cpm8xx_t *cp = &(immr->im_cpm);
return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
}
#if defined(CONFIG_MPC823)
void fb_put_byte(uchar **fb, uchar **from)
{
*(*fb)++ = (255 - *(*from)++);
}
#endif
#ifdef CONFIG_LCD_LOGO
#include <bmp_logo.h>
void lcd_logo_set_cmap(void)
{
int i;
ushort *cmap;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
cpm8xx_t *cp = &(immr->im_cpm);
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]);
for (i = 0; i < BMP_LOGO_COLORS; ++i)
*cmap++ = bmp_logo_palette[i];
}
#endif
void lcd_enable (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
/* Enable the LCD panel */
immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
lcdp->lcd_lccr |= LCCR_PON;
}
/************************************************************************/
#endif /* CONFIG_LCD */