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Merge branch '2021-07-06-update-to-gcc11-clang11'

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- Update CI to use gcc-11.1 and clang-11 to build everything.  This
  requires a few fixes to the code that these newer compilers have
  exposed.
This commit is contained in:
Tom Rini
2021-07-07 13:32:22 -04:00
parent 54fb6e396d 7bb1cc3bb9
commit 5b8a83551d
21 changed files with 76 additions and 72 deletions
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10
drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
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@@ -8,6 +8,7 @@
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_db.h"
#include "mv_ddr_plat.h"
#define KILLER_PATTERN_LENGTH 32
#define EXT_ACCESS_BURST_LENGTH 8
@@ -112,9 +113,12 @@ int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
int ddr3_tip_reset_fifo_ptr(u32 dev_num);
int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
int ddr3_tip_read_adll_value(u32 dev_num,
u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 reg_addr, u32 mask);
int ddr3_tip_write_adll_value(u32 dev_num,
u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
u32 reg_addr);
int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
#endif /* _DDR3_TRAINING_IP_FLOW_H_ */

4
drivers/pinctrl/mscc/mscc-common.h
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@@ -61,6 +61,6 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func,
const struct mscc_pin_data *mscc_pins, int num_pins,
char * const *function_names,
const unsigned long *mscc_gpios);
const struct pinctrl_ops mscc_pinctrl_ops;
extern const struct pinctrl_ops mscc_pinctrl_ops;
const struct dm_gpio_ops mscc_gpio_ops;
extern const struct dm_gpio_ops mscc_gpio_ops;