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arm: dts: k3-j721e: Add DT nodes for USB

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J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Vignesh Raghavendra 2019-11-18 19:16:35 +05:30 committed by Lokesh Vutla
parent f4b3c1cc33
commit 5aeab3bf5e
4 changed files with 128 additions and 0 deletions
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14
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
View File

@ -282,6 +282,20 @@
u-boot,dm-spl;
};
&main_usbss0_pins_default {
u-boot,dm-spl;
};
&usbss0 {
u-boot,dm-spl;
ti,usb2-only;
};
&usb0 {
dr_mode = "peripheral";
u-boot,dm-spl;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

37
arch/arm/dts/k3-j721e-common-proc-board.dts
View File

@ -77,3 +77,40 @@
voltage-ranges = <1800 1800 3300 3300>;
ti,driver-strength-ohm = <50>;
};
&main_pmx0 {
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
main_usbss1_pins_default: main_usbss1_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
};
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "super-speed";
};
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;
ti,usb2-only;
};
&usb1 {
dr_mode = "host";
maximum-speed = "high-speed";
};

70
arch/arm/dts/k3-j721e-main.dtsi
View File

@ -340,6 +340,76 @@
resets = <&k3_reset 15 1>;
};
usbss0: cdns_usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
clock-names = "usb2_refclk", "lpm_clk";
assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
phy@4108000 {
compatible = "ti,j721e-usb2-phy";
reg = <0x00 0x4108000 0x00 0x400>;
};
usb0: usb@6000000 {
compatible = "cdns,usb3";
reg = <0x00 0x6000000 0x00 0x10000>,
<0x00 0x6010000 0x00 0x10000>,
<0x00 0x6020000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
usbss1: cdns_usb@4114000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4114000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
clock-names = "usb2_refclk", "lpm_clk";
assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
phy@4118000 {
compatible = "ti,j721e-usb2-phy";
reg = <0x00 0x4118000 0x00 0x400>;
};
usb1: usb@6400000 {
compatible = "cdns,usb3";
reg = <0x00 0x6400000 0x00 0x10000>,
<0x00 0x6410000 0x00 0x10000>,
<0x00 0x6420000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
ufs_wrapper: ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x0 0x4e80000 0x0 0x100>;

7
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
View File

@ -112,6 +112,13 @@
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
};
&wkup_uart0 {