dm: spi: add BCM63xx SPI driver
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Álvaro Fernández Rojas
Jagan Teki
parent
6c94bd12c4
commit
5ac07d2969
@ -40,6 +40,14 @@ config ATMEL_SPI
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many AT91 (ARM) chips. This driver can be used to access
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the SPI Flash, such as AT25DF321.
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config BCM63XX_SPI
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bool "BCM6348 SPI driver"
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depends on ARCH_BMIPS
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help
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Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
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access the SPI NOR flash on platforms embedding these Broadcom
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SPI cores.
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config CADENCE_QSPI
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bool "Cadence QSPI driver"
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help
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@ -18,6 +18,7 @@ endif
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obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
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obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
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obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
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obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
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obj-$(CONFIG_CF_SPI) += cf_spi.o
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obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
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433
drivers/spi/bcm63xx_spi.c
Normal file
433
drivers/spi/bcm63xx_spi.c
Normal file
@ -0,0 +1,433 @@
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/spi/spi-bcm63xx.c:
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* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
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* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <spi.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* BCM6348 SPI core */
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#define SPI_6348_CLK 0x06
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#define SPI_6348_CMD 0x00
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#define SPI_6348_CTL 0x40
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#define SPI_6348_CTL_SHIFT 6
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#define SPI_6348_FILL 0x07
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#define SPI_6348_IR_MASK 0x04
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#define SPI_6348_IR_STAT 0x02
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#define SPI_6348_RX 0x80
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#define SPI_6348_RX_SIZE 0x3f
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#define SPI_6348_TX 0x41
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#define SPI_6348_TX_SIZE 0x3f
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/* BCM6358 SPI core */
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#define SPI_6358_CLK 0x706
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#define SPI_6358_CMD 0x700
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#define SPI_6358_CTL 0x000
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#define SPI_6358_CTL_SHIFT 14
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#define SPI_6358_FILL 0x707
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#define SPI_6358_IR_MASK 0x702
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#define SPI_6358_IR_STAT 0x704
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#define SPI_6358_RX 0x400
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#define SPI_6358_RX_SIZE 0x220
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#define SPI_6358_TX 0x002
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#define SPI_6358_TX_SIZE 0x21e
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/* SPI Clock register */
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#define SPI_CLK_SHIFT 0
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#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT)
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#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT)
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#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT)
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#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT)
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#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT)
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#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT)
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#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT)
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#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT)
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#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT)
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#define SPI_CLK_SSOFF_SHIFT 3
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#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT)
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#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
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#define SPI_CLK_BSWAP_SHIFT 7
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#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)
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/* SPI Command register */
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#define SPI_CMD_OP_SHIFT 0
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#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
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#define SPI_CMD_SLAVE_SHIFT 4
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#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT)
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#define SPI_CMD_PREPEND_SHIFT 8
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#define SPI_CMD_PREPEND_BYTES 0xf
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#define SPI_CMD_3WIRE_SHIFT 12
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#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)
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/* SPI Control register */
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#define SPI_CTL_TYPE_FD_RW 0
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#define SPI_CTL_TYPE_HD_W 1
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#define SPI_CTL_TYPE_HD_R 2
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/* SPI Interrupt registers */
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#define SPI_IR_DONE_SHIFT 0
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#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT)
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#define SPI_IR_RXOVER_SHIFT 1
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#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT)
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#define SPI_IR_TXUNDER_SHIFT 2
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#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT)
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#define SPI_IR_TXOVER_SHIFT 3
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#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT)
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#define SPI_IR_RXUNDER_SHIFT 4
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#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT)
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#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\
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SPI_IR_RXOVER_MASK |\
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SPI_IR_TXUNDER_MASK |\
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SPI_IR_TXOVER_MASK |\
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SPI_IR_RXUNDER_MASK)
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enum bcm63xx_regs_spi {
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SPI_CLK,
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SPI_CMD,
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SPI_CTL,
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SPI_CTL_SHIFT,
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SPI_FILL,
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SPI_IR_MASK,
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SPI_IR_STAT,
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SPI_RX,
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SPI_RX_SIZE,
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SPI_TX,
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SPI_TX_SIZE,
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};
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struct bcm63xx_spi_priv {
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const unsigned long *regs;
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void __iomem *base;
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size_t tx_bytes;
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uint8_t num_cs;
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};
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#define SPI_CLK_CNT 8
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static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {
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{ 25000000, SPI_CLK_25MHZ },
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{ 20000000, SPI_CLK_20MHZ },
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{ 12500000, SPI_CLK_12_50MHZ },
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{ 6250000, SPI_CLK_6_250MHZ },
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{ 3125000, SPI_CLK_3_125MHZ },
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{ 1563000, SPI_CLK_1_563MHZ },
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{ 781000, SPI_CLK_0_781MHZ },
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{ 391000, SPI_CLK_0_391MHZ }
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};
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static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
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if (cs >= priv->num_cs) {
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printf("no cs %u\n", cs);
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return -ENODEV;
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}
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return 0;
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}
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static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
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const unsigned long *regs = priv->regs;
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if (mode & SPI_LSB_FIRST)
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setbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
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else
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clrbits_8(priv->base + regs[SPI_CLK], SPI_CLK_BSWAP_MASK);
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return 0;
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}
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static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
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const unsigned long *regs = priv->regs;
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uint8_t clk_cfg;
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int i;
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/* default to lowest clock configuration */
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clk_cfg = SPI_CLK_0_391MHZ;
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/* find the closest clock configuration */
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for (i = 0; i < SPI_CLK_CNT; i++) {
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if (speed >= bcm63xx_spi_freq_table[i][0]) {
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clk_cfg = bcm63xx_spi_freq_table[i][1];
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break;
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}
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}
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/* write clock configuration */
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clrsetbits_8(priv->base + regs[SPI_CLK],
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SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
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clk_cfg | SPI_CLK_SSOFF_2);
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return 0;
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}
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/*
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* BCM63xx SPI driver doesn't allow keeping CS active between transfers since
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* they are HW controlled.
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* However, it provides a mechanism to prepend write transfers prior to read
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* transfers (with a maximum prepend of 15 bytes), which is usually enough for
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* SPI-connected flashes since reading requires prepending a write transfer of
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* 5 bytes.
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*
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* This implementation takes advantage of the prepend mechanism and combines
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* multiple transfers into a single one where possible (single/multiple write
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* transfer(s) followed by a final read/write transfer).
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* However, it's not possible to buffer reads, which means that read transfers
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* should always be done as the final ones.
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* On the other hand, take into account that combining write transfers into
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* a single one is just buffering and doesn't require prepend mechanism.
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*/
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static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
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const unsigned long *regs = priv->regs;
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size_t data_bytes = bitlen / 8;
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if (flags & SPI_XFER_BEGIN) {
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/* clear prepends */
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priv->tx_bytes = 0;
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/* initialize hardware */
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writeb_be(0, priv->base + regs[SPI_IR_MASK]);
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}
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if (din) {
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/* buffering reads not possible since cs is hw controlled */
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if (!(flags & SPI_XFER_END)) {
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printf("unable to buffer reads\n");
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return -EINVAL;
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}
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/* check rx size */
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if (data_bytes > regs[SPI_RX_SIZE]) {
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printf("max rx bytes exceeded\n");
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return -EMSGSIZE;
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}
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}
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if (dout) {
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/* check tx size */
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if (priv->tx_bytes + data_bytes > regs[SPI_TX_SIZE]) {
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printf("max tx bytes exceeded\n");
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return -EMSGSIZE;
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}
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/* copy tx data */
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memcpy_toio(priv->base + regs[SPI_TX] + priv->tx_bytes,
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dout, data_bytes);
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priv->tx_bytes += data_bytes;
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}
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if (flags & SPI_XFER_END) {
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struct dm_spi_slave_platdata *plat =
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dev_get_parent_platdata(dev);
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uint16_t val, cmd;
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int ret;
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/* determine control config */
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if (dout && !din) {
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/* buffered write transfers */
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val = priv->tx_bytes;
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val |= (SPI_CTL_TYPE_HD_W << regs[SPI_CTL_SHIFT]);
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priv->tx_bytes = 0;
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} else {
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if (dout && din && (flags & SPI_XFER_ONCE)) {
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/* full duplex read/write */
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val = data_bytes;
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val |= (SPI_CTL_TYPE_FD_RW <<
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regs[SPI_CTL_SHIFT]);
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priv->tx_bytes = 0;
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} else {
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/* prepended write transfer */
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val = data_bytes;
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val |= (SPI_CTL_TYPE_HD_R <<
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regs[SPI_CTL_SHIFT]);
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if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
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printf("max prepend bytes exceeded\n");
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return -EMSGSIZE;
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}
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}
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}
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if (regs[SPI_CTL_SHIFT] >= 8)
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writew_be(val, priv->base + regs[SPI_CTL]);
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else
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writeb_be(val, priv->base + regs[SPI_CTL]);
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/* clear interrupts */
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writeb_be(SPI_IR_CLEAR_MASK, priv->base + regs[SPI_IR_STAT]);
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/* issue the transfer */
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cmd = SPI_CMD_OP_START;
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cmd |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
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cmd |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
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if (plat->mode & SPI_3WIRE)
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cmd |= SPI_CMD_3WIRE_MASK;
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writew_be(cmd, priv->base + regs[SPI_CMD]);
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/* enable interrupts */
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writeb_be(SPI_IR_DONE_MASK, priv->base + regs[SPI_IR_MASK]);
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ret = wait_for_bit_8(priv->base + regs[SPI_IR_STAT],
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SPI_IR_DONE_MASK, true, 1000, false);
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if (ret) {
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printf("interrupt timeout\n");
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return ret;
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}
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/* copy rx data */
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if (din)
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memcpy_fromio(din, priv->base + regs[SPI_RX],
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data_bytes);
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}
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return 0;
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}
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static const struct dm_spi_ops bcm63xx_spi_ops = {
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.cs_info = bcm63xx_spi_cs_info,
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.set_mode = bcm63xx_spi_set_mode,
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.set_speed = bcm63xx_spi_set_speed,
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.xfer = bcm63xx_spi_xfer,
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};
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static const unsigned long bcm6348_spi_regs[] = {
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[SPI_CLK] = SPI_6348_CLK,
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[SPI_CMD] = SPI_6348_CMD,
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[SPI_CTL] = SPI_6348_CTL,
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[SPI_CTL_SHIFT] = SPI_6348_CTL_SHIFT,
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[SPI_FILL] = SPI_6348_FILL,
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[SPI_IR_MASK] = SPI_6348_IR_MASK,
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[SPI_IR_STAT] = SPI_6348_IR_STAT,
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[SPI_RX] = SPI_6348_RX,
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[SPI_RX_SIZE] = SPI_6348_RX_SIZE,
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[SPI_TX] = SPI_6348_TX,
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[SPI_TX_SIZE] = SPI_6348_TX_SIZE,
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};
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static const unsigned long bcm6358_spi_regs[] = {
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[SPI_CLK] = SPI_6358_CLK,
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[SPI_CMD] = SPI_6358_CMD,
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[SPI_CTL] = SPI_6358_CTL,
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[SPI_CTL_SHIFT] = SPI_6358_CTL_SHIFT,
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[SPI_FILL] = SPI_6358_FILL,
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[SPI_IR_MASK] = SPI_6358_IR_MASK,
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[SPI_IR_STAT] = SPI_6358_IR_STAT,
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[SPI_RX] = SPI_6358_RX,
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[SPI_RX_SIZE] = SPI_6358_RX_SIZE,
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[SPI_TX] = SPI_6358_TX,
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[SPI_TX_SIZE] = SPI_6358_TX_SIZE,
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};
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static const struct udevice_id bcm63xx_spi_ids[] = {
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{
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.compatible = "brcm,bcm6348-spi",
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.data = (ulong)&bcm6348_spi_regs,
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}, {
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.compatible = "brcm,bcm6358-spi",
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.data = (ulong)&bcm6358_spi_regs,
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}, { /* sentinel */ }
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};
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static int bcm63xx_spi_child_pre_probe(struct udevice *dev)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
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const unsigned long *regs = priv->regs;
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struct spi_slave *slave = dev_get_parent_priv(dev);
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struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
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/* check cs */
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if (plat->cs >= priv->num_cs) {
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printf("no cs %u\n", plat->cs);
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return -ENODEV;
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}
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/* max read/write sizes */
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slave->max_read_size = regs[SPI_RX_SIZE];
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slave->max_write_size = regs[SPI_TX_SIZE];
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return 0;
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}
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static int bcm63xx_spi_probe(struct udevice *dev)
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{
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struct bcm63xx_spi_priv *priv = dev_get_priv(dev);
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const unsigned long *regs =
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(const unsigned long *)dev_get_driver_data(dev);
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struct reset_ctl rst_ctl;
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struct clk clk;
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fdt_addr_t addr;
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fdt_size_t size;
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int ret;
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addr = devfdt_get_addr_size_index(dev, 0, &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = regs;
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priv->base = ioremap(addr, size);
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priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"num-cs", 8);
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/* enable clock */
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret < 0)
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return ret;
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ret = clk_free(&clk);
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if (ret < 0)
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return ret;
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/* perform reset */
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ret = reset_get_by_index(dev, 0, &rst_ctl);
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if (ret < 0)
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return ret;
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ret = reset_deassert(&rst_ctl);
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if (ret < 0)
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return ret;
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ret = reset_free(&rst_ctl);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* initialize hardware */
|
||||
writeb_be(0, priv->base + regs[SPI_IR_MASK]);
|
||||
|
||||
/* set fill register */
|
||||
writeb_be(0xff, priv->base + regs[SPI_FILL]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(bcm63xx_spi) = {
|
||||
.name = "bcm63xx_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = bcm63xx_spi_ids,
|
||||
.ops = &bcm63xx_spi_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv),
|
||||
.child_pre_probe = bcm63xx_spi_child_pre_probe,
|
||||
.probe = bcm63xx_spi_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user