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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini
2014-08-29 11:06:51 -04:00
parent 6af857c50d d145878d59
commit 5a1095a830
73 changed files with 6001 additions and 205 deletions
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19
board/aristainetos/Kconfig Normal file
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if TARGET_ARISTAINETOS
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "aristainetos"
config SYS_SOC
string
default "mx6"
config SYS_CONFIG_NAME
string
default "aristainetos"
endif

6
board/aristainetos/MAINTAINERS Normal file
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ARISTAINETOS BOARD
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/aristainetos/
F: include/configs/aristainetos.h
F: configs/aristainetos_defconfig

9
board/aristainetos/Makefile Normal file
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#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := aristainetos.o

519
board/aristainetos/aristainetos.c Normal file
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/*
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define DISP_PAD_CTRL (0x10)
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
struct i2c_pads_info i2c_pad_info3 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
.gp = IMX_GPIO_NR(3, 17)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart5_pads[] = {
MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const gpio_pads[] = {
/* LED enable */
MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* spi flash WP protect */
MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* backlight enable */
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED yellow */
MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED red */
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED green */
MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED blue */
MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* i2c4 scl */
MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* i2c4 sda */
MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* spi CS 1 */
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const misc_pads[] = {
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
/* OTG Power enable */
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
}
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const display_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
MX6_PAD_DI0_PIN4__GPIO4_IO20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
};
static iomux_v3_cfg_t const backlight_pads[] = {
MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spi(void)
{
int i;
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
for (i = 0; i < 3; i++)
enable_spi_clk(true, i);
/* set cs1 to high */
gpio_direction_output(ECSPI4_CS1, 1);
}
static void setup_iomux_gpio(void)
{
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
int board_mmc_init(bd_t *bis)
{
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
}
#endif
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(bd_t *bis)
{
struct iomuxc *iomuxc_regs =
(struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
setup_iomux_enet();
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
ret = enable_fec_anatop_clock(ENET_50MHz);
if (ret)
return ret;
return cpu_eth_init(bis);
}
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_lvds(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(
display_pads,
ARRAY_SIZE(display_pads));
imx_iomux_v3_setup_multiple_pads(
backlight_pads,
ARRAY_SIZE(backlight_pads));
/* enable backlight PWM 3 */
if (pwm_init(2, 0, 0))
goto error;
/* duty cycle 200ns, period: 3000ns */
if (pwm_config(2, 200, 3000))
goto error;
if (pwm_enable(2))
goto error;
return;
error:
puts("error init pwm for backlight\n");
return;
}
struct display_info_t const displays[] = {
{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_lvds,
.mode = {
.name = "lb07wv8",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 33246,
.left_margin = 88,
.right_margin = 88,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 25,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
}
}
};
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
enable_ipu_clock();
reg = readl(&mxc_ccm->cs2cdr);
/* select pll 5 clock */
reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
writel(reg, &mxc_ccm->cs2cdr);
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
}
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_gpio();
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
return 0;
}
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nfc_pads,
ARRAY_SIZE(nfc_pads));
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
int board_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_spi();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
&i2c_pad_info1);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
&i2c_pad_info2);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
&i2c_pad_info3);
/* i2c4 not used, set it to gpio input */
gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
gpio_direction_input(IMX_GPIO_NR(1, 7));
gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
gpio_direction_input(IMX_GPIO_NR(1, 8));
/* SPI NOR Flash read only */
gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
/* enable LED */
gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
gpio_request(IMX_GPIO_NR(1, 4), "LED red");
gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
gpio_request(IMX_GPIO_NR(1, 5), "LED green");
gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
setup_gpmi_nand();
/* GPIO_1 for USB_OTG_ID */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
return 0;
}
int checkboard(void)
{
puts("Board: aristaitenos\n");
return 0;
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
int ret;
ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
if (!ret)
gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
if (!ret)
gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
return 0;
}
int board_ehci_power(int port, int on)
{
if (port)
gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
else
gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
return 0;
}
#endif

33
board/aristainetos/aristainetos.cfg Normal file
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@@ -0,0 +1,33 @@
/*
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "mt41j128M.cfg"
#include "clocks.cfg"

24
board/aristainetos/clocks.cfg Normal file
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@@ -0,0 +1,24 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00c03f3f
DATA 4, CCM_CCGR1, 0x0030fcff
DATA 4, CCM_CCGR2, 0x0fffcfc0
DATA 4, CCM_CCGR3, 0x3ff0300f
DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0f0000c3
DATA 4, CCM_CCGR6, 0x000003ff

61
board/aristainetos/ddr-setup.cfg Normal file
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@@ -0,0 +1,61 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR IO TYPE */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
/* Clock */
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
/* Address */
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* Control */
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
/* Data Strobe */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030

70
board/aristainetos/mt41j128M.cfg Normal file
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@@ -0,0 +1,70 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ZQ Calibration */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/*
* DQS gating, read delay, write delay calibration values
* based on calibration compare of 0x00ffff00
*/
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
/* read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurment */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* in DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
/* MR2 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
/* MR3 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
/* MR1 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
/* MR0 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
/* ZQ calibration */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
/* final ddr setup */
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

3
board/boundary/nitrogen6x/nitrogen6x.c
View File

@@ -644,8 +644,7 @@ int overwrite_console(void)
int board_init(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,

1
board/embest/mx6boards/mx6boards.c
View File

@@ -246,6 +246,7 @@ int board_mmc_init(bd_t *bis)
riotboard_usdhc3_pads,
ARRAY_SIZE(riotboard_usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
} else {
gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(7, 8), 1);

2
board/freescale/mx31pdk/MAINTAINERS
View File

@@ -1,5 +1,5 @@
MX31PDK BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
M: Magnus Lilja <lilja.magnus@gmail.com>
S: Maintained
F: board/freescale/mx31pdk/
F: include/configs/mx31pdk.h

2
board/freescale/mx6sabresd/mx6sabresd.c
View File

@@ -466,7 +466,7 @@ static int pfuze_init(void)
if (ret)
return ret;
p = pmic_get("PFUZE100_PMIC");
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;

3
board/freescale/mx6slevk/mx6slevk.c
View File

@@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
static int setup_fec(void)
{
struct iomuxc_base_regs *iomuxc_regs =
(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */

23
board/freescale/mx6sxsabresd/Kconfig Normal file
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@@ -0,0 +1,23 @@
if TARGET_MX6SXSABRESD
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "mx6sxsabresd"
config SYS_VENDOR
string
default "freescale"
config SYS_SOC
string
default "mx6"
config SYS_CONFIG_NAME
string
default "mx6sxsabresd"
endif

6
board/freescale/mx6sxsabresd/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
MX6SXSABRESD BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
S: Maintained
F: board/freescale/mx6sxsabresd/
F: include/configs/mx6sxsabresd.h
F: configs/mx6sxsabresd_defconfig

6
board/freescale/mx6sxsabresd/Makefile Normal file
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@@ -0,0 +1,6 @@
# (C) Copyright 2014 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6sxsabresd.o

132
board/freescale/mx6sxsabresd/imximage.cfg Normal file
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@@ -0,0 +1,132 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
/* IOMUX - DDR IO Type */
DATA 4 0x020e0618 0x000c0000
DATA 4 0x020e05fc 0x00000000
/* Clock */
DATA 4 0x020e032c 0x00000030
/* Address */
DATA 4 0x020e0300 0x00000020
DATA 4 0x020e02fc 0x00000020
DATA 4 0x020e05f4 0x00000020
/* Control */
DATA 4 0x020e0340 0x00000020
DATA 4 0x020e0320 0x00000000
DATA 4 0x020e0310 0x00000020
DATA 4 0x020e0314 0x00000020
DATA 4 0x020e0614 0x00000020
/* Data Strobe */
DATA 4 0x020e05f8 0x00020000
DATA 4 0x020e0330 0x00000028
DATA 4 0x020e0334 0x00000028
DATA 4 0x020e0338 0x00000028
DATA 4 0x020e033c 0x00000028
/* Data */
DATA 4 0x020e0608 0x00020000
DATA 4 0x020e060c 0x00000028
DATA 4 0x020e0610 0x00000028
DATA 4 0x020e061c 0x00000028
DATA 4 0x020e0620 0x00000028
DATA 4 0x020e02ec 0x00000028
DATA 4 0x020e02f0 0x00000028
DATA 4 0x020e02f4 0x00000028
DATA 4 0x020e02f8 0x00000028
/* Calibrations - ZQ */
DATA 4 0x021b0800 0xa1390003
/* Write leveling */
DATA 4 0x021b080c 0x00290025
DATA 4 0x021b0810 0x00220022
/* DQS Read Gate */
DATA 4 0x021b083c 0x41480144
DATA 4 0x021b0840 0x01340130
/* Read/Write Delay */
DATA 4 0x021b0848 0x3C3E4244
DATA 4 0x021b0850 0x34363638
/* Read data bit delay */
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
/* Complete calibration by forced measurement */
DATA 4 0x021b08b8 0x00000800
/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x676b52f3
DATA 4 0x021b0010 0xb66d8b63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00011740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x006b1023
DATA 4 0x021b0040 0x0000005f
DATA 4 0x021b0000 0x84190000
/* Initialize MT41K256M16HA-125 - MR2 */
DATA 4 0x021b001c 0x04008032
/* MR3 */
DATA 4 0x021b001c 0x00008033
/* MR1 */
DATA 4 0x021b001c 0x00048031
/* MR0 */
DATA 4 0x021b001c 0x05208030
/* DDR device ZQ calibration */
DATA 4 0x021b001c 0x04008040
/* Final DDR setup, before operation start */
DATA 4 0x021b0020 0x00000800
DATA 4 0x021b0818 0x00011117
DATA 4 0x021b001c 0x00000000

295
board/freescale/mx6sxsabresd/mx6sxsabresd.c Normal file
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@@ -0,0 +1,295 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const peri_3v3_pads[] = {
MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const phy_control_pads[] = {
/* 25MHz Ethernet PHY Clock */
MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
/* ENET PHY Power */
MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* AR8031 PHY Reset */
MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int ret;
int reg;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads));
/* Enable the ENET power, active low */
gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
ret = enable_fec_anatop_clock(ENET_125MHz);
if (ret)
return ret;
return 0;
}
int board_eth_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
setup_fec();
return cpu_eth_init(bis);
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
.gp = IMX_GPIO_NR(1, 0),
},
.sda = {
.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
.gp = IMX_GPIO_NR(1, 1),
},
};
static int pfuze_init(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SW1AB standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~0x1F;
reg |= 0x1F;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
* Phy control debug reg 0
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
/* rgmii tx clock delay enable */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
ARRAY_SIZE(peri_3v3_pads));
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
return 0;
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1; /* Assume boot SD always present */
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
pfuze_init();
return 0;
}
int checkboard(void)
{
puts("Board: MX6SX SABRE SDB\n");
return 0;
}

168
board/gateworks/gw_ventana/eeprom.c
View File

@@ -6,7 +6,10 @@
*/
#include <common.h>
#include <errno.h>
#include <i2c.h>
#include <malloc.h>
#include <asm/bitops.h>
#include "gsc.h"
#include "ventana_eeprom.h"
@@ -38,14 +41,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
/* read eeprom config section */
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
puts("EEPROM: Failed to read EEPROM\n");
info->model[0] = 0;
return GW_UNKNOWN;
}
/* sanity checks */
if (info->model[0] != 'G' || info->model[1] != 'W') {
puts("EEPROM: Invalid Model in EEPROM\n");
info->model[0] = 0;
return GW_UNKNOWN;
}
@@ -55,7 +56,6 @@ read_eeprom(int bus, struct ventana_board_info *info)
if ((info->chksum[0] != chksum>>8) ||
(info->chksum[1] != (chksum&0xff))) {
puts("EEPROM: Failed EEPROM checksum\n");
info->model[0] = 0;
return GW_UNKNOWN;
}
@@ -87,3 +87,165 @@ read_eeprom(int bus, struct ventana_board_info *info)
}
return type;
}
/* list of config bits that the bootloader will remove from dtb if not set */
struct ventana_eeprom_config econfig[] = {
{ "eth0", "ethernet0", EECONFIG_ETH0 },
{ "eth1", "ethernet1", EECONFIG_ETH1 },
{ "sata", "ahci0", EECONFIG_SATA },
{ "pcie", NULL, EECONFIG_PCIE},
{ "lvds0", NULL, EECONFIG_LVDS0 },
{ "lvds1", NULL, EECONFIG_LVDS1 },
{ "usb0", NULL, EECONFIG_USB0 },
{ "usb1", NULL, EECONFIG_USB1 },
{ "mmc0", NULL, EECONFIG_SD0 },
{ "mmc1", NULL, EECONFIG_SD1 },
{ "mmc2", NULL, EECONFIG_SD2 },
{ "mmc3", NULL, EECONFIG_SD3 },
{ "uart0", NULL, EECONFIG_UART0 },
{ "uart1", NULL, EECONFIG_UART1 },
{ "uart2", NULL, EECONFIG_UART2 },
{ "uart3", NULL, EECONFIG_UART3 },
{ "uart4", NULL, EECONFIG_UART4 },
{ "ipu0", NULL, EECONFIG_IPU0 },
{ "ipu1", NULL, EECONFIG_IPU1 },
{ "can0", NULL, EECONFIG_FLEXCAN },
{ "i2c0", NULL, EECONFIG_I2C0 },
{ "i2c1", NULL, EECONFIG_I2C1 },
{ "i2c2", NULL, EECONFIG_I2C2 },
{ "vpu", NULL, EECONFIG_VPU },
{ "csi0", NULL, EECONFIG_CSI0 },
{ "csi1", NULL, EECONFIG_CSI1 },
{ "spi0", NULL, EECONFIG_ESPCI0 },
{ "spi1", NULL, EECONFIG_ESPCI1 },
{ "spi2", NULL, EECONFIG_ESPCI2 },
{ "spi3", NULL, EECONFIG_ESPCI3 },
{ "spi4", NULL, EECONFIG_ESPCI4 },
{ "spi5", NULL, EECONFIG_ESPCI5 },
{ "gps", "pps", EECONFIG_GPS },
{ "hdmi_in", NULL, EECONFIG_HDMI_IN },
{ "hdmi_out", NULL, EECONFIG_HDMI_OUT },
{ "cvbs_in", NULL, EECONFIG_VID_IN },
{ "cvbs_out", NULL, EECONFIG_VID_OUT },
{ "nand", NULL, EECONFIG_NAND },
{ /* Sentinel */ }
};
#ifdef CONFIG_CMD_EECONFIG
static struct ventana_eeprom_config *get_config(const char *name)
{
struct ventana_eeprom_config *cfg = econfig;
while (cfg->name) {
if (0 == strcmp(name, cfg->name))
return cfg;
cfg++;
}
return NULL;
}
static u8 econfig_bytes[sizeof(ventana_info.config)];
static int econfig_init = -1;
int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct ventana_eeprom_config *cfg;
struct ventana_board_info *info = &ventana_info;
int i;
if (argc < 2)
return CMD_RET_USAGE;
/* initialize */
if (econfig_init != 1) {
memcpy(econfig_bytes, info->config, sizeof(econfig_bytes));
econfig_init = 1;
}
/* list configs */
if ((strncmp(argv[1], "list", 4) == 0)) {
cfg = econfig;
while (cfg->name) {
printf("%s: %d\n", cfg->name,
test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
cfg++;
}
}
/* save */
else if ((strncmp(argv[1], "save", 4) == 0)) {
unsigned char *buf = (unsigned char *)info;
int chksum;
/* calculate new checksum */
memcpy(info->config, econfig_bytes, sizeof(econfig_bytes));
for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
chksum += buf[i];
debug("old chksum:0x%04x\n",
(info->chksum[0] << 8) | info->chksum[1]);
debug("new chksum:0x%04x\n", chksum);
info->chksum[0] = chksum >> 8;
info->chksum[1] = chksum & 0xff;
/* write new config data */
if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info,
1, econfig_bytes, sizeof(econfig_bytes))) {
printf("EEPROM: Failed updating config\n");
return CMD_RET_FAILURE;
}
/* write new config data */
if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info,
1, info->chksum, 2)) {
printf("EEPROM: Failed updating checksum\n");
return CMD_RET_FAILURE;
}
printf("Config saved to EEPROM\n");
}
/* get config */
else if (argc == 2) {
cfg = get_config(argv[1]);
if (cfg) {
printf("%s: %d\n", cfg->name,
test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
} else {
printf("invalid config: %s\n", argv[1]);
return CMD_RET_FAILURE;
}
}
/* set config */
else if (argc == 3) {
cfg = get_config(argv[1]);
if (cfg) {
if (simple_strtol(argv[2], NULL, 10)) {
test_and_set_bit(cfg->bit, econfig_bytes);
printf("Enabled %s\n", cfg->name);
} else {
test_and_clear_bit(cfg->bit, econfig_bytes);
printf("Disabled %s\n", cfg->name);
}
} else {
printf("invalid config: %s\n", argv[1]);
return CMD_RET_FAILURE;
}
}
else
return CMD_RET_USAGE;
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
econfig, 3, 0, do_econfig,
"EEPROM configuration",
"list - list config\n"
"save - save config to EEPROM\n"
"<name> - get config 'name'\n"
"<name> [0|1] - set config 'name' to value\n"
);
#endif /* CONFIG_CMD_EECONFIG */

2
board/gateworks/gw_ventana/gsc.c
View File

@@ -57,7 +57,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
break;
mdelay(10);
}
mdelay(1);
mdelay(100);
return ret;
}

271
board/gateworks/gw_ventana/gw_ventana.c
View File

@@ -50,10 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
/* I2C bus numbers */
#define I2C_GSC 0
#define I2C_PMIC 1
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -78,11 +74,18 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
/*
* EEPROM board info struct populated by read_eeprom so that we only have to
* read it once.
*/
static struct ventana_board_info ventana_info;
struct ventana_board_info ventana_info;
int board_type;
@@ -187,7 +190,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
};
/* ENET */
@@ -211,7 +214,7 @@ iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
/* NAND */
@@ -281,10 +284,10 @@ static void setup_iomux_uart(void)
#ifdef CONFIG_USB_EHCI_MX6
iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
/* OTG PWR */
IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
};
int board_ehci_hcd_init(int port)
@@ -296,15 +299,13 @@ int board_ehci_hcd_init(int port)
/* Reset USB HUB (present on GW54xx/GW53xx) */
switch (info->model[3]) {
case '3': /* GW53xx */
SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
MUX_PAD_CTRL(NO_PAD_CTRL));
SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 9), 1);
break;
case '4': /* GW54xx */
SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
MUX_PAD_CTRL(NO_PAD_CTRL));
SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 16), 1);
@@ -426,7 +427,7 @@ static void enable_lvds(struct display_info_t const *dev)
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
@@ -523,7 +524,7 @@ static void setup_display(void)
writel(reg, &iomux->gpr[3]);
/* Backlight CABEN on LVDS connector */
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -535,118 +536,128 @@ static void setup_display(void)
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* PCICK_SSON */
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* GPS_SHDN */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* VID_PWR */
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* VID_PWR */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* MIPI_DIO */
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* PCICK_SSON */
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
};
/*
@@ -677,6 +688,7 @@ struct ventana {
int dioi2c_en;
int pcie_sson;
int usb_sel;
int wdis;
};
struct ventana gpio_cfg[] = {
@@ -762,6 +774,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 2),
.vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
},
/* GW52xx */
@@ -805,6 +818,7 @@ struct ventana gpio_cfg[] = {
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
.wdis = IMX_GPIO_NR(7, 12),
},
/* GW53xx */
@@ -847,6 +861,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
},
/* GW54xx */
@@ -891,6 +906,7 @@ struct ventana gpio_cfg[] = {
.vidin_en = IMX_GPIO_NR(3, 31),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.wdis = IMX_GPIO_NR(5, 17),
},
};
@@ -902,8 +918,8 @@ int power_init_board(void)
/* configure PFUZE100 PMIC */
if (board_type == GW54xx || board_type == GW54proto) {
power_pfuze100_init(I2C_PMIC);
p = pmic_get("PFUZE100_PMIC");
power_pfuze100_init(CONFIG_I2C_PMIC);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
@@ -924,7 +940,7 @@ int power_init_board(void)
/* configure LTC3676 PMIC */
else {
power_ltc3676_init(I2C_PMIC);
power_ltc3676_init(CONFIG_I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
@@ -975,12 +991,10 @@ static void setup_board_gpio(int board)
gpio_direction_output(GP_MSATA_SEL, 0);
}
/*
* assert PCI_RST# (released by OS when clock is valid)
* TODO: figure out why leaving this de-asserted from PCI scan on boot
* causes linux pcie driver to hang during enumeration
*/
#if !defined(CONFIG_CMD_PCI)
/* assert PCI_RST# (released by OS when clock is valid) */
gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
#endif
/* turn off (active-high) user LED's */
for (i = 0; i < 4; i++) {
@@ -1016,21 +1030,27 @@ static void setup_board_gpio(int board)
if (gpio_cfg[board].usb_sel)
gpio_direction_output(gpio_cfg[board].usb_sel, 0);
/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
if (gpio_cfg[board].wdis)
gpio_direction_output(gpio_cfg[board].wdis, 1);
/*
* Configure DIO pinmux/padctl registers
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
*/
for (i = 0; i < 4; i++) {
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
unsigned ctrl = DIO_PAD_CTRL;
iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
sprintf(arg, "dio%d", i);
if (!hwconfig(arg))
continue;
s = hwconfig_subarg(arg, "padctrl", &len);
if (s)
ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
if (s) {
ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
& 0x1ffff) | MUX_MODE_SION;
}
if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
if (!quiet) {
printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
@@ -1039,7 +1059,7 @@ static void setup_board_gpio(int board)
cfg->gpio_param);
}
imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
MUX_PAD_CTRL(ctrl));
ctrl);
gpio_direction_input(cfg->gpio_param);
} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
cfg->pwm_padmux) {
@@ -1122,8 +1142,7 @@ int dram_init(void)
int board_init(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
@@ -1152,7 +1171,7 @@ int board_init(void)
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
board_type = read_eeprom(I2C_GSC, &ventana_info);
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
/* board-specifc GPIO iomux */
SETUP_IOMUX_PADS(gw_gpio_pads);
@@ -1200,7 +1219,7 @@ int checkboard(void)
return 0;
/* Display GSC firmware revision/CRC/status */
i2c_set_bus_num(I2C_GSC);
i2c_set_bus_num(CONFIG_I2C_GSC);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
printf("GSC: v%d", buf[0]);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
@@ -1264,6 +1283,10 @@ int misc_init_r(void)
else if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO))
cputype = "imx6dl";
if (8 << (ventana_info.nand_flash_size-1) >= 2048)
setenv("flash_layout", "large");
else
setenv("flash_layout", "normal");
memset(str, 0, sizeof(str));
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
str[i] = tolower(info->model[i]);
@@ -1326,7 +1349,7 @@ int misc_init_r(void)
*
* Disable the boot watchdog and display/clear the timeout flag if set
*/
i2c_set_bus_num(I2C_GSC);
i2c_set_bus_num(CONFIG_I2C_GSC);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
reg |= (1 << GSC_SC_CTRL1_WDDIS);
if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
@@ -1336,7 +1359,7 @@ int misc_init_r(void)
}
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
puts("GSC boot watchdog timeout detected");
puts("GSC boot watchdog timeout detected\n");
reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
}
@@ -1347,74 +1370,6 @@ int misc_init_r(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
/* FDT aliases associated with EEPROM config bits */
const char *fdt_aliases[] = {
"ethernet0",
"ethernet1",
"hdmi_out",
"ahci0",
"pcie",
"ssi0",
"ssi1",
"lcd0",
"lvds0",
"lvds1",
"usb0",
"usb1",
"mmc0",
"mmc1",
"mmc2",
"mmc3",
"uart0",
"uart1",
"uart2",
"uart3",
"uart4",
"ipu0",
"ipu1",
"can0",
"mipi_dsi",
"mipi_csi",
"tzasc0",
"tzasc1",
"i2c0",
"i2c1",
"i2c2",
"vpu",
"csi0",
"csi1",
"caam",
NULL,
NULL,
NULL,
NULL,
NULL,
"spi0",
"spi1",
"spi2",
"spi3",
"spi4",
"spi5",
NULL,
NULL,
"pps",
NULL,
NULL,
NULL,
"hdmi_in",
"cvbs_out",
"cvbs_in",
"nand",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
};
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@@ -1426,8 +1381,8 @@ const char *fdt_aliases[] = {
*/
void ft_board_setup(void *blob, bd_t *bd)
{
int bit;
struct ventana_board_info *info = &ventana_info;
struct ventana_eeprom_config *cfg;
struct node_info nodes[] = {
{ "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@@ -1462,9 +1417,17 @@ void ft_board_setup(void *blob, bd_t *bd)
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
*/
for (bit = 0; bit < 64; bit++) {
if (!test_bit(bit, info->config))
fdt_del_node_and_alias(blob, fdt_aliases[bit]);
if (getenv("fdt_noconfig")) {
puts(" Skiping periperhal config (fdt_noconfig defined)\n");
return;
}
cfg = econfig;
while (cfg->name) {
if (!test_bit(cfg->bit, info->config)) {
fdt_del_node_and_alias(blob, cfg->dtalias ?
cfg->dtalias : cfg->name);
}
cfg++;
}
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */

11
board/gateworks/gw_ventana/ventana_eeprom.h
View File

@@ -110,8 +110,19 @@ enum {
GW53xx,
GW54xx,
GW_UNKNOWN,
GW_BADCRC,
};
/* config items */
struct ventana_eeprom_config {
const char *name; /* name of item */
const char *dtalias; /* name of dt node to remove if not set */
int bit; /* bit within config */
};
extern struct ventana_eeprom_config econfig[];
extern struct ventana_board_info ventana_info;
int read_eeprom(int bus, struct ventana_board_info *);
#endif

3
board/solidrun/hummingboard/hummingboard.c
View File

@@ -144,8 +144,7 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis)
{
struct iomuxc_base_regs *const iomuxc_regs =
(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret = enable_fec_anatop_clock(ENET_25MHz);
if (ret)

9
board/tqc/tqma6/Makefile Normal file
View File

@@ -0,0 +1,9 @@
#
# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := tqma6.o
obj-$(CONFIG_MBA6) += tqma6_mba6.o

35
board/tqc/tqma6/README Normal file
View File

@@ -0,0 +1,35 @@
U-Boot for the TQ Systems TQMa6 modules
This file contains information for the port of
U-Boot to the TQ Systems TQMa6 modules.
1. Boot source
--------------
The following boot source is supported:
- SD/eMMC
- SPI NOR
2. Building
------------
To build U-Boot for the TQ Systems TQMa6 modules:
make tqma6<x>_<baseboard>_<boot>_config
make
x is a placeholder for the CPU variant
q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
s - means i.MX6S: TQMa6S (i.MX6S)
baseboard is a placeholder for the boot device
mmc - means eMMC
spi - mean SPI NOR
This gives the following configurations:
tqma6q_mba6_mmc_config
tqma6q_mba6_spi_config
tqma6s_mba6_mmc_config
tqma6s_mba6_spi_config

24
board/tqc/tqma6/clocks.cfg Normal file
View File

@@ -0,0 +1,24 @@
/*
* Copyright (C) 2013 Boundary Devices
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

262
board/tqc/tqma6/tqma6.c Normal file
View File

@@ -0,0 +1,262 @@
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
* Author: Markus Niebel <markus.niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
#include <i2c.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
#include "tqma6_bb.h"
DECLARE_GLOBAL_DATA_PTR;
#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
static const uint16_t tqma6_emmc_dsr = 0x0100;
/* eMMC on USDHCI3 always present */
static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
/* eMMC reset */
NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
};
/*
* According to board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 eMMC (SD3) on TQMa6
* mmc1 .. n optional slots used on baseboard
*/
struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
.esdhc_base = USDHC3_BASE_ADDR,
.max_bus_width = 8,
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is always present */
ret = 1;
else
ret = tqma6_bb_board_mmc_getcd(mmc);
return ret;
}
int board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is always present */
ret = 0;
else
ret = tqma6_bb_board_mmc_getwp(mmc);
return ret;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
ARRAY_SIZE(tqma6_usdhc3_pads));
tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
puts("Warning: failed to initialize eMMC dev\n");
} else {
struct mmc *mmc = find_mmc_device(0);
if (mmc)
mmc_set_dsr(mmc, tqma6_emmc_dsr);
}
tqma6_bb_board_mmc_init(bis);
return 0;
}
static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
/* SS1 */
NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
};
static unsigned const tqma6_ecspi1_cs[] = {
IMX_GPIO_NR(3, 19),
};
static void tqma6_iomuxc_spi(void)
{
unsigned i;
for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
gpio_direction_output(tqma6_ecspi1_cs[i], 1);
imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
ARRAY_SIZE(tqma6_ecspi1_pads));
}
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 6)
}
};
static void tqma6_setup_i2c(void)
{
/* use logical index for bus, e.g. I2C1 -> 0 */
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
}
int board_early_init_f(void)
{
return tqma6_bb_board_early_init_f();
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
tqma6_iomuxc_spi();
tqma6_setup_i2c();
tqma6_bb_board_init();
return 0;
}
static const char *tqma6_get_boardname(void)
{
u32 cpurev = get_cpu_rev();
switch ((cpurev & 0xFF000) >> 12) {
case MXC_CPU_MX6SOLO:
return "TQMa6S";
break;
case MXC_CPU_MX6DL:
return "TQMa6DL";
break;
case MXC_CPU_MX6D:
return "TQMa6D";
break;
case MXC_CPU_MX6Q:
return "TQMa6Q";
break;
default:
return "??";
};
}
int board_late_init(void)
{
struct pmic *p;
u32 reg;
setenv("board_name", tqma6_get_boardname());
/*
* configure PFUZE100 PMIC:
* TODO: should go to power_init_board if bus switching is
* fixed in generic power code
*/
power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
}
tqma6_bb_board_late_init();
return 0;
}
int checkboard(void)
{
printf("Board: %s on a %s\n", tqma6_get_boardname(),
tqma6_bb_get_boardname());
return 0;
}
/*
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
/* bring in eMMC dsr settings */
do_fixup_by_path_u32(blob,
"/soc/aips-bus@02100000/usdhc@02198000",
"dsr", tqma6_emmc_dsr, 2);
tqma6_bb_ft_board_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

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/*
* Copyright (C) 2013, 2014 TQ Systems
* Author: Markus Niebel <markus.niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TQMA6_BB__
#define __TQMA6_BB
#include <common.h>
int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
int tqma6_bb_board_mmc_init(bd_t *bis);
int tqma6_bb_board_early_init_f(void);
int tqma6_bb_board_init(void);
int tqma6_bb_board_late_init(void);
int tqma6_bb_checkboard(void);
const char *tqma6_bb_get_boardname(void);
/*
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd);
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
#endif

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/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*
* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
* Author: Markus Niebel <markus.niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
#include <malloc.h>
#include <i2c.h>
#include <micrel.h>
#include <miiphy.h>
#include <mmc.h>
#include <netdev.h>
#include "tqma6_bb.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#if defined(CONFIG_MX6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
#elif defined(CONFIG_MX6S)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
#else
#error "need to define target CPU"
#endif
#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_34ohm)
#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_60ohm)
/* disable on die termination for RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
static iomux_v3_cfg_t const mba6_enet_pads[] = {
NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
/*
* these pins are also used for config strapping by phy
*/
NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
ENET_RX_PAD_CTRL),
/* KSZ9031 PHY Reset */
NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
};
static void mba6_setup_iomuxc_enet(void)
{
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
ARRAY_SIZE(mba6_enet_pads));
/* Reset PHY */
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
/* Need delay 10ms after power on according to KSZ9031 spec */
udelay(1000 * 10);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
/*
* KSZ9031 manual: 100 usec wait time after reset before communication
* over MDIO
* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
* reset before the phy sees a high level
*/
udelay(200);
}
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
};
static void mba6_setup_iomuxc_uart(void)
{
imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
ARRAY_SIZE(mba6_uart2_pads));
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = gpio_get_value(USDHC2_WP_GPIO);
return ret;
}
static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
.esdhc_base = USDHC2_BASE_ADDR,
.max_bus_width = 4,
};
static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
/* CD */
NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
/* WP */
NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
};
int tqma6_bb_board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
ARRAY_SIZE(mba6_usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
gpio_direction_input(USDHC2_WP_GPIO);
mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
puts("Warning: failed to initialize SD\n");
return 0;
}
static struct i2c_pads_info mba6_i2c1_pads = {
/* I2C1: MBa6x */
.scl = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 26)
}
};
static void mba6_setup_i2c(void)
{
/* use logical index for bus, e.g. I2C1 -> 0 */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
}
static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
};
static unsigned const mba6_ecspi1_cs[] = {
IMX_GPIO_NR(3, 24),
IMX_GPIO_NR(3, 25),
};
static void mba6_setup_iomuxc_spi(void)
{
unsigned i;
for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
gpio_direction_output(mba6_ecspi1_cs[i], 1);
imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
ARRAY_SIZE(mba6_ecspi1_pads));
}
int board_phy_config(struct phy_device *phydev)
{
/*
* optimized pad skew values depends on CPU variant on the TQMa6x module:
* i.MX6Q/D or i.MX6DL/S
*/
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2036
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2052
#else
#error
#endif
/* min rx/tx ctrl delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_CTRL_SKEW);
/* min rx delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_RX_SKEW);
/* max tx delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_TX_SKEW);
/* rx/tx clk skew */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_CLK_SKEW);
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
bus = fec_get_miibus(base, -1);
if (!bus)
return 0;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
puts("No phy found\n");
return 0;
}
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret) {
puts("FEC MXC: probe failed\n");
free(phydev);
free(bus);
}
return 0;
}
int tqma6_bb_board_early_init_f(void)
{
mba6_setup_iomuxc_uart();
return 0;
}
int tqma6_bb_board_init(void)
{
mba6_setup_i2c();
mba6_setup_iomuxc_spi();
/* do it here - to have reset completed */
mba6_setup_iomuxc_enet();
return 0;
}
int tqma6_bb_board_late_init(void)
{
return 0;
}
const char *tqma6_bb_get_boardname(void)
{
return "MBa6x";
}
/*
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
{
/* TBD */
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

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/*
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
#define __ASSEMBLY__
#include <config.h>
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
#if defined(CONFIG_TQMA6X_MMC_BOOT)
BOOT_FROM sd
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
BOOT_FROM spi
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* TQMa6Q/D DDR config Rev. 0100B */
/* IOMUX configuration */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
/* memory interface calibration values */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* configure memory interface */
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
#include "clocks.cfg"

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/*
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
#define __ASSEMBLY__
#include <config.h>
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
#if defined(CONFIG_TQMA6X_MMC_BOOT)
BOOT_FROM sd
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
BOOT_FROM spi
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* TQMa6S DDR config Rev. 0100B */
/* IOMUX configuration */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
/* memory interface calibration values */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
/* configure memory interface */
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
#include "clocks.cfg"