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Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

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This commit is contained in:
Tom Rini 2022-09-06 09:01:39 -04:00
commit 59c51fa4ab
8 changed files with 130 additions and 136 deletions
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16
arch/riscv/dts/fu740-c000-u-boot.dtsi
View File

@ -7,11 +7,11 @@
/ { / {
cpus { cpus {
assigned-clocks = <&prci PRCI_CLK_COREPLL>; assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
assigned-clock-rates = <1200000000>; assigned-clock-rates = <1200000000>;
u-boot,dm-spl; u-boot,dm-spl;
cpu0: cpu@0 { cpu0: cpu@0 {
clocks = <&prci PRCI_CLK_COREPLL>; clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl; u-boot,dm-spl;
status = "okay"; status = "okay";
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {
@ -19,28 +19,28 @@
}; };
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
clocks = <&prci PRCI_CLK_COREPLL>; clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl; u-boot,dm-spl;
cpu1_intc: interrupt-controller { cpu1_intc: interrupt-controller {
u-boot,dm-spl; u-boot,dm-spl;
}; };
}; };
cpu2: cpu@2 { cpu2: cpu@2 {
clocks = <&prci PRCI_CLK_COREPLL>; clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl; u-boot,dm-spl;
cpu2_intc: interrupt-controller { cpu2_intc: interrupt-controller {
u-boot,dm-spl; u-boot,dm-spl;
}; };
}; };
cpu3: cpu@3 { cpu3: cpu@3 {
clocks = <&prci PRCI_CLK_COREPLL>; clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl; u-boot,dm-spl;
cpu3_intc: interrupt-controller { cpu3_intc: interrupt-controller {
u-boot,dm-spl; u-boot,dm-spl;
}; };
}; };
cpu4: cpu@4 { cpu4: cpu@4 {
clocks = <&prci PRCI_CLK_COREPLL>; clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl; u-boot,dm-spl;
cpu4_intc: interrupt-controller { cpu4_intc: interrupt-controller {
u-boot,dm-spl; u-boot,dm-spl;
@ -76,7 +76,7 @@
reg = <0x0 0x100b0000 0x0 0x0800 reg = <0x0 0x100b0000 0x0 0x0800
0x0 0x100b2000 0x0 0x2000 0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>; 0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci PRCI_CLK_DDRPLL>; clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>; clock-frequency = <933333324>;
u-boot,dm-spl; u-boot,dm-spl;
}; };
@ -100,7 +100,7 @@
}; };
&eth0 { &eth0 {
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>; assigned-clock-rates = <125125000>;
}; };

93
arch/riscv/dts/fu740-c000.dtsi
View File

@ -1,10 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 SiFive, Inc */ /* Copyright (c) 2020 SiFive, Inc */
/dts-v1/; /dts-v1/;
#include <dt-bindings/clock/sifive-fu740-prci.h> #include <dt-bindings/clock/sifive-fu740-prci.h>
#include <dt-bindings/reset/sifive-fu740-prci.h>
/ { / {
#address-cells = <2>; #address-cells = <2>;
@ -139,20 +138,21 @@
soc { soc {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; compatible = "simple-bus";
ranges; ranges;
plic0: interrupt-controller@c000000 { plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0"; #address-cells = <0>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>; reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>; riscv,ndev = <69>;
interrupt-controller; interrupt-controller;
interrupts-extended = < interrupts-extended =
&cpu0_intc 0xffffffff <&cpu0_intc 0xffffffff>,
&cpu1_intc 0xffffffff &cpu1_intc 9 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
&cpu2_intc 0xffffffff &cpu2_intc 9 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
&cpu3_intc 0xffffffff &cpu3_intc 9 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
&cpu4_intc 0xffffffff &cpu4_intc 9>; <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
}; };
prci: clock-controller@10000000 { prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci"; compatible = "sifive,fu740-c000-prci";
@ -166,7 +166,7 @@
reg = <0x0 0x10010000 0x0 0x1000>; reg = <0x0 0x10010000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <39>; interrupts = <39>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled"; status = "disabled";
}; };
uart1: serial@10011000 { uart1: serial@10011000 {
@ -174,7 +174,7 @@
reg = <0x0 0x10011000 0x0 0x1000>; reg = <0x0 0x10011000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <40>; interrupts = <40>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled"; status = "disabled";
}; };
i2c0: i2c@10030000 { i2c0: i2c@10030000 {
@ -182,7 +182,7 @@
reg = <0x0 0x10030000 0x0 0x1000>; reg = <0x0 0x10030000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <52>; interrupts = <52>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <1>; reg-io-width = <1>;
#address-cells = <1>; #address-cells = <1>;
@ -194,7 +194,7 @@
reg = <0x0 0x10031000 0x0 0x1000>; reg = <0x0 0x10031000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <53>; interrupts = <53>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <1>; reg-io-width = <1>;
#address-cells = <1>; #address-cells = <1>;
@ -203,22 +203,22 @@
}; };
qspi0: spi@10040000 { qspi0: spi@10040000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0"; compatible = "sifive,fu740-c000-spi", "sifive,spi0";
reg = <0x0 0x10040000 0x0 0x1000 reg = <0x0 0x10040000 0x0 0x1000>,
0x0 0x20000000 0x0 0x10000000>; <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <41>; interrupts = <41>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
qspi1: spi@10041000 { qspi1: spi@10041000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0"; compatible = "sifive,fu740-c000-spi", "sifive,spi0";
reg = <0x0 0x10041000 0x0 0x1000 reg = <0x0 0x10041000 0x0 0x1000>,
0x0 0x30000000 0x0 0x10000000>; <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <42>; interrupts = <42>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
@ -228,7 +228,7 @@
reg = <0x0 0x10050000 0x0 0x1000>; reg = <0x0 0x10050000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <43>; interrupts = <43>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
@ -237,12 +237,12 @@
compatible = "sifive,fu540-c000-gem"; compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <55>; interrupts = <55>;
reg = <0x0 0x10090000 0x0 0x2000 reg = <0x0 0x10090000 0x0 0x2000>,
0x0 0x100a0000 0x0 0x1000>; <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk"; clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>, clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
<&prci PRCI_CLK_GEMGXLPLL>; <&prci FU740_PRCI_CLK_GEMGXLPLL>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
@ -251,8 +251,8 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>; reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <44 45 46 47>; interrupts = <44>, <45>, <46>, <47>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
@ -260,8 +260,8 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>; reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <48 49 50 51>; interrupts = <48>, <49>, <50>, <51>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
@ -273,7 +273,7 @@
cache-size = <2097152>; cache-size = <2097152>;
cache-unified; cache-unified;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <19 21 22 20>; interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>; reg = <0x0 0x2010000 0x0 0x1000>;
}; };
gpio: gpio@10060000 { gpio: gpio@10060000 {
@ -287,28 +287,27 @@
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
clocks = <&prci PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled"; status = "disabled";
}; };
pcie@e00000000 { pcie@e00000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#num-lanes = <8>;
#size-cells = <2>;
compatible = "sifive,fu740-pcie"; compatible = "sifive,fu740-pcie";
reg = <0xe 0x00000000 0x1 0x0 #address-cells = <3>;
0xd 0xf0000000 0x0 0x10000000 #size-cells = <2>;
0x0 0x100d0000 0x0 0x1000>; #interrupt-cells = <1>;
reg = <0xe 0x00000000 0x0 0x80000000>,
<0xd 0xf0000000 0x0 0x10000000>,
<0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt"; reg-names = "dbi", "config", "mgmt";
device_type = "pci"; device_type = "pci";
dma-coherent; dma-coherent;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>; num-lanes = <0x8>;
interrupts = <56 57 58 59 60 61 62 63 64>; interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd"; interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -316,13 +315,11 @@
<0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>; <0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
pwren-gpios = <&gpio 5 0>; pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>; reset-gpios = <&gpio 8 0>;
clocks = <&prci PRCI_CLK_PCIEAUX>; resets = <&prci 4>;
clock-names = "pcieaux";
resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
reset-names = "rst_n";
status = "okay"; status = "okay";
}; };
}; };

95
arch/riscv/dts/hifive-unmatched-a00.dts
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2019-2021 SiFive, Inc */ /* Copyright (c) 2020 SiFive, Inc */
#include "fu740-c000.dtsi" #include "fu740-c000.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
@ -9,8 +9,6 @@
#define RTCCLK_FREQ 1000000 #define RTCCLK_FREQ 1000000
/ { / {
#address-cells = <2>;
#size-cells = <2>;
model = "SiFive HiFive Unmatched A00"; model = "SiFive HiFive Unmatched A00";
compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
"sifive,fu740"; "sifive,fu740";
@ -28,9 +26,6 @@
reg = <0x0 0x80000000 0x4 0x00000000>; reg = <0x0 0x80000000 0x4 0x00000000>;
}; };
soc {
};
hfclk: hfclk { hfclk: hfclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -65,10 +60,21 @@
temperature-sensor@4c { temperature-sensor@4c {
compatible = "ti,tmp451"; compatible = "ti,tmp451";
reg = <0x4c>; reg = <0x4c>;
vcc-supply = <&vdd_bpro>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
}; };
eeprom@54 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x54>;
vcc-supply = <&vdd_bpro>;
label = "board-id";
pagesize = <16>;
read-only;
size = <256>;
};
pmic@58 { pmic@58 {
compatible = "dlg,da9063"; compatible = "dlg,da9063";
reg = <0x58>; reg = <0x58>;
@ -76,48 +82,44 @@
interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller; interrupt-controller;
regulators { onkey {
vdd_bcore1: bcore1 { compatible = "dlg,da9063-onkey";
regulator-min-microvolt = <1050000>; };
regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>;
regulator-max-microamp = <5000000>;
regulator-always-on;
};
vdd_bcore2: bcore2 { rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
regulators {
vdd_bcore: bcores-merged {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>; regulator-min-microamp = <4800000>;
regulator-max-microamp = <5000000>; regulator-max-microamp = <4800000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bpro: bpro { vdd_bpro: bpro {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <2500000>; regulator-min-microamp = <2400000>;
regulator-max-microamp = <2500000>; regulator-max-microamp = <2400000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bperi: bperi { vdd_bperi: bperi {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1060000>;
regulator-min-microamp = <1500000>; regulator-min-microamp = <1500000>;
regulator-max-microamp = <1500000>; regulator-max-microamp = <1500000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bmem: bmem { vdd_bmem_bio: bmem-bio-merged {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3000000>;
regulator-max-microamp = <3000000>;
regulator-always-on;
};
vdd_bio: bio {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3000000>; regulator-min-microamp = <3000000>;
@ -128,86 +130,66 @@
vdd_ldo1: ldo1 { vdd_ldo1: ldo1 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <100000>;
regulator-max-microamp = <100000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo2: ldo2 { vdd_ldo2: ldo2 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo3: ldo3 { vdd_ldo3: ldo3 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo4: ldo4 { vdd_ldo4: ldo4 {
regulator-min-microvolt = <2500000>; regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>; regulator-max-microvolt = <2500000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo5: ldo5 { vdd_ldo5: ldo5 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <100000>;
regulator-max-microamp = <100000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo6: ldo6 { vdd_ldo6: ldo6 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo7: ldo7 { vdd_ldo7: ldo7 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo8: ldo8 { vdd_ldo8: ldo8 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ld09: ldo9 { vdd_ld09: ldo9 {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1050000>;
regulator-min-microamp = <200000>; regulator-always-on;
regulator-max-microamp = <200000>;
}; };
vdd_ldo10: ldo10 { vdd_ldo10: ldo10 {
regulator-min-microvolt = <1000000>; regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>; regulator-max-microvolt = <1000000>;
regulator-min-microamp = <300000>; regulator-always-on;
regulator-max-microamp = <300000>;
}; };
vdd_ldo11: ldo11 { vdd_ldo11: ldo11 {
regulator-min-microvolt = <2500000>; regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>; regulator-max-microvolt = <2500000>;
regulator-min-microamp = <300000>;
regulator-max-microamp = <300000>;
regulator-always-on; regulator-always-on;
}; };
}; };
@ -217,7 +199,7 @@
&qspi0 { &qspi0 {
status = "okay"; status = "okay";
flash@0 { flash@0 {
compatible = "issi,is25wp256", "jedec,spi-nor"; compatible = "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
m25p,fast-read; m25p,fast-read;
@ -234,6 +216,7 @@
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
voltage-ranges = <3300 3300>; voltage-ranges = <3300 3300>;
disable-wp; disable-wp;
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
}; };
}; };
@ -256,4 +239,8 @@
&gpio { &gpio {
status = "okay"; status = "okay";
gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3",
"PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN",
"ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4",
"EN_VDD_SD", "SD_CD";
}; };

14
cmd/riscv/sbi.c
View File

@ -68,11 +68,21 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
ret = sbi_get_impl_version(&vers); ret = sbi_get_impl_version(&vers);
if (ret < 0) if (ret < 0)
break; break;
if (impl_id == 1) switch (impl_id) {
case 1: /* OpenSBI */
printf("%ld.%ld", printf("%ld.%ld",
vers >> 16, vers & 0xffff); vers >> 16, vers & 0xffff);
else break;
case 3: /* KVM */
printf("%ld.%ld.%ld",
vers >> 16,
(vers >> 8) & 0xff,
vers & 0xff);
break;
default:
printf("0x%lx", vers); printf("0x%lx", vers);
break;
}
break; break;
} }
} }

18
drivers/clk/sifive/fu740-prci.c
View File

@ -103,53 +103,53 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
/* List of clock controls provided by the PRCI */ /* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu740[] = { struct __prci_clock __prci_init_clocks_fu740[] = {
[PRCI_CLK_COREPLL] = { [FU740_PRCI_CLK_COREPLL] = {
.name = "corepll", .name = "corepll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data, .pwd = &__prci_corepll_data,
}, },
[PRCI_CLK_DDRPLL] = { [FU740_PRCI_CLK_DDRPLL] = {
.name = "ddrpll", .name = "ddrpll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data, .pwd = &__prci_ddrpll_data,
}, },
[PRCI_CLK_GEMGXLPLL] = { [FU740_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll", .name = "gemgxlpll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data, .pwd = &__prci_gemgxlpll_data,
}, },
[PRCI_CLK_DVFSCOREPLL] = { [FU740_PRCI_CLK_DVFSCOREPLL] = {
.name = "dvfscorepll", .name = "dvfscorepll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_dvfscorepll_data, .pwd = &__prci_dvfscorepll_data,
}, },
[PRCI_CLK_HFPCLKPLL] = { [FU740_PRCI_CLK_HFPCLKPLL] = {
.name = "hfpclkpll", .name = "hfpclkpll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_hfpclkpll_data, .pwd = &__prci_hfpclkpll_data,
}, },
[PRCI_CLK_CLTXPLL] = { [FU740_PRCI_CLK_CLTXPLL] = {
.name = "cltxpll", .name = "cltxpll",
.parent_name = "hfclk", .parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops, .ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_cltxpll_data, .pwd = &__prci_cltxpll_data,
}, },
[PRCI_CLK_TLCLK] = { [FU740_PRCI_CLK_TLCLK] = {
.name = "tlclk", .name = "tlclk",
.parent_name = "corepll", .parent_name = "corepll",
.ops = &sifive_fu740_prci_tlclksel_clk_ops, .ops = &sifive_fu740_prci_tlclksel_clk_ops,
}, },
[PRCI_CLK_PCLK] = { [FU740_PRCI_CLK_PCLK] = {
.name = "pclk", .name = "pclk",
.parent_name = "hfpclkpll", .parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
}, },
[PRCI_CLK_PCIEAUX] { [FU740_PRCI_CLK_PCIE_AUX] {
.name = "pcieaux", .name = "pcieaux",
.parent_name = "", .parent_name = "",
.ops = &sifive_fu740_prci_pcieaux_clk_ops, .ops = &sifive_fu740_prci_pcieaux_clk_ops,

4
drivers/clk/sifive/sifive-prci.c
View File

@ -685,14 +685,14 @@ static int sifive_prci_probe(struct udevice *dev)
* case the design uses hfpclk to drive * case the design uses hfpclk to drive
* Chiplink * Chiplink
*/ */
pc = &data->clks[PRCI_CLK_HFPCLKPLL]; pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
parent_rate = sifive_prci_parent_rate(pc, data); parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000, sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate); parent_rate);
pc->ops->enable_clk(pc, 1); pc->ops->enable_clk(pc, 1);
} else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) { } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
/* CLTX pll init */ /* CLTX pll init */
pc = &data->clks[PRCI_CLK_CLTXPLL]; pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
parent_rate = sifive_prci_parent_rate(pc, data); parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000, sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate); parent_rate);

1
drivers/sysreset/Kconfig
View File

@ -113,6 +113,7 @@ config SYSRESET_PSCI
config SYSRESET_SBI config SYSRESET_SBI
bool "Enable support for SBI System Reset" bool "Enable support for SBI System Reset"
depends on RISCV_SMODE && SBI_V02 depends on RISCV_SMODE && SBI_V02
default y
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
help help
Enable system reset and poweroff via the SBI system reset extension. Enable system reset and poweroff via the SBI system reset extension.

25
include/dt-bindings/clock/sifive-fu740-prci.h
View File

@ -1,10 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/* /*
* Copyright (C) 2020-2021 SiFive, Inc. * Copyright (C) 2019 SiFive, Inc.
* Wesley Terpstra * Wesley Terpstra
* Paul Walmsley * Paul Walmsley
* Zong Li * Zong Li
* Pragnesh Patel
*/ */
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
@ -12,14 +11,14 @@
/* Clock indexes for use by Device Tree data and the PRCI driver */ /* Clock indexes for use by Device Tree data and the PRCI driver */
#define PRCI_CLK_COREPLL 0 #define FU740_PRCI_CLK_COREPLL 0
#define PRCI_CLK_DDRPLL 1 #define FU740_PRCI_CLK_DDRPLL 1
#define PRCI_CLK_GEMGXLPLL 2 #define FU740_PRCI_CLK_GEMGXLPLL 2
#define PRCI_CLK_DVFSCOREPLL 3 #define FU740_PRCI_CLK_DVFSCOREPLL 3
#define PRCI_CLK_HFPCLKPLL 4 #define FU740_PRCI_CLK_HFPCLKPLL 4
#define PRCI_CLK_CLTXPLL 5 #define FU740_PRCI_CLK_CLTXPLL 5
#define PRCI_CLK_TLCLK 6 #define FU740_PRCI_CLK_TLCLK 6
#define PRCI_CLK_PCLK 7 #define FU740_PRCI_CLK_PCLK 7
#define PRCI_CLK_PCIEAUX 8 #define FU740_PRCI_CLK_PCIE_AUX 8
#endif #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */