ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev Kit
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also known as the RZ/G2M. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
parent
4ce9566e43
commit
59028798ab
@ -774,6 +774,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
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r8a7794-silk-u-boot.dtb
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dtb-$(CONFIG_RCAR_GEN3) += \
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r8a774a1-beacon-rzg2m-kit.dtb \
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r8a77950-ulcb-u-boot.dtb \
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r8a77950-salvator-x-u-boot.dtb \
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r8a77960-ulcb-u-boot.dtb \
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597
arch/arm/dts/beacon-renesom-baseboard.dtsi
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597
arch/arm/dts/beacon-renesom-baseboard.dtsi
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@ -0,0 +1,597 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020, Compass Electronics Group, LLC
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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serial0 = &scif2;
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serial1 = &hscif0;
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serial2 = &hscif1;
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serial3 = &scif0;
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serial4 = &hscif2;
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serial5 = &scif5;
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spi0 = &msiof0;
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spi1 = &msiof1;
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spi2 = &msiof2;
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spi3 = &msiof3;
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ethernet0 = &avb;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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power-supply = <®_lcd>;
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enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
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pwms = <&pwm0 0 50000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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};
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hdmi0-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi0_con: endpoint {
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remote-endpoint = <&rcar_dw_hdmi0_out>;
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};
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};
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};
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keys {
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compatible = "gpio-keys";
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key-1 {
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gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_1>;
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label = "Switch-1";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-2 {
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gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_2>;
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label = "Switch-2";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-3 {
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gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_3>;
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label = "Switch-3";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-4 {
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gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_4>;
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label = "Switch-4";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-5 {
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gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_5>;
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label = "Switch-4";
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wakeup-source;
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debounce-interval = <20>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&led_pins>;
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pinctrl-names = "default";
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led0 {
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gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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label = "LED0";
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linux,default-trigger = "heartbeat";
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};
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led1 {
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gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
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label = "LED1";
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linux,default-trigger = "heartbeat";
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};
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led2 {
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gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
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label = "LED2";
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linux,default-trigger = "heartbeat";
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};
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led3 {
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gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
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label = "LED3";
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linux,default-trigger = "heartbeat";
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};
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};
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reg_audio: regulator_audio {
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compatible = "regulator-fixed";
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regulator-name = "audio-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_lcd: regulator-lcd {
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compatible = "regulator-fixed";
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regulator-name = "lcd_panel_pwr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_lcd_reset: regulator-lcd-reset {
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compatible = "regulator-fixed";
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regulator-name = "nLCD_RESET";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_lcd>;
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};
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reg_cam0: regulator_camera {
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compatible = "regulator-fixed";
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regulator-name = "reg_cam0";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_cam1: regulator_camera {
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compatible = "regulator-fixed";
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regulator-name = "reg_cam1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100000>;
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};
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sound_card {
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compatible = "audio-graph-card";
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label = "rcar-sound";
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dais = <&rsnd_port0>, <&rsnd_port1>;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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regulator-always-on;
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};
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/* External DU dot clocks */
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x302_clk: x302-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33000000>;
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};
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x304_clk: x304-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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&audio_clk_a {
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clock-frequency = <22579200>;
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};
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&audio_clk_b {
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clock-frequency = <22579200>;
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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renesas,can-clock-select = <0x0>;
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status = "okay";
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};
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&can1 {
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pinctrl-0 = <&can1_pins>;
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pinctrl-names = "default";
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renesas,can-clock-select = <0x0>;
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status = "okay";
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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<&versaclock5 1>,
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<&x302_clk>,
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<&versaclock5 2>;
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clock-names = "du.0", "du.1", "du.2",
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"dclkin.0", "dclkin.1", "dclkin.2";
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};
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&ehci0 {
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dr_mode = "otg";
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>;
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};
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&ehci1 {
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>;
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};
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&hdmi0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dw_hdmi0_in: endpoint {
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remote-endpoint = <&du_out_hdmi0>;
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};
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};
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port@1 {
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reg = <1>;
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rcar_dw_hdmi0_out: endpoint {
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remote-endpoint = <&hdmi0_con>;
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};
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};
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port@2 {
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/* HDMI sound */
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reg = <2>;
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dw_hdmi0_snd_in: endpoint {
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remote-endpoint = <&rsnd_endpoint1>;
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};
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};
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};
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};
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&hscif1 {
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pinctrl-0 = <&hscif1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&hsusb {
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dr_mode = "otg";
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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gpio_exp2: gpio@21 {
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compatible = "onnn,pca9654";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_exp3: gpio@22 {
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compatible = "onnn,pca9654";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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versaclock6_bb: versaclock6_bb@6a {
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compatible = "idt,5p49v6965";
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reg = <0x6a>;
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#clock-cells = <1>;
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clocks = <&x304_clk>;
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clock-names = "xin";
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/* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
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assigned-clocks = <&versaclock6_bb 1>,
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<&versaclock6_bb 2>,
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<&versaclock6_bb 3>,
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<&versaclock6_bb 4>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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};
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&i2c5 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c5_pins>;
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pinctrl-names = "default";
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codec: wm8962@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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DCVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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AVDD-supply = <®_audio>;
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CPVDD-supply = <®_audio>;
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MICVDD-supply = <®_audio>;
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PLLVDD-supply = <®_audio>;
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SPKVDD1-supply = <®_audio>;
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SPKVDD2-supply = <®_audio>;
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gpio-cfg = <
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0x0000 /* 0:Default */
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0x0000 /* 1:Default */
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0x0000 /* 2:Default */
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0x0000 /* 3:Default */
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0x0000 /* 4:Default */
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0x0000 /* 5:Default */
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>;
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port {
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wm8962_endpoint: endpoint {
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remote-endpoint = <&rsnd_endpoint0>;
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};
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};
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};
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/* 0 - lcd_reset */
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/* 1 - lcd_pwr */
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/* 2 - lcd_select */
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/* 3 - backlight-enable */
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/* 4 - Touch_shdwn */
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/* 5 - LCD_H_pol */
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/* 6 - lcd_V_pol */
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gpio_exp1: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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touchscreen@26 {
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compatible = "ilitek,ili2117";
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reg = <0x26>;
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interrupt-parent = <&gpio5>;
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interrupts = <9 IRQ_TYPE_EDGE_RISING>;
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wakeup-source;
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};
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};
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&ohci0 {
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dr_mode = "otg";
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status = "okay";
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};
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&ohci1 {
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status = "okay";
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};
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&pciec0 {
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status = "okay";
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};
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&pciec1 {
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status = "okay";
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pfc {
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can0_pins: can0 {
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groups = "can0_data_a";
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function = "can0";
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};
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can1_pins: can1 {
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groups = "can1_data";
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function = "can1";
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};
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du_pins: du {
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groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp";
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function = "du";
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};
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i2c2_pins: i2c2 {
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groups = "i2c2_a";
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function = "i2c2";
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};
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i2c5_pins: i2c5 {
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groups = "i2c5";
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function = "i2c5";
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};
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led_pins: leds {
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/* GP_0_4 , AVS1, AVS2, GP_7_3 */
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pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3";
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bias-pull-down;
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};
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msiof1_pins: msiof1 {
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groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g";
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function = "msiof1";
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};
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pwm0_pins: pwm0 {
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groups = "pwm0";
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function = "pwm0";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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sound_pins: sound {
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groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
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function = "ssi";
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};
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sound_clk_pins: sound_clk {
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groups = "audio_clk_a_a";
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function = "audio_clk";
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};
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usb0_pins: usb0 {
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mux {
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groups = "usb0";
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function = "usb0";
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};
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};
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usb1_pins: usb1 {
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mux {
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groups = "usb1";
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function = "usb1";
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};
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};
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usb30_pins: usb30 {
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mux {
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groups = "usb30";
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function = "usb30";
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};
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};
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};
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&pwm0 {
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pinctrl-0 = <&pwm0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&rcar_sound {
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pinctrl-0 = <&sound_pins &sound_clk_pins>;
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pinctrl-names = "default";
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/* Single DAI */
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#sound-dai-cells = <0>;
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/* audio_clkout0/1/2/3 */
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||||
#clock-cells = <1>;
|
||||
clock-frequency = <11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rsnd_port0: port@0 {
|
||||
reg = <0>;
|
||||
rsnd_endpoint0: endpoint {
|
||||
remote-endpoint = <&wm8962_endpoint>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint0>;
|
||||
frame-master = <&rsnd_endpoint0>;
|
||||
|
||||
playback = <&ssi1 &dvc1 &src1>;
|
||||
capture = <&ssi0>;
|
||||
};
|
||||
};
|
||||
rsnd_port1: port@1 {
|
||||
reg = <0x01>;
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif5 {
|
||||
pinctrl-0 = <&scif5_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
312
arch/arm/dts/beacon-renesom-som.dtsi
Normal file
312
arch/arm/dts/beacon-renesom-som.dtsi
Normal file
@ -0,0 +1,312 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
osc_32k: osc_32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
wlan_pwrseq: wlan_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&osc_32k>;
|
||||
clock-names = "ext_clock";
|
||||
post-power-on-delay-ms = <80>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
usb_hub_reset {
|
||||
gpio-hog;
|
||||
gpios = <10 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "usb-hub-reset";
|
||||
};
|
||||
};
|
||||
|
||||
&hscif0 {
|
||||
pinctrl-0 = <&hscif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
max-speed = <4000000>;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&osc_32k>;
|
||||
clock-names = "extclk";
|
||||
};
|
||||
};
|
||||
|
||||
&hscif2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hscif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pca9654: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"i2c4_20_0",
|
||||
"wl_reg_on",
|
||||
"bt_reg_on",
|
||||
"i2c4_20_3",
|
||||
"i2c4_20_4",
|
||||
"bt_dev_wake",
|
||||
"i2c4_20_6",
|
||||
"i2c4_20_7";
|
||||
};
|
||||
|
||||
pca9654_lte: gpio@21 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x21>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"i2c4_21_0",
|
||||
"zoe_pwr_on",
|
||||
"zoe_extint",
|
||||
"zoe_reset_n",
|
||||
"sara_reset",
|
||||
"i2c4_21_5",
|
||||
"sara_pwr_off",
|
||||
"sara_networking_status";
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "microchip, at24c64", "atmel,24c64";
|
||||
pagesize = <32>;
|
||||
read-only; /* Manufacturing EEPROM programmed at factory */
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
versaclock5: versaclock_som@6a {
|
||||
compatible = "idt,5p49v6965";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&x304_clk>;
|
||||
clock-names = "xin";
|
||||
/* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
|
||||
assigned-clocks = <&versaclock5 1>,
|
||||
<&versaclock5 2>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>;
|
||||
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mdio", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
pins_mdio {
|
||||
groups = "avb_mdio";
|
||||
drive-strength = <24>;
|
||||
};
|
||||
|
||||
pins_mii_tx {
|
||||
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
|
||||
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
hscif0_pins: hscif0 {
|
||||
groups = "hscif0_data", "hscif0_ctrl";
|
||||
function = "hscif0";
|
||||
};
|
||||
|
||||
hscif1_pins: hscif1 {
|
||||
groups = "hscif1_data_a", "hscif1_ctrl_a";
|
||||
function = "hscif1";
|
||||
};
|
||||
|
||||
hscif2_pins: hscif2 {
|
||||
groups = "hscif2_data_a";
|
||||
function = "hscif2";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif5_pins: scif5 {
|
||||
groups = "scif5_data_a";
|
||||
function = "scif5";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_a";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
pm-ignore-notify;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&wlan_pwrseq>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-1 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_extal_clk {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&usb3s0_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&vspb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vspi0 {
|
||||
status = "okay";
|
||||
};
|
34
arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
Normal file
34
arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
Normal file
@ -0,0 +1,34 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&prr {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
/delete-property/ cd-gpios;
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
status = "disabled";
|
||||
};
|
15
arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
Normal file
15
arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r8a774a1.dtsi"
|
||||
#include "beacon-renesom-som.dtsi"
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2M Development Kit";
|
||||
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
|
||||
};
|
@ -46,6 +46,11 @@ choice
|
||||
prompt "Renesas ARM64 SoCs board select"
|
||||
optional
|
||||
|
||||
config TARGET_BEACON_RZG2M
|
||||
bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
|
||||
select R8A774A1
|
||||
select PINCTRL_PFC_R8A774A1
|
||||
|
||||
config TARGET_CONDOR
|
||||
bool "Condor board"
|
||||
imply R8A77980
|
||||
@ -103,6 +108,7 @@ source "board/renesas/eagle/Kconfig"
|
||||
source "board/renesas/ebisu/Kconfig"
|
||||
source "board/renesas/salvator-x/Kconfig"
|
||||
source "board/renesas/ulcb/Kconfig"
|
||||
source "board/beacon/beacon-rzg2m/Kconfig"
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
default 0x80000 if TARGET_SALVATOR_X
|
||||
|
15
board/beacon/beacon-rzg2m/Kconfig
Normal file
15
board/beacon/beacon-rzg2m/Kconfig
Normal file
@ -0,0 +1,15 @@
|
||||
if TARGET_BEACON_RZG2M
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "beacon-rzg2m"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "beacon"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "beacon-rzg2m"
|
||||
|
||||
endif
|
6
board/beacon/beacon-rzg2m/MAINTAINERS
Normal file
6
board/beacon/beacon-rzg2m/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
BEACON_RZG2M BOARD
|
||||
M: Adam Ford <aford173@gmail.com>
|
||||
S: Maintained
|
||||
F: board/beacon/beacon-rzg2m/
|
||||
F: include/configs/beacon-rzg2m.h
|
||||
F: configs/r8a774a1_beacon_defconfig
|
9
board/beacon/beacon-rzg2m/Makefile
Normal file
9
board/beacon/beacon-rzg2m/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# board/renesas/hihope-rzg2m/Makefile
|
||||
#
|
||||
# Copyright (C) 2019 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := beacon-rzg2m.o
|
52
board/beacon/beacon-rzg2m/beacon-rzg2m.c
Normal file
52
board/beacon/beacon-rzg2m/beacon-rzg2m.c
Normal file
@ -0,0 +1,52 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* Kconfig forces this on, so just return 0 */
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
if (fdtdec_setup_mem_size_base() != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
fdtdec_setup_memory_banksize();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RST_BASE 0xE6160000
|
||||
#define RST_CA57RESCNT (RST_BASE + 0x40)
|
||||
#define RST_CODE 0xA5A5000F
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
writel(RST_CODE, RST_CA57RESCNT);
|
||||
}
|
64
configs/r8a774a1_beacon_defconfig
Normal file
64
configs/r8a774a1_beacon_defconfig
Normal file
@ -0,0 +1,64 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_BEACON_RZG2M=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
89
include/configs/beacon-rzg2m.h
Normal file
89
include/configs/beacon-rzg2m.h
Normal file
@ -0,0 +1,89 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
#ifndef __BEACON_RZG2M_H
|
||||
#define __BEACON_RZG2M_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */
|
||||
/* #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1
|
||||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"usb_pgood_delay=2000\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttySC0,115200\0" \
|
||||
"fdt_addr=0x48000000\0" \
|
||||
"loadaddr=0x48080000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcrootpart=2\0" \
|
||||
"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
" root=PARTUUID=${uuid} rootwait rw ${optargs}\0" \
|
||||
"loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs ${jh_clk} console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
#endif /* __BEACON_RZG2M_H */
|
Loading…
Reference in New Issue
Block a user