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clk: zynq: Show watchdog clock rate properly

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watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
2018-02-21 15:06:20 +01:00
parent 1cf6cac4d1
commit 58afff43e3
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/clk_zynq.c
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@@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
return zynq_clk_get_peripheral_rate(priv, id, two_divs); return zynq_clk_get_peripheral_rate(priv, id, two_divs);
case dma_clk: case dma_clk:
return zynq_clk_get_cpu_rate(priv, cpu_2x_clk); return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
case usb0_aper_clk ... smc_aper_clk: case usb0_aper_clk ... swdt_clk:
return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
default: default:
return -ENXIO; return -ENXIO;