Merge branch 'master' of git://git.denx.de/u-boot-sh
This commit is contained in:
commit
589cf349f0
@ -6,4 +6,13 @@
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#if !defined(CONFIG_CPU_SH2)
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#include <asm/processor.h>
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
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#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
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#endif
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#endif
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|
@ -203,9 +203,6 @@
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#define PYDR 0xA405016A
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#define PZDR 0xA405016C
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/* Ether */
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#define EDMR 0xA4600000
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/* UBC */
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/* H-UDI */
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|
@ -13,44 +13,25 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <sh_tmu.h>
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#define TCR_TPSC 0x07
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#if defined(CONFIG_CPU_SH3)
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#define TSTR 0x2
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#define TCR0 0xc
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#endif /* CONFIG_CPU_SH3 */
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static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
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#define TSTR 0x4
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#define TCR0 0x10
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#endif /* CONFIG_CPU_SH4 */
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unsigned long get_tbclk(void)
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{
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u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
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return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
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}
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unsigned long timer_read_counter(void)
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{
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return ~readl(&tmu->tcnt0);
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}
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static void tmu_timer_start(unsigned int timer)
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{
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if (timer > 2)
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return;
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writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
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}
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static void tmu_timer_stop(unsigned int timer)
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{
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if (timer > 2)
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return;
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writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
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}
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#define TCR_TPSC 0x07
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#define TSTR_STR0 BIT(0)
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int timer_init(void)
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{
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u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
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writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
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tmu_timer_stop(0);
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tmu_timer_start(0);
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writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
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writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
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writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
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return 0;
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}
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|
@ -61,8 +61,6 @@
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#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
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#define CPLD_DONE_DAT 0x20
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#define HIZCRB ((vu_short *)0xA405015A)
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/* data */
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#define CPLD_NOMAL_START 0xA0A80000
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#define CPLD_SAFE_START 0xA0AC0000
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@ -191,7 +189,7 @@ void init_cpld(void)
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if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
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return;
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*HIZCRB = 0x0000;
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*((vu_short *)HIZCRB) = 0x0000;
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*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
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/* write CPLD data from NOR flash to device */
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|
@ -91,8 +91,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#endif /* __MIGO_R_H */
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|
@ -37,9 +37,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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|
@ -112,8 +112,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#endif /* __AP325RXA_H */
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|
@ -100,8 +100,6 @@
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#else
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#define CONFIG_SYS_CLK_FREQ 44444444
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#endif
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __AP_SH4A_4A_H */
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|
@ -18,6 +18,9 @@
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_TMU_TIMER
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
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#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
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#define CONFIG_SYS_DCACHE_OFF
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/* STACK */
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@ -91,8 +94,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __ARMADILLO_800EVA_H */
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|
@ -52,8 +52,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* ENV setting */
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#if !defined(CONFIG_MTD_NOR_FLASH)
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|
@ -131,8 +131,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 41666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __ECOVEC_H */
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|
@ -69,9 +69,7 @@
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/* Clock */
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* Ether */
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#define CONFIG_SH_ETHER_USE_PORT (1)
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|
@ -33,9 +33,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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|
@ -33,9 +33,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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|
@ -34,9 +34,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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|
@ -49,9 +49,7 @@
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/* Clocks */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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/* UART */
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#define CONFIG_CONS_SCIF0 1
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@ -60,9 +60,7 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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/* PCMCIA */
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#define CONFIG_IDE_PCMCIA 1
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@ -82,8 +82,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#endif /* __MS7722SE_H */
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@ -62,8 +62,6 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __MS7750SE_H */
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|
@ -38,9 +38,6 @@
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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|
@ -98,8 +98,6 @@
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#else
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#define CONFIG_SYS_CLK_FREQ 44444444
|
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#endif
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __R0P7734_H */
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|
@ -46,9 +46,7 @@
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* SuperH Clock setting
|
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*/
|
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#define CONFIG_SYS_CLK_FREQ 60000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
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/*
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|
@ -71,9 +71,7 @@
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/* Board Clock */
|
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#define CONFIG_SYS_CLK_FREQ 33333333
|
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* PCI Controller */
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#if defined(CONFIG_CMD_PCI)
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|
@ -22,7 +22,6 @@
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|
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#define CONFIG_ARCH_CPU_INIT
|
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|
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#define CONFIG_TMU_TIMER
|
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#ifndef CONFIG_PINCTRL_PFC
|
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#define CONFIG_SH_GPIO_PFC
|
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#endif
|
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@ -57,4 +56,10 @@
|
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#undef CONFIG_SPI_FLASH_MTD
|
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#endif
|
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/* Timer */
|
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#define CONFIG_TMU_TIMER
|
||||
#define CONFIG_SYS_TIMER_COUNTS_DOWN
|
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#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
|
||||
#define CONFIG_SYS_TIMER_RATE (32500000 / 4) /* CP/4 */
|
||||
|
||||
#endif /* __RCAR_GEN2_COMMON_H */
|
||||
|
@ -58,7 +58,6 @@
|
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|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
|
||||
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
|
||||
|
@ -47,7 +47,6 @@
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 36000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
|
||||
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
|
||||
|
@ -46,7 +46,6 @@
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66125000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
|
||||
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
|
||||
|
@ -75,7 +75,5 @@
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 48000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#endif /* __SH7752EVB_H */
|
||||
|
@ -75,7 +75,5 @@
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 48000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#endif /* __SH7753EVB_H */
|
||||
|
@ -87,7 +87,5 @@
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 48000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#endif /* __SH7757LCR_H */
|
||||
|
@ -69,9 +69,7 @@
|
||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
|
@ -126,8 +126,6 @@
|
||||
/* Board Clock */
|
||||
/* The SCIF used external clock. system clock only used timer. */
|
||||
#define CONFIG_SYS_CLK_FREQ 50000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
#endif /* __SH7785LCR_H */
|
||||
|
@ -78,9 +78,7 @@
|
||||
#else
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif /* CONFIG_T_SH7706LSR */
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
/* Network device */
|
||||
#define CONFIG_DRIVER_NE2000
|
||||
|
@ -38,9 +38,6 @@
|
||||
/* Board Clock */
|
||||
#define RMOBILE_XTAL_CLK 20000000u
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
|
@ -42,9 +42,6 @@
|
||||
/* Board Clock */
|
||||
#define RMOBILE_XTAL_CLK 20000000u
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
|
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SH_TMU_H
|
||||
#define __SH_TMU_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#if defined(CONFIG_CPU_SH3)
|
||||
struct tmu_regs {
|
||||
u8 tocr;
|
||||
u8 reserved0;
|
||||
u8 tstr;
|
||||
u8 reserved1;
|
||||
u32 tcor0;
|
||||
u32 tcnt0;
|
||||
u16 tcr0;
|
||||
u16 reserved2;
|
||||
u32 tcor1;
|
||||
u32 tcnt1;
|
||||
u16 tcr1;
|
||||
u16 reserved3;
|
||||
u32 tcor2;
|
||||
u32 tcnt2;
|
||||
u16 tcr2;
|
||||
u16 reserved4;
|
||||
u32 tcpr2;
|
||||
};
|
||||
#endif /* CONFIG_CPU_SH3 */
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
|
||||
struct tmu_regs {
|
||||
u32 reserved;
|
||||
u8 tstr;
|
||||
u8 reserved2[3];
|
||||
u32 tcor0;
|
||||
u32 tcnt0;
|
||||
u16 tcr0;
|
||||
u16 reserved3;
|
||||
u32 tcor1;
|
||||
u32 tcnt1;
|
||||
u16 tcr1;
|
||||
u16 reserved4;
|
||||
u32 tcor2;
|
||||
u32 tcnt2;
|
||||
u16 tcr2;
|
||||
u16 reserved5;
|
||||
};
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
|
||||
static inline unsigned long get_tmu0_clk_rate(void)
|
||||
{
|
||||
return CONFIG_SH_TMU_CLK_FREQ;
|
||||
}
|
||||
|
||||
#endif /* __SH_TMU_H */
|
@ -4277,7 +4277,6 @@ CONFIG_SYS_TMRINTR_PEND
|
||||
CONFIG_SYS_TMRINTR_PRI
|
||||
CONFIG_SYS_TMRPND_REG
|
||||
CONFIG_SYS_TMR_BASE
|
||||
CONFIG_SYS_TMU_CLK_DIV
|
||||
CONFIG_SYS_TSEC1
|
||||
CONFIG_SYS_TSEC1_OFFSET
|
||||
CONFIG_SYS_TSEC2
|
||||
|
Loading…
Reference in New Issue
Block a user