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board: esd: remove remainders of dead boards

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Commit 99bcad18 deleted ADCIOP and DASA_SIM board support
but missed to delete board/esd/adciop and board/esd/dasa_sim.
It also missed to add entries to doc/README.scrapyard.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
This commit is contained in:
Masahiro Yamada 2014-03-31 12:59:58 +09:00 committed by Tom Rini
parent 6873fae3a9
commit 585cd86c78
13 changed files with 2 additions and 4877 deletions
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8
board/esd/adciop/Makefile
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o

87
board/esd/adciop/adciop.c
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include "adciop.h"
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
{
/*
* Set port pin in escc2 to keep living, and configure user led output
*/
*(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */
*(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */
/*
* Init pci regs
*/
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
char str[64];
int i = getenv_f("serial#", str, sizeof (str));
puts ("Board: ");
if (!i || strncmp (str, "ADCIOP", 6)) {
puts ("### No HW ID - assuming ADCIOP\n");
return (1);
}
puts (str);
putc ('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}

28
board/esd/adciop/adciop.h
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@ -1,28 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

97
board/esd/adciop/flash.c
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@ -1,97 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
if (size_b1 > size_b0) {
printf ("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,
size_b0, size_b0<<20
);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
flash_info[1].sector_count = -1;
flash_info[0].size = 0;
flash_info[1].size = 0;
return (0);
}
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
FLASH_BASE0_PRELIM+size_b0-1,
&flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0),
&flash_info[1]);
flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
FLASH_BASE0_PRELIM+size_b0+size_b1-1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
flash_protect(FLAG_PROTECT_CLEAR,
FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
FLASH_BASE0_PRELIM+size_b0-1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}

8
board/esd/dasa_sim/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o

209
board/esd/dasa_sim/cmd_dasa_sim.c
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@ -1,209 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/io.h>
#define OK 0
#define ERROR (-1)
extern u_long pci9054_iobase;
/***************************************************************************
*
* Routines for PLX PCI9054 eeprom access
*
*/
static unsigned int PciEepromReadLongVPD (int offs)
{
unsigned int value;
unsigned int ret;
int count;
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
(offs << 16) | 0x0003);
count = 0;
for (;;) {
udelay (10 * 1000);
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
if ((ret & 0x80000000) != 0) {
break;
} else {
count++;
if (count > 10) {
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
break;
}
}
}
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
return value;
}
static int PciEepromWriteLongVPD (int offs, unsigned int value)
{
unsigned int ret;
int count;
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
(offs << 16) | 0x80000003);
count = 0;
for (;;) {
udelay (10 * 1000);
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
if ((ret & 0x80000000) == 0) {
break;
} else {
count++;
if (count > 10) {
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
break;
}
}
}
return true;
}
static void showPci9054 (void)
{
int val;
int l, i;
/* read 9054-values */
for (l = 0; l < 6; l++) {
printf ("%02x: ", l * 0x10);
for (i = 0; i < 4; i++) {
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
l * 16 + i * 4,
(unsigned int *)&val);
printf ("%08x ", val);
}
printf ("\n");
}
printf ("\n");
for (l = 0; l < 7; l++) {
printf ("%02x: ", l * 0x10);
for (i = 0; i < 4; i++)
printf ("%08x ",
PciEepromReadLongVPD ((i + l * 4) * 4));
printf ("\n");
}
printf ("\n");
}
static void updatePci9054 (void)
{
/*
* Set EEPROM write-protect register to 0
*/
out_be32 ((void *)(pci9054_iobase + 0x0c),
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
/* Long Serial EEPROM Load Registers... */
PciEepromWriteLongVPD (0x00, 0x905410b5);
PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
PciEepromWriteLongVPD (0x08, 0x28140100);
PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
PciEepromWriteLongVPD (0x10, 0x00000000);
/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
PciEepromWriteLongVPD (0x34, 0x00000000);
PciEepromWriteLongVPD (0x38, 0x00000000);
PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
PciEepromWriteLongVPD (0x40, 0x00000000);
/* Extra Long Serial EEPROM Load Registers... */
PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
/* Offset to LAS1: Group 1: 0x00040000 */
/* Group 2: 0x00080000 */
/* Group 3: 0x000c0000 */
PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
}
static void clearPci9054 (void)
{
/*
* Set EEPROM write-protect register to 0
*/
out_be32 ((void *)(pci9054_iobase + 0x0c),
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
/* Long Serial EEPROM Load Registers... */
PciEepromWriteLongVPD (0x00, 0xffffffff);
PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
printf ("Finished clearing PLX PCI9054 EEPROM!\n");
}
/* ------------------------------------------------------------------------- */
int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
char * const argv[])
{
if (strcmp (argv[1], "info") == 0) {
showPci9054 ();
return 0;
}
if (strcmp (argv[1], "update") == 0) {
updatePci9054 ();
return 0;
}
if (strcmp (argv[1], "clear") == 0) {
clearPci9054 ();
return 0;
}
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
pci9054, 3, 1, do_pci9054,
"PLX PCI9054 EEPROM access",
"pci9054 info - print EEPROM values\n"
"pci9054 update - updates EEPROM with default values"
);
/* ------------------------------------------------------------------------- */

198
board/esd/dasa_sim/dasa_sim.c
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/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include "dasa_sim.h"
/* ------------------------------------------------------------------------- */
#undef FPGA_DEBUG
#define _NOT_USED_ 0xFFFFFFFF
/* ------------------------------------------------------------------------- */
/* fpga configuration data - generated by bit2inc */
static unsigned char fpgadata[] = {
#include "fpgadata.c"
};
#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
#define LOAD_LONG(a) a
/******************************************************************************
*
* sysFpgaBoot - Load fpga-image into fpga
*
*/
static int fpgaBoot (void)
{
int i, j, index, len;
unsigned char b;
int imageSize;
imageSize = sizeof (fpgadata);
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
index += len + 3;
}
/* search for preamble 0xFF2X */
for (index = 0; index < imageSize - 1; index++) {
if ((fpgadata[index] == 0xff)
&& ((fpgadata[index + 1] & 0xf0) == 0x20))
break;
}
/* enable cs1 instead of user0... */
*(unsigned long *) 0x50000084 &= ~0x00000002;
#ifdef FPGA_DEBUG
printf ("%s\n",
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
"NOT DONE" : "DONE");
#endif
/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
*(unsigned long *) 0x50000084 &= ~0x00000400;
udelay (FPGA_PRG_SLEEP * 1000);
*(unsigned long *) 0x50000084 |= 0x00000400;
udelay (FPGA_PRG_SLEEP * 1000);
#ifdef FPGA_DEBUG
printf ("%s\n",
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
"NOT DONE" : "DONE");
#endif
/* cs1: disable burst, disable ready */
*(unsigned long *) 0x50000114 &= ~0x00000300;
/* cs1: set write timing */
*(unsigned long *) 0x50000118 |= 0x00010900;
/* write configuration-data into fpga... */
for (i = index; i < imageSize; i++) {
b = fpgadata[i];
for (j = 0; j < 8; j++) {
*(unsigned long *) 0x30000000 =
((b & 0x80) == 0x80)
? LOAD_LONG (0x03030101)
: LOAD_LONG (0x02020000);
b <<= 1;
}
}
#ifdef FPGA_DEBUG
printf ("%s\n",
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
"NOT DONE" : "DONE");
#endif
/* set cs1 to 32 bit data-width, disable burst, enable ready */
*(unsigned long *) 0x50000114 |= 0x00000202;
*(unsigned long *) 0x50000114 &= ~0x00000100;
/* cs1: set iop access to little endian */
*(unsigned long *) 0x50000114 &= ~0x00000010;
/* cs1: set read and write timing */
*(unsigned long *) 0x50000118 = 0x00010000;
*(unsigned long *) 0x5000011c = 0x00010001;
#ifdef FPGA_DEBUG
printf ("%s\n",
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
"NOT DONE" : "DONE");
#endif
/* wait for 30 ms... */
udelay (30 * 1000);
/* check if fpga's DONE signal - correctly booted ? */
if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
return -1;
return 0;
}
int board_early_init_f (void)
{
/*
* Init pci regs
*/
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
int index;
int len;
char str[64];
int i = getenv_f("serial#", str, sizeof (str));
int fpga;
unsigned short val;
puts ("Board: ");
/*
* Boot onboard FPGA
*/
fpga = fpgaBoot ();
if (!i || strncmp (str, "DASA_SIM", 8)) {
puts ("### No HW ID - assuming DASA_SIM");
}
puts (str);
if (fpga == 0) {
val = *(unsigned short *) 0x30000202;
printf (" (Id=%d Version=%d Revision=%d)",
(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf ("%s ", &(fpgadata[index + 1]));
index += len + 3;
}
} else {
puts ("\nFPGA: Booting failed!");
}
putc ('\n');
return 0;
}
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}

28
board/esd/dasa_sim/dasa_sim.h
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@ -1,28 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

164
board/esd/dasa_sim/eeprom.c
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@ -1,164 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#define EEPROM_CAP 0x50000358
#define EEPROM_DATA 0x5000035c
unsigned int eepromReadLong(int offs)
{
unsigned int value;
unsigned short ret;
int count;
out_be16((void *)EEPROM_CAP, offs);
count = 0;
for (;;)
{
count++;
ret = in_be16((void *)EEPROM_CAP);
if ((ret & 0x8000) != 0)
break;
}
value = in_be32((void *)EEPROM_DATA);
return value;
}
unsigned char eepromReadByte(int offs)
{
unsigned int valueLong;
unsigned char *ptr;
valueLong = eepromReadLong(offs & ~3);
ptr = (unsigned char *)&valueLong;
return ptr[offs & 3];
}
void eepromWriteLong(int offs, unsigned int value)
{
unsigned short ret;
int count;
count = 0;
out_be32((void *)EEPROM_DATA, value);
out_be16((void *)EEPROM_CAP, 0x8000 + offs);
for (;;)
{
count++;
ret = in_be16((void *)EEPROM_CAP);
if ((ret & 0x8000) == 0)
break;
}
}
void eepromWriteByte(int offs, unsigned char valueByte)
{
unsigned int valueLong;
unsigned char *ptr;
valueLong = eepromReadLong(offs & ~3);
ptr = (unsigned char *)&valueLong;
ptr[offs & 3] = valueByte;
eepromWriteLong(offs & ~3, valueLong);
}
void i2c_read (uchar *addr, int alen, uchar *buffer, int len)
{
int i;
int len2, ptr;
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
ptr = *(short *)addr;
/*
* Read till lword boundary
*/
len2 = 4 - (*(short *)addr & 0x0003);
for (i=0; i<len2; i++)
{
*buffer++ = eepromReadByte(ptr++);
}
/*
* Read all lwords
*/
len2 = (len - len2) >> 2;
for (i=0; i<len2; i++)
{
*(unsigned int *)buffer = eepromReadLong(ptr);
buffer += 4;
ptr += 4;
}
/*
* Read last bytes
*/
len2 = (*(short *)addr + len) & 0x0003;
for (i=0; i<len2; i++)
{
*buffer++ = eepromReadByte(ptr++);
}
}
void i2c_write (uchar *addr, int alen, uchar *buffer, int len)
{
int i;
int len2, ptr;
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
ptr = *(short *)addr;
/*
* Write till lword boundary
*/
len2 = 4 - (*(short *)addr & 0x0003);
for (i=0; i<len2; i++)
{
eepromWriteByte(ptr++, *buffer++);
}
/*
* Write all lwords
*/
len2 = (len - len2) >> 2;
for (i=0; i<len2; i++)
{
eepromWriteLong(ptr, *(unsigned int *)buffer);
buffer += 4;
ptr += 4;
}
/*
* Write last bytes
*/
len2 = (*(short *)addr + len) & 0x0003;
for (i=0; i<len2; i++)
{
eepromWriteByte(ptr++, *buffer++);
}
}

58
board/esd/dasa_sim/flash.c
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@ -1,58 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-monitor_flash_len,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}

3903
board/esd/dasa_sim/fpgadata.c
View File

File diff suppressed because it is too large Load Diff

89
board/esd/dasa_sim/u-boot.lds
View File

@ -1,89 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
KEEP(*(.resetvec))
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/ppc4xx/start.o (.text)
. = env_offset;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

2
doc/README.scrapyard
View File

@ -44,6 +44,8 @@ LANTEC powerpc mpc850 1b0757e 2012-10-28 Wolfgang Den
SCM powerpc mpc8260 1b0757e 2012-10-28 Wolfgang Grandegger <wg@denx.de>
SX1 arm arm925t 53c4154 2012-10-26
TQM85xx powerpc MPC85xx d923a5d 2012-10-04 Stefan Roese <sr@denx.de>
ADCIOP powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
DASA_SIM powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park@samsung.com>
tb0229 mips mips32 3f3110d 2011-12-12
rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de>