xilinx-ppc440: Remove support for v5fx30teval

It is just a specialized version of xilinx-ppc440

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ricardo Ribalda Delgado
2016-01-26 11:24:06 +01:00
committed by Michal Simek
parent 70c29dcdbc
commit 583aefb89c
9 changed files with 0 additions and 128 deletions

View File

@@ -1,12 +0,0 @@
if TARGET_V5FX30TEVAL
config SYS_BOARD
default "v5fx30teval"
config SYS_VENDOR
default "avnet"
config SYS_CONFIG_NAME
default "v5fx30teval"
endif

View File

@@ -1,7 +0,0 @@
V5FX30TEVAL BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
S: Maintained
F: board/avnet/v5fx30teval/
F: include/configs/v5fx30teval.h
F: configs/v5fx30teval_defconfig
F: configs/v5fx30teval_flash_defconfig

View File

@@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += v5fx30teval.o
include $(srctree)/board/xilinx/ppc440-generic/Makefile

View File

@@ -1,17 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Avnet Virtex 5 FX30 Evaluation Board\n");
return 0;
}

View File

@@ -1,22 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters.h by Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif