ARM: rmobile: Add support R-Car Generation 3
This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
parent
a7da6f8c3d
commit
581183def6
@ -8,8 +8,13 @@ config RCAR_32
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bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
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select CPU_V7
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config RCAR_GEN3
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bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
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select ARM64
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endchoice
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source "arch/arm/mach-rmobile/Kconfig.32"
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source "arch/arm/mach-rmobile/Kconfig.64"
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endif
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12
arch/arm/mach-rmobile/Kconfig.64
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12
arch/arm/mach-rmobile/Kconfig.64
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@ -0,0 +1,12 @@
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if RCAR_GEN3
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choice
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prompt "Renesus ARM64 SoCs board select"
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optional
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endchoice
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config SYS_SOC
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default "rmobile"
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endif
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100
arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
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100
arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
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@ -0,0 +1,100 @@
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/*
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* ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
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#define __ASM_ARCH_RCAR_GEN3_BASE_H
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/*
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* R-Car (R8A7750) I/O Addresses
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*/
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#define RWDT_BASE 0xE6020000
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#define SWDT_BASE 0xE6030000
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#define LBSC_BASE 0xEE220200
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#define TMU_BASE 0xE61E0000
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#define GPIO5_BASE 0xE6055000
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/* SCIF */
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#define SCIF0_BASE 0xE6E60000
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#define SCIF1_BASE 0xE6E68000
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#define SCIF2_BASE 0xE6E88000
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#define SCIF3_BASE 0xE6C50000
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#define SCIF4_BASE 0xE6C40000
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#define SCIF5_BASE 0xE6F30000
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/* Module stop status register */
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#define MSTPSR0 0xE6150030
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#define MSTPSR1 0xE6150038
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#define MSTPSR2 0xE6150040
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#define MSTPSR3 0xE6150048
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#define MSTPSR4 0xE615004C
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#define MSTPSR5 0xE615003C
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#define MSTPSR6 0xE61501C0
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#define MSTPSR7 0xE61501C4
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#define MSTPSR8 0xE61509A0
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#define MSTPSR9 0xE61509A4
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#define MSTPSR10 0xE61509A8
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#define MSTPSR11 0xE61509AC
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/* Realtime module stop control register */
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#define RMSTPCR0 0xE6150110
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#define RMSTPCR1 0xE6150114
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#define RMSTPCR2 0xE6150118
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#define RMSTPCR3 0xE615011C
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#define RMSTPCR4 0xE6150120
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#define RMSTPCR5 0xE6150124
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#define RMSTPCR6 0xE6150128
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#define RMSTPCR7 0xE615012C
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#define RMSTPCR8 0xE6150980
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#define RMSTPCR9 0xE6150984
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#define RMSTPCR10 0xE6150988
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#define RMSTPCR11 0xE615098C
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/* System module stop control register */
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#define SMSTPCR0 0xE6150130
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#define SMSTPCR1 0xE6150134
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#define SMSTPCR2 0xE6150138
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#define SMSTPCR3 0xE615013C
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#define SMSTPCR4 0xE6150140
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#define SMSTPCR5 0xE6150144
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#define SMSTPCR6 0xE6150148
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#define SMSTPCR7 0xE615014C
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#define SMSTPCR8 0xE6150990
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#define SMSTPCR9 0xE6150994
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#define SMSTPCR10 0xE6150998
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#define SMSTPCR11 0xE615099C
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/* SDHI */
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#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
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#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
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#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
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#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
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/* PFC */
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#define PFC_PUEN6 0xE6060418
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#define PUEN_USB1_OVC (1 << 2)
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#define PUEN_USB1_PWEN (1 << 1)
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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/* RWDT */
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struct rcar_rwdt {
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u32 rwtcnt;
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u32 rwtcsra;
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u32 rwtcsrb;
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};
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/* SWDT */
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struct rcar_swdt {
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u32 swtcnt;
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u32 swtcsra;
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u32 swtcsrb;
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};
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#endif
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#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */
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76
arch/arm/mach-rmobile/lowlevel_init_gen3.S
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76
arch/arm/mach-rmobile/lowlevel_init_gen3.S
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@ -0,0 +1,76 @@
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/*
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* arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
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* This file is lowlevel initialize routine.
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*
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* (C) Copyright 2015 Renesas Electronics Corporation
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*
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* This file is based on the arch/arm/cpu/armv8/start.S
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*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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#ifndef CONFIG_ARMV8_MULTIENTRY
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/*
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* For single-entry systems the lowlevel init is very simple.
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*/
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ldr x0, =GICD_BASE
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bl gic_init_secure
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#else /* CONFIG_ARMV8_MULTIENTRY is set */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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branch_if_master x0, x1, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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bl armv8_switch_to_el2
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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bl armv8_switch_to_el1
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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bl s_init
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2:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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@ -29,7 +30,10 @@ static struct mstp_ctl mstptbl[] = {
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RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
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{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
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RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
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/* No MSTP6 */
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#ifdef CONFIG_RCAR_GEN3
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{ SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
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RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
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#endif
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{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
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RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
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{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
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