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riscv: Add indirect stringification to csr_xxx ops

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With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Bin Meng 2018-12-12 06:12:39 -08:00 committed by Andes
parent aef59e5cc4
commit 57fe5c64cb
1 changed files with 9 additions and 7 deletions
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16
arch/riscv/include/asm/csr.h
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@ -61,10 +61,12 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#define xcsr(csr) #csr
#define csr_swap(csr, val) \ #define csr_swap(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \ : "=r" (__v) : "rK" (__v) \
: "memory"); \ : "memory"); \
__v; \ __v; \
@ -73,7 +75,7 @@
#define csr_read(csr) \ #define csr_read(csr) \
({ \ ({ \
register unsigned long __v; \ register unsigned long __v; \
__asm__ __volatile__ ("csrr %0, " #csr \ __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
: "=r" (__v) : \ : "=r" (__v) : \
: "memory"); \ : "memory"); \
__v; \ __v; \
@ -82,7 +84,7 @@
#define csr_write(csr, val) \ #define csr_write(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrw " #csr ", %0" \ __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
: : "rK" (__v) \ : : "rK" (__v) \
: "memory"); \ : "memory"); \
}) })
@ -90,7 +92,7 @@
#define csr_read_set(csr, val) \ #define csr_read_set(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \ : "=r" (__v) : "rK" (__v) \
: "memory"); \ : "memory"); \
__v; \ __v; \
@ -99,7 +101,7 @@
#define csr_set(csr, val) \ #define csr_set(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrs " #csr ", %0" \ __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
: : "rK" (__v) \ : : "rK" (__v) \
: "memory"); \ : "memory"); \
}) })
@ -107,7 +109,7 @@
#define csr_read_clear(csr, val) \ #define csr_read_clear(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
: "=r" (__v) : "rK" (__v) \ : "=r" (__v) : "rK" (__v) \
: "memory"); \ : "memory"); \
__v; \ __v; \
@ -116,7 +118,7 @@
#define csr_clear(csr, val) \ #define csr_clear(csr, val) \
({ \ ({ \
unsigned long __v = (unsigned long)(val); \ unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrc " #csr ", %0" \ __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
: : "rK" (__v) \ : : "rK" (__v) \
: "memory"); \ : "memory"); \
}) })