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Support PCIe extended config registers

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FSL PCIe block has extended cfg registers in the 100 and 400 range.
For example, to read the LTSSM register: pci display <busn>.0 404 1

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
This commit is contained in:
Ed Swarthout 2007-07-11 14:52:01 -05:00 committed by Wolfgang Denk
parent ba5feb1258
commit 571f49fa71
1 changed files with 2 additions and 2 deletions
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4
drivers/pci_indirect.c
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@ -45,7 +45,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_E500)
#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
@ -55,7 +55,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
b = b - hose->first_busno; \
dev = PCI_BDF(b, d, f); \
*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
*(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \