From aba27acf6711dce0ef1507f2f9f02a80d70a45da Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 26 Jun 2013 16:04:26 +0200 Subject: [PATCH 1/6] powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA A set of accessor functions was added to be able to access not only memory mapped FPGA in a generic way. Thanks to Wolfgang Denk for getting this sorted properly. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/405ep/405ep.c | 22 +++++------ board/gdsys/405ep/dlvision-10g.c | 18 ++++++--- board/gdsys/405ep/io.c | 16 +++++--- board/gdsys/405ep/iocon.c | 24 ++++++++---- board/gdsys/405ep/neo.c | 13 +++++-- board/gdsys/405ex/405ex.c | 22 +++++------ board/gdsys/405ex/io64.c | 34 ++++++++-------- board/gdsys/common/Makefile | 2 + board/gdsys/common/fpga.c | 41 ++++++++++++++++++++ board/gdsys/common/osd.c | 66 +++++++++++++++++--------------- include/configs/dlvision-10g.h | 6 +++ include/configs/io.h | 5 +++ include/configs/io64.h | 6 +++ include/configs/iocon.h | 5 +++ include/configs/neo.h | 5 +++ include/gdsys_fpga.h | 43 +++++++++++++++++---- 16 files changed, 229 insertions(+), 99 deletions(-) create mode 100644 board/gdsys/common/fpga.c diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index f0df2e39e6..426dc05c7d 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -18,6 +18,12 @@ #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + DECLARE_GLOBAL_DATA_PTR; int get_fpga_state(unsigned dev) @@ -90,23 +96,17 @@ int board_early_init_r(void) gd405ep_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - struct ihs_fpga *fpga = - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI - u16 *reflection_target = &fpga->reflection_low; -#else - u16 *reflection_target = &fpga->reflection_high; -#endif /* * wait for fpga out of reset */ ctr = 0; while (1) { - out_le16(&fpga->reflection_low, - REFLECTION_TESTPATTERN); + u16 val; - if (in_le16(reflection_target) == - REFLECTION_TESTPATTERN_INV) + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) break; udelay(100000); diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index 48d878643b..35dfbbc577 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -55,6 +55,8 @@ enum { RAM_DDR2_64 = 2, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -79,10 +81,9 @@ static unsigned int get_mc2_present(void) static void print_fpga_info(unsigned dev) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_rs232; @@ -96,6 +97,10 @@ static void print_fpga_info(unsigned dev) printf("FPGA%d: ", dev); + FPGA_GET_REG(dev, versions, &versions); + FPGA_GET_REG(dev, fpga_version, &fpga_version); + FPGA_GET_REG(dev, fpga_features, &fpga_features); + hardware_version = versions & 0x000f; if (fpga_state @@ -247,8 +252,9 @@ int checkboard(void) int last_stage_init(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); + u16 versions; + + FPGA_GET_REG(0, versions, &versions); print_fpga_info(0); if (get_mc2_present()) diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index eee9ba0aaa..03d796cdb8 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -37,6 +37,8 @@ enum { HWVER_122 = 3, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -101,15 +103,18 @@ int checkboard(void) static void print_fpga_info(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; @@ -163,7 +168,6 @@ static void print_fpga_info(void) */ int last_stage_init(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; print_fpga_info(); @@ -175,7 +179,7 @@ int last_stage_init(void) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ - out_le16(&fpga->quad_serdes_reset, 0); + FPGA_SET_REG(0, quad_serdes_reset, 0); return 0; } diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index c728bc7b73..1af5245c8a 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -53,6 +53,8 @@ enum { RAM_DDR2_32 = 0, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + /* * Check Board Identity: */ @@ -76,10 +78,9 @@ int checkboard(void) static void print_fpga_info(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_compression; @@ -90,6 +91,10 @@ static void print_fpga_info(void) unsigned feature_carriers; unsigned feature_video_channels; + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_compression = (fpga_features & 0xe000) >> 13; @@ -211,20 +216,25 @@ int last_stage_init(void) /* * provide access to fpga gpios (for I2C bitbang) + * (these may look all too simple but make iocon.h much more readable) */ void fpga_gpio_set(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin); + FPGA_SET_REG(0, gpio.set, pin); } void fpga_gpio_clear(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin); + FPGA_SET_REG(0, gpio.clear, pin); } int fpga_gpio_get(int pin) { - return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; + u16 val; + + FPGA_GET_REG(0, gpio.read, &val); + + return val & pin; } void gd405ep_init(void) diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c index bca78032f8..ff0edb2547 100644 --- a/board/gdsys/405ep/neo.c +++ b/board/gdsys/405ep/neo.c @@ -28,6 +28,8 @@ enum { HWVER_300 = 3, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -54,10 +56,9 @@ int checkboard(void) static void print_fpga_info(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; int fpga_state = get_fpga_state(0); unsigned unit_type; unsigned hardware_version; @@ -74,6 +75,10 @@ static void print_fpga_info(void) return; } + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c index 32e24c08cb..c1a583ffbe 100644 --- a/board/gdsys/405ex/405ex.c +++ b/board/gdsys/405ex/405ex.c @@ -11,6 +11,12 @@ #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + DECLARE_GLOBAL_DATA_PTR; int get_fpga_state(unsigned dev) @@ -220,23 +226,17 @@ int board_early_init_r(void) gd405ex_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - struct ihs_fpga *fpga = - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI - u16 *reflection_target = &fpga->reflection_low; -#else - u16 *reflection_target = &fpga->reflection_high; -#endif /* * wait for fpga out of reset */ ctr = 0; while (1) { - out_le16(&fpga->reflection_low, - REFLECTION_TESTPATTERN); + u16 val; - if (in_le16(reflection_target) == - REFLECTION_TESTPATTERN_INV) + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) break; udelay(100000); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index fa8961a351..2f8e306261 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -51,6 +51,8 @@ enum { HWVER_110 = 1, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + static inline void blank_string(int size) { int i; @@ -84,10 +86,9 @@ int misc_init_r(void) static void print_fpga_info(unsigned dev) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; int fpga_state = get_fpga_state(dev); unsigned unit_type; @@ -95,6 +96,10 @@ static void print_fpga_info(unsigned dev) unsigned feature_channels; unsigned feature_expansion; + FPGA_GET_REG(dev, versions, &versions); + FPGA_GET_REG(dev, fpga_version, &fpga_version); + FPGA_GET_REG(dev, fpga_features, &fpga_features); + printf("FPGA%d: ", dev); if (fpga_state & FPGA_STATE_PLATFORM) printf("(legacy) "); @@ -226,8 +231,6 @@ int last_stage_init(void) { unsigned int k; unsigned int fpga; - struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1); int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; @@ -265,17 +268,16 @@ int last_stage_init(void) /* take fpga serdes blocks out of reset */ puts(str_serdes); udelay(500000); - out_le16(&fpga0->quad_serdes_reset, 0); - out_le16(&fpga1->quad_serdes_reset, 0); + FPGA_SET_REG(0, quad_serdes_reset, 0); + FPGA_SET_REG(1, quad_serdes_reset, 0); blank_string(strlen(str_serdes)); /* take channels out of reset */ puts(str_channels); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; for (k = 0; k < 32; ++k) - out_le16(ch0_config_int + 4 * k, 0); + FPGA_SET_REG(fpga, ch[k].config_int, 0); } blank_string(strlen(str_channels)); @@ -283,16 +285,16 @@ int last_stage_init(void) puts(str_locks); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; for (k = 0; k < 32; ++k) { - u16 status = in_le16(ch0_status_int + 4*k); + u16 status; + FPGA_GET_REG(k, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); } /* reset events */ - out_le16(ch0_status_int + 4*k, status); + FPGA_SET_REG(fpga, ch[k].status_int, 0); } } blank_string(strlen(str_locks)); @@ -300,14 +302,14 @@ int last_stage_init(void) /* verify hicb_status */ puts(str_hicb); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; for (k = 0; k < 32; ++k) { - u16 status = in_le16(ch0_hicb_status_int + 4*k); + u16 status; + FPGA_GET_REG(k, hicb_ch[k].status_int, &status); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); /* reset events */ - out_le16(ch0_hicb_status_int + 4*k, status); + FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); } } blank_string(strlen(str_hicb)); diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 43e6a4cdef..60b16048b9 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -13,6 +13,8 @@ endif LIB = $(obj)lib$(VENDOR).o +COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o + COBJS-$(CONFIG_IO) += miiphybb.o COBJS-$(CONFIG_IO64) += miiphybb.o COBJS-$(CONFIG_IOCON) += osd.o diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c new file mode 100644 index 0000000000..e3af6cb54f --- /dev/null +++ b/board/gdsys/common/fpga.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2013 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + out_le16(reg, data); + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + *data = in_le16(reg); + + return 0; +} diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 45cea5eaaf..fd84388f89 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -6,8 +6,8 @@ */ #include -#include #include +#include #include @@ -54,34 +54,41 @@ enum { #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_i2c *i2c = &fpga->i2c; + u16 val; - while (in_le16(&fpga->extended_interrupt) & (1 << 12)) - ; - out_le16(&i2c->write_mailbox_ext, reg | (data << 8)); - out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1)); + do { + FPGA_GET_REG(screen, extended_interrupt, &val); + } while (val & (1 << 12)); + + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); } static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_i2c *i2c = &fpga->i2c; unsigned int ctr = 0; + u16 val; - while (in_le16(&fpga->extended_interrupt) & (1 << 12)) - ; - out_le16(&fpga->extended_interrupt, 1 << 14); - out_le16(&i2c->write_mailbox_ext, reg); - out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1)); - while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) { + do { + FPGA_GET_REG(screen, extended_interrupt, &val); + } while (val & (1 << 12)); + + FPGA_SET_REG(screen, extended_interrupt, 1 << 14); + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); + + FPGA_GET_REG(screen, extended_interrupt, &val); + while (!(val & (1 << 14))) { udelay(100000); if (ctr++ > 5) { printf("iic receive timeout\n"); break; } + FPGA_GET_REG(screen, extended_interrupt, &val); } - return in_le16(&i2c->read_mailbox_ext) >> 8; + + FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); + return val >> 8; } #endif @@ -113,7 +120,6 @@ static void mpc92469ac_calc_parameters(unsigned int fout, static void mpc92469ac_set(unsigned screen, unsigned int fout) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); unsigned int n; unsigned int m; unsigned int bitval = 0; @@ -134,7 +140,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) break; } - out_le16(&fpga->mpc3w_control, (bitval << 9) | m); + FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); } #endif @@ -249,14 +255,12 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) static int osd_write_videomem(unsigned screen, unsigned offset, u16 *data, size_t charcount) { - struct ihs_fpga *fpga = - (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen); unsigned int k; for (k = 0; k < charcount; ++k) { if (offset + k >= BUFSIZE) return -1; - out_le16(&fpga->videomem + offset + k, data[k]); + FPGA_SET_REG(screen, videomem[offset + k], data[k]); } return charcount; @@ -302,14 +306,15 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int osd_probe(unsigned screen) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_osd *osd = &fpga->osd; - u16 version = in_le16(&osd->version); - u16 features = in_le16(&osd->features); + u16 version; + u16 features; unsigned width; unsigned height; u8 value; + FPGA_GET_REG(0, osd.version, &version); + FPGA_GET_REG(0, osd.features, &features); + width = ((features & 0x3f00) >> 8) + 1; height = (features & 0x001f) + 1; @@ -356,12 +361,13 @@ int osd_probe(unsigned screen) fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); #endif - out_le16(&fpga->videocontrol, 0x0002); - out_le16(&osd->control, 0x0049); + FPGA_SET_REG(screen, videocontrol, 0x0002); + FPGA_SET_REG(screen, osd.control, 0x0049); + + FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); + FPGA_SET_REG(screen, osd.x_pos, 0x007f); + FPGA_SET_REG(screen, osd.y_pos, 0x005f); - out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1)); - out_le16(&osd->x_pos, 0x007f); - out_le16(&osd->y_pos, 0x005f); return 0; } diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 17391cddc9..d4011a1e8a 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -123,6 +123,12 @@ #define CONFIG_SYS_FPGA_COUNT 2 +#define CONFIG_SYS_FPGA_PTR { \ + (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ + (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } + +#define CONFIG_SYS_FPGA_COMMON + #define CONFIG_SYS_LATCH0_RESET 0xffff #define CONFIG_SYS_LATCH0_BOOT 0xffff #define CONFIG_SYS_LATCH1_RESET 0xffcf diff --git a/include/configs/io.h b/include/configs/io.h index 33743e61ac..27d1b0f0a1 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -230,6 +230,11 @@ #define CONFIG_SYS_FPGA_COUNT 1 +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } + +#define CONFIG_SYS_FPGA_COMMON + /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 #define CONFIG_SYS_EBC_PB3AP 0xa2015480 diff --git a/include/configs/io64.h b/include/configs/io64.h index dcd1b82e25..f110b70602 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -498,6 +498,12 @@ #define CONFIG_SYS_FPGA_COUNT 2 +#define CONFIG_SYS_FPGA_PTR { \ + (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ + (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } + +#define CONFIG_SYS_FPGA_COMMON + #define CONFIG_SYS_LATCH0_RESET 0xffff #define CONFIG_SYS_LATCH0_BOOT 0xffff #define CONFIG_SYS_LATCH1_RESET 0xffbf diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 32d9050adb..67a7ab9ee3 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -236,6 +236,11 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_FPGA_COUNT 1 +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } + +#define CONFIG_SYS_FPGA_COMMON + /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 #define CONFIG_SYS_EBC_PB3AP 0x02025080 diff --git a/include/configs/neo.h b/include/configs/neo.h index 5abb8b1a75..91871f718f 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -222,6 +222,11 @@ #define CONFIG_SYS_FPGA_COUNT 1 +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } + +#define CONFIG_SYS_FPGA_COMMON + /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 #define CONFIG_SYS_EBC_PB3AP 0x92015480 diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 0a8268cbb5..8b895457bd 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -19,6 +19,23 @@ enum { int get_fpga_state(unsigned dev); void print_fpga_state(unsigned dev); +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); + +extern struct ihs_fpga *fpga_ptr[]; + +#define FPGA_SET_REG(ix, fld, val) \ + fpga_set_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) + +#define FPGA_GET_REG(ix, fld, val) \ + fpga_get_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) + struct ihs_gpio { u16 read; u16 clear; @@ -67,6 +84,19 @@ struct ihs_fpga { #endif #ifdef CONFIG_IO64 + +struct ihs_fpga_channel { + u16 status_int; + u16 config_int; + u16 switch_connect_config; + u16 tx_destination; +}; + +struct ihs_fpga_hicb { + u16 status_int; + u16 config_int; +}; + struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ @@ -75,12 +105,9 @@ struct ihs_fpga { u16 reserved_0[5]; /* 0x0008 */ u16 quad_serdes_reset; /* 0x0012 */ u16 reserved_1[502]; /* 0x0014 */ - u16 ch0_status_int; /* 0x0400 */ - u16 ch0_config_int; /* 0x0402 */ - u16 reserved_2[126]; /* 0x0404 */ - u16 ch0_hicb_status_int;/* 0x0500 */ - u16 ch0_hicb_config_int;/* 0x0502 */ - u16 reserved_3[7549]; /* 0x0504 */ + struct ihs_fpga_channel ch[32]; /* 0x0400 */ + struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ + u16 reserved_2[7487]; /* 0x0580 */ u16 reflection_high; /* 0x3ffe */ }; #endif @@ -100,7 +127,7 @@ struct ihs_fpga { u16 reflection_high; /* 0x00fe */ struct ihs_osd osd; /* 0x0100 */ u16 reserved_3[889]; /* 0x010e */ - u16 videomem; /* 0x0800 */ + u16 videomem[31736]; /* 0x0800 */ }; #endif @@ -121,7 +148,7 @@ struct ihs_fpga { u16 reserved_4[176]; /* 0x00a0 */ struct ihs_osd osd; /* 0x0200 */ u16 reserved_5[761]; /* 0x020e */ - u16 videomem; /* 0x0800 */ + u16 videomem[31736]; /* 0x0800 */ }; #endif From 049de79d85dda8933092185f705731fa75f9b275 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 26 Jun 2013 16:04:27 +0200 Subject: [PATCH 2/6] powerpc/ppc4xx: Add gdsys mclink interface mclink is a serial interface for communication between gdsys FPGA. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/common/mclink.c | 153 ++++++++++++++++++++++++++++++++++++ board/gdsys/common/mclink.h | 31 ++++++++ 2 files changed, 184 insertions(+) create mode 100644 board/gdsys/common/mclink.c create mode 100644 board/gdsys/common/mclink.h diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c new file mode 100644 index 0000000000..e0382a3808 --- /dev/null +++ b/board/gdsys/common/mclink.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +enum { + MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7, + MCINT_TX_ERROR_EV = 1 << 9, + MCINT_TX_BUFFER_FREE = 1 << 10, + MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11, + MCINT_RX_ERROR_EV = 1 << 13, + MCINT_RX_CONTENT_AVAILABLE = 1 << 14, + MCINT_RX_PACKET_RECEIVED_EV = 1 << 15, +}; + +int mclink_probe(void) +{ + unsigned int k; + int slaves = 0; + + for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) { + int timeout = 0; + unsigned int ctr = 0; + u16 mc_status; + + FPGA_GET_REG(k, mc_status, &mc_status); + + if (!(mc_status & (1 << 15))) + break; + + FPGA_SET_REG(k, mc_control, 0x8000); + + FPGA_GET_REG(k, mc_status, &mc_status); + while (!(mc_status & (1 << 14))) { + udelay(100); + if (ctr++ > 500) { + timeout = 1; + break; + } + FPGA_GET_REG(k, mc_status, &mc_status); + } + if (timeout) + break; + + printf("waited %d us for mclink %d to come up\n", ctr * 100, k); + + slaves++; + } + + return slaves; +} + +int mclink_send(u8 slave, u16 addr, u16 data) +{ + unsigned int ctr = 0; + u16 int_status; + u16 rx_cmd_status; + u16 rx_cmd; + + /* reset interrupt status */ + FPGA_GET_REG(0, mc_int, &int_status); + FPGA_SET_REG(0, mc_int, int_status); + + /* send */ + FPGA_SET_REG(0, mc_tx_address, addr); + FPGA_SET_REG(0, mc_tx_data, data); + FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); + FPGA_SET_REG(0, mc_control, 0x8001); + + /* wait for reply */ + FPGA_GET_REG(0, mc_int, &int_status); + while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { + udelay(100); + if (ctr++ > 3) + return -ETIMEDOUT; + FPGA_GET_REG(0, mc_int, &int_status); + } + + FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); + rx_cmd = (rx_cmd_status >> 12) & 0x03; + if (rx_cmd != 0) + printf("mclink_send: received cmd %d, expected %d\n", rx_cmd, + 0); + + return 0; +} + +int mclink_receive(u8 slave, u16 addr, u16 *data) +{ + u16 rx_cmd_status; + u16 rx_cmd; + u16 int_status; + unsigned int ctr = 0; + + /* send read request */ + FPGA_SET_REG(0, mc_tx_address, addr); + FPGA_SET_REG(0, mc_tx_cmd, + ((slave & 0x03) << 14) | (1 << 12) | (1 << 0)); + FPGA_SET_REG(0, mc_control, 0x8001); + + + /* wait for reply */ + FPGA_GET_REG(0, mc_int, &int_status); + while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { + udelay(100); + if (ctr++ > 3) + return -ETIMEDOUT; + FPGA_GET_REG(0, mc_int, &int_status); + } + + /* check reply */ + FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); + if ((rx_cmd_status >> 14) != slave) { + printf("mclink_receive: reply from slave %d, expected %d\n", + rx_cmd_status >> 14, slave); + return -EINVAL; + } + + rx_cmd = (rx_cmd_status >> 12) & 0x03; + if (rx_cmd != 1) { + printf("mclink_send: received cmd %d, expected %d\n", + rx_cmd, 1); + return -EIO; + } + + FPGA_GET_REG(0, mc_rx_data, data); + + return 0; +} diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h new file mode 100644 index 0000000000..47a62b4fcc --- /dev/null +++ b/board/gdsys/common/mclink.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MCLINK_H_ +#define _MCLINK_H_ + +int mclink_probe(void); +int mclink_send(u8 slave, u16 addr, u16 data); +int mclink_receive(u8 slave, u16 addr, u16 *data); + +#endif From 869b550ea31b0b12e863203e1e22d4433ebad287 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 26 Jun 2013 16:04:28 +0200 Subject: [PATCH 3/6] powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- common/Makefile | 1 + common/cmd_fpgad.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 common/cmd_fpgad.c diff --git a/common/Makefile b/common/Makefile index 87ba82e204..288690bca5 100644 --- a/common/Makefile +++ b/common/Makefile @@ -92,6 +92,7 @@ COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o endif +COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o diff --git a/common/cmd_fpgad.c b/common/cmd_fpgad.c new file mode 100644 index 0000000000..07536ffdd6 --- /dev/null +++ b/common/cmd_fpgad.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2013 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * based on cmd_mem.c + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +static uint dp_last_fpga; +static uint dp_last_addr; +static uint dp_last_length = 0x40; + +/* + * FPGA Memory Display + * + * Syntax: + * fpgad {fpga} {addr} {len} + */ +#define DISP_LINE_LEN 16 +int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int k; + unsigned int fpga; + ulong addr, length; + int rc = 0; + u16 linebuf[DISP_LINE_LEN/sizeof(u16)]; + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + fpga = dp_last_fpga; + addr = dp_last_addr; + length = dp_last_length; + + if (argc < 3) + return CMD_RET_USAGE; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* + * FPGA is specified since argc > 2 + */ + fpga = simple_strtoul(argv[1], NULL, 16); + + /* + * Address is specified since argc > 2 + */ + addr = simple_strtoul(argv[2], NULL, 16); + + /* + * If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if (argc > 3) + length = simple_strtoul(argv[3], NULL, 16); + } + + /* Print the lines. */ + for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k) + fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16), + &linebuf[k]); + print_buffer(addr, (void *)linebuf, sizeof(u16), + length, DISP_LINE_LEN / sizeof(u16)); + addr += sizeof(u16)*length; + + dp_last_fpga = fpga; + dp_last_addr = addr; + dp_last_length = length; + return rc; +} + +U_BOOT_CMD( + fpgad, 4, 1, do_fpga_md, + "fpga register display", + "fpga address [# of objects]" +); From e50e8968d994491a426116c3ed6b3e7e26e45f3a Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 25 Jul 2013 19:28:13 +0200 Subject: [PATCH 4/6] powerpc/ppc4xx: Support gdsys multichannel iocon hardware Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/405ep/iocon.c | 464 +++++++++++++++++++++++++++++++++--- board/gdsys/common/Makefile | 2 +- board/gdsys/common/osd.c | 20 +- include/configs/iocon.h | 58 ++++- include/gdsys_fpga.h | 15 +- 5 files changed, 508 insertions(+), 51 deletions(-) diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 1af5245c8a..9f84fb1869 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,15 @@ #include #include "../common/osd.h" +#include "../common/mclink.h" + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) @@ -31,11 +41,20 @@ enum { HWVER_100 = 0, HWVER_104 = 1, HWVER_110 = 2, + HWVER_120 = 3, + HWVER_200 = 4, + HWVER_210 = 5, +}; + +enum { + FPGA_HWVER_200 = 0, + FPGA_HWVER_210 = 1, }; enum { COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA, + COMPRESSION_TYPE1_DELTA = 1, + COMPRESSION_TYPE1_TYPE2_DELTA = 3, }; enum { @@ -51,10 +70,71 @@ enum { enum { RAM_DDR2_32 = 0, + RAM_DDR3_32 = 1, }; +enum { + MCFPGA_DONE = 1 << 0, + MCFPGA_INIT_N = 1 << 1, + MCFPGA_PROGRAM_N = 1 << 2, + MCFPGA_UPDATE_ENABLE_N = 1 << 3, + MCFPGA_RESET_N = 1 << 4, +}; + +enum { + GPIO_MDC = 1 << 14, + GPIO_MDIO = 1 << 15, +}; + +unsigned int mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; +static int setup_88e1518(const char *bus, unsigned char addr); +static int verify_88e1518(const char *bus, unsigned char addr); + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + int res; + + switch (fpga) { + case 0: + out_le16(reg, data); + break; + default: + res = mclink_send(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_send reg %02lx data %04x returned %d\n", + regoff, data, res); + return res; + } + break; + } + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + int res; + + switch (fpga) { + case 0: + *data = in_le16(reg); + break; + default: + if (fpga > mclink_fpgacount) + return -EINVAL; + res = mclink_receive(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_receive reg %02lx returned %d\n", + regoff, res); + return res; + } + } + + return 0; +} + /* * Check Board Identity: */ @@ -76,7 +156,7 @@ int checkboard(void) return 0; } -static void print_fpga_info(void) +static void print_fpga_info(unsigned int fpga) { u16 versions; u16 fpga_version; @@ -90,13 +170,13 @@ static void print_fpga_info(void) unsigned feature_ramconfig; unsigned feature_carriers; unsigned feature_video_channels; + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; FPGA_GET_REG(0, versions, &versions); FPGA_GET_REG(0, fpga_version, &fpga_version); FPGA_GET_REG(0, fpga_features, &fpga_features); unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; feature_compression = (fpga_features & 0xe000) >> 13; feature_osd = fpga_features & (1<<11); feature_audio = (fpga_features & 0x0600) >> 9; @@ -105,6 +185,9 @@ static void print_fpga_info(void) feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; + if (legacy) + printf("legacy "); + switch (unit_type) { case UNITTYPE_MAIN_USER: printf("Mainchannel"); @@ -119,27 +202,68 @@ static void print_fpga_info(void) break; } - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; + if (unit_type == UNITTYPE_MAIN_USER) { + if (legacy) + hardware_version = + (in_le16((void *)LATCH2_BASE)>>8) & 0x0f; + else + hardware_version = + (!!pca9698_get_value(0x20, 24) << 0) + | (!!pca9698_get_value(0x20, 25) << 1) + | (!!pca9698_get_value(0x20, 26) << 2) + | (!!pca9698_get_value(0x20, 27) << 3); + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00,"); + break; - case HWVER_104: - printf(" HW-Ver 1.04\n"); - break; + case HWVER_104: + printf(" HW-Ver 1.04,"); + break; - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; + case HWVER_110: + printf(" HW-Ver 1.10,"); + break; - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; + case HWVER_120: + printf(" HW-Ver 1.20-1.21,"); + break; + + case HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } } - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); + if (unit_type == UNITTYPE_VIDEO_USER) { + hardware_version = versions & 0x000f; + switch (hardware_version) { + case FPGA_HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case FPGA_HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + } + + printf(" FPGA V %d.%02d\n features:", + fpga_version / 100, fpga_version % 100); switch (feature_compression) { @@ -151,6 +275,10 @@ static void print_fpga_info(void) printf(" type1-deltacompression"); break; + case COMPRESSION_TYPE1_TYPE2_DELTA: + printf(" type1-deltacompression, type2-inlinecompression"); + break; + default: printf(" compression %d(not supported)", feature_compression); break; @@ -197,6 +325,10 @@ static void print_fpga_info(void) printf(", RAM 32 bit DDR2"); break; + case RAM_DDR3_32: + printf(", RAM 32 bit DDR3"); + break; + default: printf(", RAM %d(not supported)", feature_ramconfig); break; @@ -209,46 +341,117 @@ static void print_fpga_info(void) int last_stage_init(void) { - print_fpga_info(); + int slaves; + unsigned int k; + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - return osd_probe(0); + print_fpga_info(0); + osd_probe(0); + + /* wait for FPGA done */ + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + unsigned int ctr = 0; + + if (i2c_probe(mclink_controllers[k])) + continue; + + while (!(pca953x_get_val(mclink_controllers[k]) + & MCFPGA_DONE)) { + udelay(100000); + if (ctr++ > 5) { + printf("no done for mclink_controller %d\n", k); + break; + } + } + } + + if (!legacy) { + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, + bb_miiphy_write); + if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) { + printf("Fixup 88e1518 erratum on %s\n", + bb_miiphy_buses[0].name); + setup_88e1518(bb_miiphy_buses[0].name, 0); + } + } + + /* wait for slave-PLLs to be up and running */ + udelay(500000); + + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; + slaves = mclink_probe(); + mclink_fpgacount = 0; + + if (slaves <= 0) + return 0; + + mclink_fpgacount = slaves; + + for (k = 1; k <= slaves; ++k) { + print_fpga_info(k); + osd_probe(k); + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); + if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) { + printf("Fixup 88e1518 erratum on %s\n", + bb_miiphy_buses[k].name); + setup_88e1518(bb_miiphy_buses[k].name, 0); + } + } + + return 0; } /* * provide access to fpga gpios (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(int pin) +void fpga_gpio_set(unsigned int bus, int pin) { - FPGA_SET_REG(0, gpio.set, pin); + FPGA_SET_REG(bus, gpio.set, pin); } -void fpga_gpio_clear(int pin) +void fpga_gpio_clear(unsigned int bus, int pin) { - FPGA_SET_REG(0, gpio.clear, pin); + FPGA_SET_REG(bus, gpio.clear, pin); } -int fpga_gpio_get(int pin) +int fpga_gpio_get(unsigned int bus, int pin) { u16 val; - FPGA_GET_REG(0, gpio.read, &val); + FPGA_GET_REG(bus, gpio.read, &val); return val & pin; } void gd405ep_init(void) { + unsigned int k; + + if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */ + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; + } else { + pca9698_direction_output(0x20, 4, 1); + } } void gd405ep_set_fpga_reset(unsigned state) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) { + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + pca9698_set_value(0x20, 4, state ? 0 : 1); } } @@ -263,5 +466,200 @@ void gd405ep_setup_hw(void) int gd405ep_get_fpga_done(unsigned fpga) { - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) + return in_le16((void *)LATCH2_BASE) + & CONFIG_SYS_FPGA_DONE(fpga); + else + return pca9698_get_value(0x20, 20); +} + +/* + * FPGA MII bitbang implementation + */ + +struct fpga_mii { + unsigned fpga; + int mdio; +} fpga_mii[] = { + { 0, 1}, + { 1, 1}, + { 2, 1}, + { 3, 1}, +}; + +static int mii_dummy_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (fpga_mii->mdio) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + fpga_mii->mdio = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + u16 gpio; + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); + + *v = ((gpio & GPIO_MDIO) != 0); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "trans1", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[0], + }, + { + .name = "trans2", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[1], + }, + { + .name = "trans3", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[2], + }, + { + .name = "trans4", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[3], + }, +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); + +/* + * Workaround for erratum mentioned in 88E1518 release notes + */ + +static int verify_88e1518(const char *bus, unsigned char addr) +{ + u16 phy_id1, phy_id2; + + if (miiphy_read(bus, addr, 2, &phy_id1) || + miiphy_read(bus, addr, 3, &phy_id2)) { + printf("Error reading from the PHY addr=%02x\n", addr); + return -EIO; + } + + if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0)) + return -EINVAL; + + return 0; +} + +struct regfix_88e1518 { + u8 reg; + u16 data; +} regfix_88e1518[] = { + { 22, 0x00ff }, + { 17, 0x214b }, + { 16, 0x2144 }, + { 17, 0x0c28 }, + { 16, 0x2146 }, + { 17, 0xb233 }, + { 16, 0x214d }, + { 17, 0xcc0c }, + { 16, 0x2159 }, + { 22, 0x00fb }, + { 7, 0xc00d }, + { 22, 0x0000 }, +}; + +static int setup_88e1518(const char *bus, unsigned char addr) +{ + unsigned int k; + + for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) { + if (miiphy_write(bus, addr, + regfix_88e1518[k].reg, + regfix_88e1518[k].data)) { + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; + } + } + + return 0; } diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 60b16048b9..216ad964af 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -17,7 +17,7 @@ COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o COBJS-$(CONFIG_IO) += miiphybb.o COBJS-$(CONFIG_IO64) += miiphybb.o -COBJS-$(CONFIG_IOCON) += osd.o +COBJS-$(CONFIG_IOCON) += osd.o mclink.o COBJS-$(CONFIG_DLVISION_10G) += osd.o COBJS-$(CONFIG_CONTROLCENTERD) += dp501.o diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index fd84388f89..354bf0b6e0 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -6,8 +6,8 @@ */ #include -#include #include +#include #include @@ -51,6 +51,12 @@ enum { CH7301_DSP = 0x56, /* DVI Sync polarity Register */ }; +unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; + +#ifdef CONFIG_SYS_CH7301 +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#endif + #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) { @@ -270,7 +276,7 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { + for (screen = 0; screen <= max_osd_screen; ++screen) { unsigned x; unsigned y; unsigned charcount; @@ -311,6 +317,9 @@ int osd_probe(unsigned screen) unsigned width; unsigned height; u8 value; +#ifdef CONFIG_SYS_CH7301 + int old_bus = i2c_get_bus_num(); +#endif FPGA_GET_REG(0, osd.version, &version); FPGA_GET_REG(0, osd.features, &features); @@ -322,9 +331,11 @@ int osd_probe(unsigned screen) screen, version/100, version%100, width, height); #ifdef CONFIG_SYS_CH7301 + i2c_set_bus_num(ch7301_i2c[screen]); value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); if (value != 0x17) { printf(" Probing CH7301 failed, DID %02x\n", value); + i2c_set_bus_num(old_bus); return -1; } i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); @@ -332,6 +343,7 @@ int osd_probe(unsigned screen) i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + i2c_set_bus_num(old_bus); #endif #ifdef CONFIG_SYS_MPC92469AC @@ -368,6 +380,8 @@ int osd_probe(unsigned screen) FPGA_SET_REG(screen, osd.x_pos, 0x007f); FPGA_SET_REG(screen, osd.y_pos, 0x005f); + if (screen > max_osd_screen) + max_osd_screen = screen; return 0; } @@ -376,7 +390,7 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { + for (screen = 0; screen <= max_osd_screen; ++screen) { unsigned x; unsigned y; unsigned k; diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 67a7ab9ee3..9d0d7a10f2 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -63,6 +63,7 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CACHE +#define CONFIG_CMD_FPGAD #undef CONFIG_CMD_EEPROM /* @@ -100,23 +101,53 @@ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 + +#define CONFIG_PCA953X /* NXP PCA9554 */ +#define CONFIG_PCA9698 /* NXP PCA9698 */ + /* * Software (bit-bang) I2C driver configuration */ +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F +#define I2C_SOFT_DECLARATIONS3 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F +#define I2C_SOFT_DECLARATIONS4 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F + +#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} #ifndef __ASSEMBLY__ -void fpga_gpio_set(int pin); -void fpga_gpio_clear(int pin); -int fpga_gpio_get(int pin); +void fpga_gpio_set(unsigned int bus, int pin); +void fpga_gpio_clear(unsigned int bus, int pin); +int fpga_gpio_get(unsigned int bus, int pin); #endif #define I2C_ACTIVE { } #define I2C_TRISTATE { } -#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0 -#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \ - else fpga_gpio_clear(0x0040) -#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \ - else fpga_gpio_clear(0x0020) +#define I2C_READ \ + (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ + } while (0) #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ /* @@ -236,10 +267,10 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } +#define CONFIG_SYS_MCLINK_MAX 3 -#define CONFIG_SYS_FPGA_COMMON +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 @@ -256,6 +287,9 @@ int fpga_gpio_get(int pin); */ #define CONFIG_SYS_MPC92469AC #define CONFIG_SYS_CH7301 -#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT +#define CONFIG_SYS_OSD_SCREENS 1 + +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI #endif /* __CONFIG_H */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 8b895457bd..f50e0e2733 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -123,10 +123,21 @@ struct ihs_fpga { u16 mpc3w_control; /* 0x001a */ u16 reserved_1[19]; /* 0x001c */ u16 videocontrol; /* 0x0042 */ - u16 reserved_2[93]; /* 0x0044 */ + u16 reserved_2[14]; /* 0x0044 */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_3[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ struct ihs_osd osd; /* 0x0100 */ - u16 reserved_3[889]; /* 0x010e */ + u16 reserved_4[889]; /* 0x010e */ u16 videomem[31736]; /* 0x0800 */ }; #endif From 0f0c1021d86ae2486687bef8b323fd5089575e78 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 26 Jun 2013 16:04:30 +0200 Subject: [PATCH 5/6] powerpc/ppc4xx: Consider gdsys FPGA OSD size OSD size was constant 32x16 characters. Now the size is set as announced by the FPGA. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/common/osd.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 354bf0b6e0..c49cd9a619 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -26,10 +26,6 @@ #define PIXCLK_640_480_60 25180000 -#define BASE_WIDTH 32 -#define BASE_HEIGHT 16 -#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT) - enum { CH7301_CM = 0x1c, /* Clock Mode Register */ CH7301_IC = 0x1d, /* Input Clock Register */ @@ -51,6 +47,11 @@ enum { CH7301_DSP = 0x56, /* DVI Sync polarity Register */ }; +unsigned int base_width; +unsigned int base_height; +size_t bufsize; +u16 *buf; + unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; #ifdef CONFIG_SYS_CH7301 @@ -264,7 +265,7 @@ static int osd_write_videomem(unsigned screen, unsigned offset, unsigned int k; for (k = 0; k < charcount; ++k) { - if (offset + k >= BUFSIZE) + if (offset + k >= bufsize) return -1; FPGA_SET_REG(screen, videomem[offset + k], data[k]); } @@ -283,7 +284,6 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned len; u8 color; unsigned int k; - u16 buf[BUFSIZE]; char *text; int res; @@ -297,12 +297,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) color = simple_strtoul(argv[3], NULL, 16); text = argv[4]; charcount = strlen(text); - len = (charcount > BUFSIZE) ? BUFSIZE : charcount; + len = (charcount > bufsize) ? bufsize : charcount; for (k = 0; k < len; ++k) buf[k] = (text[k] << 8) | color; - res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len); + res = osd_write_videomem(screen, y * base_width + x, buf, len); if (res < 0) return res; } @@ -314,8 +314,6 @@ int osd_probe(unsigned screen) { u16 version; u16 features; - unsigned width; - unsigned height; u8 value; #ifdef CONFIG_SYS_CH7301 int old_bus = i2c_get_bus_num(); @@ -324,11 +322,15 @@ int osd_probe(unsigned screen) FPGA_GET_REG(0, osd.version, &version); FPGA_GET_REG(0, osd.features, &features); - width = ((features & 0x3f00) >> 8) + 1; - height = (features & 0x001f) + 1; + base_width = ((features & 0x3f00) >> 8) + 1; + base_height = (features & 0x001f) + 1; + bufsize = base_width * base_height; + buf = malloc(sizeof(u16) * bufsize); + if (!buf) + return -1; printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", - screen, version/100, version%100, width, height); + screen, version/100, version%100, base_width, base_height); #ifdef CONFIG_SYS_CH7301 i2c_set_bus_num(ch7301_i2c[screen]); @@ -394,7 +396,7 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned x; unsigned y; unsigned k; - u16 buffer[BASE_WIDTH]; + u16 buffer[base_width]; char *rp; u16 *wp = buffer; unsigned count = (argc > 4) ? @@ -419,13 +421,13 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rp += 4; wp++; - if (wp - buffer > BASE_WIDTH) + if (wp - buffer > base_width) break; } for (k = 0; k < count; ++k) { unsigned offset = - y * BASE_WIDTH + x + k * (wp - buffer); + y * base_width + x + k * (wp - buffer); osd_write_videomem(screen, offset, buffer, wp - buffer); } From 28437154649db9f4445b93f278199e34b0447a57 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 26 Jun 2013 16:04:31 +0200 Subject: [PATCH 6/6] powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards CONFIG_SYS_FLASH_PROTECTION was active on most gdsys boards by default, while hardware flash protection was not implemented. Hardware support was added recently and we get into trouble because backward compatibility is broken (u-boot can't unprotect the protected flash after a downgrade). So we decided to disable hardware flash protection for all our boards. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision-10g.h | 3 +-- include/configs/dlvision.h | 3 +-- include/configs/io.h | 3 +-- include/configs/iocon.h | 3 +-- include/configs/neo.h | 3 +-- 5 files changed, 5 insertions(+), 10 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index d4011a1e8a..a03c46295e 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -18,7 +18,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME dlvsion-10g -#define CONFIG_IDENT_STRING " dlvision-10g 0.03" +#define CONFIG_IDENT_STRING " dlvision-10g 0.04" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F @@ -151,7 +151,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 27471284ac..2f8d6b4c90 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -18,7 +18,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME dlvision -#define CONFIG_IDENT_STRING " dlvision 0.01" +#define CONFIG_IDENT_STRING " dlvision 0.02" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ @@ -109,7 +109,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ diff --git a/include/configs/io.h b/include/configs/io.h index 27d1b0f0a1..79ada68ac7 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -18,7 +18,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME io -#define CONFIG_IDENT_STRING " io 0.05" +#define CONFIG_IDENT_STRING " io 0.06" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F @@ -123,7 +123,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 9d0d7a10f2..ec9016a6d1 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -18,7 +18,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME iocon -#define CONFIG_IDENT_STRING " iocon 0.04" +#define CONFIG_IDENT_STRING " iocon 0.05" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F @@ -172,7 +172,6 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ diff --git a/include/configs/neo.h b/include/configs/neo.h index 91871f718f..ccbb1fa9b1 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -19,7 +19,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME neo -#define CONFIG_IDENT_STRING " neo 0.01" +#define CONFIG_IDENT_STRING " neo 0.02" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F @@ -130,7 +130,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */