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MIPS: Malta: Enable CM & L2 support

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Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton
2016-09-21 11:18:56 +01:00
committed by Daniel Schwierzeck
parent 7953354b07
commit 566ce04de4
2 changed files with 2 additions and 6 deletions
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6
board/imgtec/malta/lowlevel_init.S
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@@ -28,12 +28,6 @@
.globl lowlevel_init
lowlevel_init:
/* disable any L2 cache for now */
sync
mfc0 t0, CP0_CONFIG, 2
ori t0, t0, 0x1 << 12
mtc0 t0, CP0_CONFIG, 2
/* detect the core card */
PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
lw t0, 0(t0)