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board/t1040qds: Relax IFC FPGA timings

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Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This commit is contained in:
Prabhakar Kushwaha 2013-12-12 12:09:01 +05:30 committed by York Sun
parent fbe76ae4e3
commit 562de1d6da
1 changed files with 1 additions and 1 deletions
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2
include/configs/T1040QDS.h
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@ -248,7 +248,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f)) FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f)) FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0 #define CONFIG_SYS_CS3_FTIM3 0x0