ARM: add support for LaCie 2Big Network v2
This patch adds support for the LaCie 2Big Network v2 board, based on the Marvell Kirkwood 6281 SoC. Additional information is available at: http://lacie-nas.org/doku.php?id=2big_network_v2 Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This commit is contained in:
Simon Guinot
Albert ARIBAUD
parent
2cb4fade0e
commit
5628fb75d1
@ -651,6 +651,7 @@ Simon Guinot <simon.guinot@sequanux.org>
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inetspace_v2 ARM926EJS (Kirkwood SoC)
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netspace_v2 ARM926EJS (Kirkwood SoC)
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netspace_max_v2 ARM926EJS (Kirkwood SoC)
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net2big_v2 ARM926EJS (Kirkwood SoC)
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Igor Grinberg <grinberg@compulab.co.il>
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49
board/LaCie/net2big_v2/Makefile
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49
board/LaCie/net2big_v2/Makefile
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@ -0,0 +1,49 @@
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := net2big_v2.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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162
board/LaCie/net2big_v2/kwbimage.cfg
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162
board/LaCie/net2big_v2/kwbimage.cfg
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@ -0,0 +1,162 @@
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1B1B1B9B
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000C30 # DDR Configuration register
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# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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DATA 0xFFD01410 0x0000CCCC # DDR Address Control
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# bit1-0: 01, Cs0width=x16
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# bit3-2: 11, Cs0size=1Gb
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# bit5-4: 00, Cs2width=nonexistent
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# bit7-6: 00, Cs1size =nonexistent
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# bit9-8: 00, Cs2width=nonexistent
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# bit11-10: 00, Cs2size =nonexistent
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# bit13-12: 00, Cs3width=nonexistent
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# bit15-14: 00, Cs3size =nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0 required
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DATA 0xFFD01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0 required
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DATA 0xFFD0141C 0x00000662 # DDR Mode
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# bit2-0: 2, BurstLen=2 required
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# bit3: 0, BurstType=0 required
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# bit6-4: 4, CL=5
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# bit7: 0, TestMode=0 normal
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# bit8: 0, DLL reset=0 normal
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# bit11-9: 6, auto-precharge write recovery ????????????
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# bit12: 0, PD must be zero
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# bit31-13: 0 required
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DATA 0xFFD01420 0x00000044 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 1, DDR drive strenght reduced
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# bit2: 1, DDR ODT control lsd enabled
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# bit5-3: 000, required
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# bit6: 1, DDR ODT control msb, enabled
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# bit9-7: 000, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0 required
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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# bit2-0: 111, required
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# bit3 : 1 , MBUS Burst Chop disabled
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# bit6-4: 111, required
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# bit7 : 1 , D2P Latency enabled
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9 : 0 , no half clock cycle addition to dataout
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 1111 required
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# bit31-16: 0 required
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DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
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DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
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# bit3-2: 00, CS0 hit selected
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# bit23-4: ones, required
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# bit31-24: 0x07, Size (i.e. 128MB)
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
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# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
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# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 01, ODT1 active NEVER!
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# bit31-4: zero, required
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DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
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# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
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# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
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# bit11-10:1, DQ_ODTSel. ODT select turned on
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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#bit0=1, enable DDR init upon this register write
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# End of Header extension
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DATA 0x0 0x0
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188
board/LaCie/net2big_v2/net2big_v2.c
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188
board/LaCie/net2big_v2/net2big_v2.c
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@ -0,0 +1,188 @@
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <command.h>
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#include <i2c.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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#include "net2big_v2.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* GPIO configuration */
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kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
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NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP6_SYSRST_OUTn,
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MPP7_GPO, /* Request power-off */
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP13_GPIO, /* Rear power switch (on|auto) */
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MPP14_GPIO, /* USB fuse alarm */
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MPP15_GPIO, /* Rear power switch (auto|off) */
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MPP16_GPIO, /* SATA HDD1 power */
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MPP17_GPIO, /* SATA HDD2 power */
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP24_GPIO, /* USB mode select */
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MPP26_GPIO, /* USB device vbus */
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MPP28_GPIO, /* USB enable host vbus */
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MPP29_GPIO, /* GPIO extension ALE */
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MPP34_GPIO, /* Rear Push button 0=on 1=off */
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MPP35_GPIO, /* Inhibit switch power-off */
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MPP36_GPIO, /* SATA HDD1 presence */
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MPP37_GPIO, /* SATA HDD2 presence */
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MPP40_GPIO, /* eSATA presence */
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MPP44_GPIO, /* GPIO extension (data 0) */
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MPP45_GPIO, /* GPIO extension (data 1) */
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MPP46_GPIO, /* GPIO extension (data 2) */
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MPP47_GPIO, /* GPIO extension (addr 0) */
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MPP48_GPIO, /* GPIO extension (addr 1) */
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MPP49_GPIO, /* GPIO extension (addr 2) */
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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return 0;
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}
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int board_init(void)
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{
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/* Machine number */
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gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
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/* Boot parameters address */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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int misc_init_r(void)
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{
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#ifdef CONFIG_CMD_I2C
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if (!getenv("ethaddr")) {
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ushort version;
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uchar mac[6];
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int ret;
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/* I2C-0 for on-board EEPROM */
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i2c_set_bus_num(0);
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/* Check layout version for EEPROM data */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uchar *) &version, 2);
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if (ret != 0) {
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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version = be16_to_cpu(version);
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if (version < 1 || version > 3) {
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printf("Error: unknown version %d for EEPROM data\n",
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version);
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return -1;
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}
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/* Read Ethernet MAC address from EEPROM */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac, 6);
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if (ret != 0) {
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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eth_setenv_enetaddr("ethaddr", mac);
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}
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#endif /* CONFIG_CMD_I2C */
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return 0;
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}
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void mv_phy_88e1116_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..(%s) could not read PHY dev address\n", __func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) {
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printf("Err..(%s) PHY status read failed\n", __func__);
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return;
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}
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if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) {
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printf("Err..(%s) PHY reset failed\n", __func__);
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return;
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}
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debug("88E1116 Initialized on %s\n", name);
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}
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/* Configure and initialize PHY */
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void reset_phy(void)
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{
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mv_phy_88e1116_init("egiga0");
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}
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/* Return GPIO push button status */
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static int
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do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
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}
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U_BOOT_CMD(button, 1, 1, do_read_push_button,
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"Return GPIO push button status 0=off 1=on", "");
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43
board/LaCie/net2big_v2/net2big_v2.h
Normal file
43
board/LaCie/net2big_v2/net2big_v2.h
Normal file
@ -0,0 +1,43 @@
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NET2BIG_V2_H
|
||||
#define NET2BIG_V2_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define NET2BIG_V2_OE_LOW 0x0600E000
|
||||
#define NET2BIG_V2_OE_HIGH 0x00000134
|
||||
#define NET2BIG_V2_OE_VAL_LOW 0x10030000
|
||||
#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
|
||||
|
||||
/* Buttons */
|
||||
#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* NET2BIG_V2_H */
|
||||
@ -141,6 +141,7 @@ km_kirkwood_pci arm arm926ejs km_arm keymile
|
||||
mgcoge3un arm arm926ejs km_arm keymile kirkwood
|
||||
portl2 arm arm926ejs km_arm keymile kirkwood
|
||||
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2
|
||||
net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood
|
||||
netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_V2
|
||||
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_MAX_V2
|
||||
dreamplug arm arm926ejs - Marvell kirkwood
|
||||
|
||||
161
include/configs/net2big_v2.h
Normal file
161
include/configs/net2big_v2.h
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_NET2BIG_V2_H
|
||||
#define _CONFIG_NET2BIG_V2_H
|
||||
|
||||
/*
|
||||
* Machine number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING " 2Big v2"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 /* SOC Name */
|
||||
#define CONFIG_MACH_NET2BIG_V2 /* Machine type */
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* Core clock definition.
|
||||
*/
|
||||
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
#include "mv-common.h"
|
||||
|
||||
/* Remove or override few declarations from mv-common.h */
|
||||
#undef CONFIG_RBTREE
|
||||
#undef CONFIG_ENV_SPI_MAX_HZ
|
||||
#undef CONFIG_SYS_IDE_MAXBUS
|
||||
#undef CONFIG_SYS_IDE_MAXDEVICE
|
||||
#undef CONFIG_SYS_PROMPT
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1
|
||||
#define CONFIG_SYS_PROMPT "2big2> "
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_NETCONSOLE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_MVSATA_IDE
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable GPI0 support
|
||||
*/
|
||||
#define CONFIG_KIRKWOOD_GPIO
|
||||
|
||||
/*
|
||||
* Enable I2C support
|
||||
*/
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
|
||||
#endif /* CONFIG_CMD_I2C */
|
||||
|
||||
/*
|
||||
* File systems support
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
/*
|
||||
* Use the HUSH parser
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* Console configuration
|
||||
*/
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
/*
|
||||
* Enable device tree support
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
|
||||
#define CONFIG_ENV_ADDR 0x70000
|
||||
#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"dhcp && run netconsole; " \
|
||||
"if run usbload || run diskload; then bootm; fi"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"loadaddr=0x800000\0" \
|
||||
"autoload=no\0" \
|
||||
"netconsole=" \
|
||||
"set stdin $stdin,nc; " \
|
||||
"set stdout $stdout,nc; " \
|
||||
"set stderr $stderr,nc;\0" \
|
||||
"diskload=ide reset && " \
|
||||
"ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
|
||||
"usbload=usb start && " \
|
||||
"fatload usb 0:1 $loadaddr /boot/$bootfile\0"
|
||||
|
||||
#endif /* _CONFIG_NET2BIG_V2_H */
|
||||
Loading…
Reference in New Issue
Block a user