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sh: Remove MigoR board

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This board has not been converted to CONFIG_DM by the deadline of v2020.01
and is missing other conversions which depend on this as well.  Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-10 12:51:21 -05:00
parent 865acad78f
commit 5617351532
8 changed files with 0 additions and 388 deletions
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5
arch/sh/Kconfig
View File

@ -21,10 +21,6 @@ choice
prompt "Target select"
optional
config TARGET_MIGOR
bool "Migo-R"
select CPU_SH4
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
@ -59,7 +55,6 @@ config SYS_CPU
source "arch/sh/lib/Kconfig"
source "board/renesas/MigoR/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
source "board/renesas/sh7752evb/Kconfig"

12
board/renesas/MigoR/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MIGOR
config SYS_BOARD
default "MigoR"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "MigoR"
endif

6
board/renesas/MigoR/MAINTAINERS
View File

@ -1,6 +0,0 @@
MIGOR BOARD
#M: -
S: Maintained
F: board/renesas/MigoR/
F: include/configs/MigoR.h
F: configs/MigoR_defconfig

13
board/renesas/MigoR/Makefile
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@ -1,13 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# Copyright (C) 2007
# Kenati Technologies, Inc.
#
# board/MigoR/Makefile
#
obj-y := migo_r.o
extra-y += lowlevel_init.o

193
board/renesas/MigoR/lowlevel_init.S
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@ -1,193 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007-2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
* Kenati Technologies, Inc.
*
* board/MigoR/lowlevel_init.S
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
write32 CCR_A, CCR_D ! Address of Cache Control Register
! Instruction Cache Invalidate
write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
! TI == TLB Invalidate bit
write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
write16 PFC_PULCR_A, PFC_PULCR_D
write16 PFC_DRVCR_A, PFC_DRVCR_D
write16 SBSCR_A, SBSCR_D
write16 PSCR_A, PSCR_D
write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA507 -> timer_STOP / WDT_CLK = max
write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
! 0x5A00 -> Clear
write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA504 -> timer_STOP / CLK = 500ms
write32 DLLFRQ_A, DLLFRQ_D ! 20080115
! 20080115
write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
! 20080115
write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
! ??
bsc_init:
write32 CMNCR_A, CMNCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS5ABCR_A, CS5ABCR_D
write32 CS5BBCR_A, CS5BBCR_D
write32 CS6ABCR_A, CS6ABCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS4WCR_A, CS4WCR_D
write32 CS5AWCR_A, CS5AWCR_D
write32 CS5BWCR_A, CS5BWCR_D
write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
write32 SDCR_A, SDCR_D
write32 SDWCR_A, SDWCR_D
write32 SDPCR_A, SDPCR_D
write32 RTCOR_A, RTCOR_D
write32 RTCNT_A, RTCNT_D
write32 RTCSR_A, RTCSR_D
write32 RFCR_A, RFCR_D
write8 SDMR3_A, SDMR3_D
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
rts
mov #0, r0
.align 4
CCR_A: .long CCR
MMUCR_A: .long MMUCR
MSTPCR0_A: .long MSTPCR0
MSTPCR2_A: .long MSTPCR2
PFC_PULCR_A: .long PULCR
PFC_DRVCR_A: .long DRVCR
SBSCR_A: .long SBSCR
PSCR_A: .long PSCR
RWTCSR_A: .long RWTCSR
RWTCNT_A: .long RWTCNT
FRQCR_A: .long FRQCR
PLLCR_A: .long PLLCR
DLLFRQ_A: .long DLLFRQ
CCR_D: .long 0x00000800
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
PFC_PULCR_D: .long 0x6000
PFC_DRVCR_D: .long 0x0464
FRQCR_D: .long 0x07033639
PLLCR_D: .long 0x00005000
DLLFRQ_D: .long 0x000004F6
CMNCR_A: .long CMNCR
CMNCR_D: .long 0x0000001B
CS0BCR_A: .long CS0BCR
CS0BCR_D: .long 0x24920400
CS4BCR_A: .long CS4BCR
CS4BCR_D: .long 0x00003400
CS5ABCR_A: .long CS5ABCR
CS5ABCR_D: .long 0x24920400
CS5BBCR_A: .long CS5BBCR
CS5BBCR_D: .long 0x24920400
CS6ABCR_A: .long CS6ABCR
CS6ABCR_D: .long 0x24920400
CS0WCR_A: .long CS0WCR
CS0WCR_D: .long 0x00000380
CS4WCR_A: .long CS4WCR
CS4WCR_D: .long 0x00110080
CS5AWCR_A: .long CS5AWCR
CS5AWCR_D: .long 0x00000300
CS5BWCR_A: .long CS5BWCR
CS5BWCR_D: .long 0x00000300
CS6AWCR_A: .long CS6AWCR
CS6AWCR_D: .long 0x00000300
SDCR_A: .long SBSC_SDCR
SDCR_D: .long 0x80160809
SDWCR_A: .long SBSC_SDWCR
SDWCR_D: .long 0x0014450C
SDPCR_A: .long SBSC_SDPCR
SDPCR_D: .long 0x00000087
RTCOR_A: .long SBSC_RTCOR
RTCNT_A: .long SBSC_RTCNT
RTCNT_D: .long 0xA55A0012
RTCOR_D: .long 0xA55A001C
RTCSR_A: .long SBSC_RTCSR
RFCR_A: .long SBSC_RFCR
RFCR_D: .long 0xA55A0221
RTCSR_D: .long 0xA55A009a
SDMR3_A: .long 0xFE581180
SDMR3_D: .long 0x0
SR_MASK_D: .long 0xEFFFFF0F
.align 2
SBSCR_D: .word 0x0044
PSCR_D: .word 0x0000
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA504
RWTCNT_D: .word 0x5A00

43
board/renesas/MigoR/migo_r.c
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@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
* Kenati Technologies, Inc.
*
* board/MigoR/migo_r.c
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("BOARD: Renesas MigoR\n");
return 0;
}
int board_init(void)
{
return 0;
}
void led_set_state (unsigned short value)
{
}
#ifdef CONFIG_CMD_NET
int board_eth_init(struct bd_info *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

34
configs/MigoR_defconfig
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@ -1,34 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FFC0000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_MIGOR=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_SDRAM=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_SLEEP is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xA0020000
CONFIG_VERSION_VARIABLE=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y

82
include/configs/MigoR.h
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@ -1,82 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas Solutions Migo-R board
*
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef __MIGO_R_H
#define __MIGO_R_H
#define CONFIG_CPU_SH7722 1
#define CONFIG_DISPLAY_BOARDINFO
/* SMC9111 */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0xB0000000)
/* MEMORY */
#define MIGO_R_SDRAM_BASE (0x8C000000)
#define MIGO_R_FLASH_BASE_1 (0xA0000000)
#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
/* SCIF */
#define CONFIG_CONS_SCIF0 1
/* Enable alternate, more extensive, memory test */
/* Scratch address used by the alternate memory test */
/* Enable temporary baudrate change while serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#undef CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
/* ENV setting */
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#endif /* __MIGO_R_H */