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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini
2016-03-22 12:14:27 -04:00
parent a119357c43 6dedcedd64
commit 55926ddd18
33 changed files with 591 additions and 334 deletions
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12
board/freescale/common/vid.c
View File

@@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override)
exit:
if (re_enable)
enable_interrupts();
i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
return ret;
}
@@ -469,7 +472,7 @@ static int print_vdd(void)
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
return -1;
goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
@@ -481,11 +484,14 @@ static int print_vdd(void)
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
return -1;
goto exit;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
exit:
i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
return ret < 0 ? -1 : 0;
return 0;
}
static int do_vdd_override(cmd_tbl_t *cmdtp,

6
board/freescale/ls1043aqds/ls1043aqds.c
View File

@@ -170,8 +170,7 @@ void board_retimer_init(void)
u8 reg;
/* Retimer is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
@@ -219,6 +218,9 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
/* Return the default channel */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
int board_early_init_f(void)

25
board/freescale/ls2080aqds/eth.c
View File

@@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 2:
/* Slot housing a SGMII riser card? */
@@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
bus = mii_dev_for_muxval(EMI1_SLOT2);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
@@ -606,12 +594,6 @@ serdes2:
dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
bus = mii_dev_for_muxval(EMI1_SLOT4);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 5:
break;
@@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
dpmac_info[dpmac_id].phydev = phy_connect(
dpmac_info[dpmac_id].bus,
dpmac_info[dpmac_id].phy_addr,
NULL,
dpmac_info[dpmac_id].enet_if);
phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;

39
board/freescale/ls2080ardb/eth_ls2080rdb.c
View File

@@ -20,42 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
int load_firmware_cortina(struct phy_device *phy_dev)
{
if (phy_dev->drv->config)
return phy_dev->drv->config(phy_dev);
return 0;
}
void load_phy_firmware(void)
{
int i;
u8 phy_addr;
struct phy_device *phy_dev;
struct mii_dev *dev;
phy_interface_t interface;
/*Initialize and upload firmware for all the PHYs*/
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
interface = wriop_get_enet_if(i);
if (interface == PHY_INTERFACE_MODE_XGMII) {
dev = wriop_get_mdio(i);
phy_addr = wriop_get_phy_address(i);
phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
interface);
if (!phy_dev) {
printf("No phydev for phyaddr %d\n", phy_addr);
continue;
}
/*Flash firmware for All CS4340 PHYS */
if (phy_dev->phy_id == PHY_UID_CS4340)
load_firmware_cortina(phy_dev);
}
}
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
@@ -125,9 +89,6 @@ int board_eth_init(bd_t *bis)
}
}
/* Load CORTINA CS4340 PHY firmware */
load_phy_firmware();
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

4
board/freescale/ls2080ardb/ls2080ardb.c
View File

@@ -149,6 +149,7 @@ int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
init_final_memctl_regs();
@@ -170,6 +171,9 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
return 0;
}