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imx: imx8ulp: Add M33 handshake functions

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Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2022-04-06 14:30:08 +08:00 committed by Stefano Babic
parent 8576f1a67a
commit 5579d66e37
3 changed files with 39 additions and 0 deletions
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1
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
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@ -14,6 +14,7 @@
#define CMC0_RBASE 0x28025000
#define MU0_B_BASE_ADDR 0x29220000
#define CMC1_BASE_ADDR 0x29240000
#define SIM1_BASE_ADDR 0x29290000

2
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
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@ -18,4 +18,6 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
int m33_image_handshake(ulong timeout_ms);
#endif

36
arch/arm/mach-imx/imx8ulp/soc.c
View File

@ -26,6 +26,7 @@
#include <dm/uclass-internal.h>
#include <fuse.h>
#include <thermal.h>
#include <linux/iopoll.h>
DECLARE_GLOBAL_DATA_PTR;
@ -137,6 +138,41 @@ enum bt_mode get_boot_mode(void)
return LOW_POWER_BOOT;
}
bool m33_image_booted(void)
{
u32 gp6;
/* DGO_GP6 */
gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
if (gp6 & BIT(5))
return true;
return false;
}
int m33_image_handshake(ulong timeout_ms)
{
u32 fsr;
int ret;
ulong timeout_us = timeout_ms * 1000;
/* enable MU0_MUB clock before access the register of MU0_MUB */
pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
/*
* Wait m33 to set FCR F0 flag of MU0_MUA
* Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA
*/
ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104, fsr, fsr & BIT(0), 10, timeout_us);
if (!ret)
clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0));
return ret;
}
#define CMC_SRS_TAMPER BIT(31)
#define CMC_SRS_SECURITY BIT(30)
#define CMC_SRS_TZWDG BIT(29)