ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -95,6 +95,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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if (step == 2)
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goto step2;
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/* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
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ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
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if (regs->ddr_eor)
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ddr_out32(&ddr->eor, regs->ddr_eor);
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@ -183,7 +186,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
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ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
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ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
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ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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ddr_out32(&ddr->sdram_cfg_2,
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