From 1659156c74fb575d851fc1f43818d232712e776b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 22 Jan 2019 17:28:28 +0530 Subject: [PATCH 01/13] sunxi: amarula_a64_relic: Enable USB host Enable USB host controllers for Amarula A64-Relic board, the respective nodes are already present in DTS. Signed-off-by: Jagan Teki --- configs/amarula_a64_relic_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index f5857cfbb3..2e6011fa45 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -11,5 +11,7 @@ CONFIG_NR_DRAM_BANKS=1 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic" +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y From bb3e5aa2896d69a6fe86861004d7d4e33824efbe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:09 +0000 Subject: [PATCH 02/13] sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- drivers/clk/sunxi/clk_a10.c | 4 ++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a80.c | 4 ++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 6 ++++++ drivers/clk/sunxi/clk_r40.c | 8 ++++++++ drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 11 files changed, 63 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index b00f51af8b..2aa41efe17 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index aa904ce067..87b74e52dc 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_OTG] = GATE(0x060, BIT(0)), [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 854259bf81..1ef2359286 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate a23_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), @@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a38d76cb7c..5bd8b7dccc 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -13,6 +13,10 @@ #include static struct ccu_clk_gate a31_gates[] = { + [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), @@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), + [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), + [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), + [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index a2ba6eefc5..910275fbce 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -13,6 +13,9 @@ #include static const struct ccu_clk_gate a64_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d6dd6a1fa1..d4bfb0a98b 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -13,6 +13,8 @@ #include static const struct ccu_clk_gate a80_gates[] = { + [CLK_BUS_MMC] = GATE(0x580, BIT(8)), + [CLK_BUS_UART0] = GATE(0x594, BIT(16)), [CLK_BUS_UART1] = GATE(0x594, BIT(17)), [CLK_BUS_UART2] = GATE(0x594, BIT(18)), @@ -22,6 +24,8 @@ static const struct ccu_clk_gate a80_gates[] = { }; static const struct ccu_reset a80_resets[] = { + [RST_BUS_MMC] = RESET(0x5a0, BIT(8)), + [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 1ef6ac5b25..b5a555da36 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate a83t_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f82949b3b6..416aec2b89 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate h3_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = { [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), [RST_USB_PHY3] = RESET(0x0cc, BIT(3)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 0da3a40e3d..902612da91 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate h6_gates[] = { + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), @@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = { }; static struct ccu_reset h6_resets[] = { + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), [RST_BUS_UART0] = RESET(0x90c, BIT(16)), [RST_BUS_UART1] = RESET(0x90c, BIT(17)), [RST_BUS_UART2] = RESET(0x90c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index fd7aae97ea..b9457e1971 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -13,6 +13,10 @@ #include static struct ccu_clk_gate r40_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), [CLK_BUS_OTG] = GATE(0x060, BIT(25)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 25ad87500e..c8a9027889 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), @@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = { static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), From e0c7ce7e52b73a1eeb3568b8a6bbcc7f189bb389 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:10 +0000 Subject: [PATCH 03/13] sunxi: clk: A80: add MMC clock support The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d4bfb0a98b..aec1d80c46 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -34,19 +34,45 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_UART5] = RESET(0x5b4, BIT(21)), }; +static const struct ccu_clk_gate a80_mmc_gates[] = { + [0] = GATE(0x0, BIT(16)), + [1] = GATE(0x4, BIT(16)), + [2] = GATE(0x8, BIT(16)), + [3] = GATE(0xc, BIT(16)), +}; + +static const struct ccu_reset a80_mmc_resets[] = { + [0] = GATE(0x0, BIT(18)), + [1] = GATE(0x4, BIT(18)), + [2] = GATE(0x8, BIT(18)), + [3] = GATE(0xc, BIT(18)), +}; + static const struct ccu_desc a80_ccu_desc = { .gates = a80_gates, .resets = a80_resets, }; +static const struct ccu_desc a80_mmc_clk_desc = { + .gates = a80_mmc_gates, + .resets = a80_mmc_resets, +}; + static int a80_clk_bind(struct udevice *dev) { - return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets)); + ulong count = ARRAY_SIZE(a80_resets); + + if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk")) + count = ARRAY_SIZE(a80_mmc_resets); + + return sunxi_reset_bind(dev, count); } static const struct udevice_id a80_ccu_ids[] = { { .compatible = "allwinner,sun9i-a80-ccu", .data = (ulong)&a80_ccu_desc }, + { .compatible = "allwinner,sun9i-a80-mmc-config-clk", + .data = (ulong)&a80_mmc_clk_desc }, { } }; From a1925a64d5e48ab9a8639b30028e90006d73d2b3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Jan 2019 15:54:11 +0000 Subject: [PATCH 04/13] mmc: sunxi: Add remaining compatible strings Add MMC compatible strings for A83T, A64, H5. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 302332bf97..1259e627cc 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -693,6 +693,18 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun7i-a20-mmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun8i-a83t-emmc", + .data = (ulong)&sun4i_a10_variant, + }, + { + .compatible = "allwinner,sun50i-a64-mmc", + .data = (ulong)&sun4i_a10_variant, + }, + { + .compatible = "allwinner,sun50i-a64-emmc", + .data = (ulong)&sun4i_a10_variant, + }, { /* sentinel */ } }; From 9e23338268d40d162a44d5c5d0ec71c209ccabf6 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Jan 2019 15:54:12 +0000 Subject: [PATCH 05/13] mmc: sunxi: Add DM_MMC support for H6 Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset. Connect that with the respective compatible string. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1259e627cc..1e13a0665d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, }; +static const struct sunxi_mmc_variant sun50i_h6_variant = { + .mclk_offset = 0x830, +}; + static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -705,6 +709,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun50i-a64-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun50i-h6-mmc", + .data = (ulong)&sun50i_h6_variant, + }, + { + .compatible = "allwinner,sun50i-h6-emmc", + .data = (ulong)&sun50i_h6_variant, + }, { /* sentinel */ } }; From 3c8c7da6fcf37ee1da4a450735f6a74291d87a6e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 21 Jan 2019 16:01:12 +0530 Subject: [PATCH 06/13] mmc: sunxi: Add DM_MMC support for A80 A80 gates clock already be part of CLK framework, so just add mod_clk offset with A80 compatible string. Cc: Rask Ingemann Lambertsen Cc: Jaehoon Chung Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1e13a0665d..0c443a732d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, }; +static const struct sunxi_mmc_variant sun9i_a80_variant = { + .mclk_offset = 0x410, +}; + static const struct sunxi_mmc_variant sun50i_h6_variant = { .mclk_offset = 0x830, }; @@ -701,6 +705,10 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun8i-a83t-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun9i-a80-mmc", + .data = (ulong)&sun9i_a80_variant, + }, { .compatible = "allwinner,sun50i-a64-mmc", .data = (ulong)&sun4i_a10_variant, From c57572eb5aac7191026a069e8980a0faf01f2455 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:13 +0000 Subject: [PATCH 07/13] mmc: sunxi: Add DM clk and reset support Now that we have the gate clocks and the reset gates in our new Allwinner clock driver, let's make use of them in the MMC driver, when DM_MMC is defined. We treat the reset device as optional now, as the older SoCs don't implement it. Signed-off-by: Andre Przywara Reviewed-by: Jagan Teki --- drivers/mmc/sunxi_mmc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0c443a732d..488e772881 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -21,7 +23,6 @@ #ifdef CONFIG_DM_MMC struct sunxi_mmc_variant { - u16 gate_offset; u16 mclk_offset; }; #endif @@ -607,9 +608,11 @@ static int sunxi_mmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sunxi_mmc_plat *plat = dev_get_platdata(dev); struct sunxi_mmc_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk reset_bulk; + struct clk gate_clk; struct mmc_config *cfg = &plat->cfg; struct ofnode_phandle_args args; - u32 *gate_reg, *ccu_reg; + u32 *ccu_reg; int bus_width, ret; cfg->name = dev->name; @@ -641,8 +644,14 @@ static int sunxi_mmc_probe(struct udevice *dev) priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; priv->mclkreg = (void *)ccu_reg + (priv->variant->mclk_offset + (priv->mmc_no * 4)); - gate_reg = (void *)ccu_reg + priv->variant->gate_offset; - setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no))); + + ret = clk_get_by_name(dev, "ahb", &gate_clk); + if (!ret) + clk_enable(&gate_clk); + + ret = reset_get_bulk(dev, &reset_bulk); + if (!ret) + reset_deassert_bulk(&reset_bulk); ret = mmc_set_mod_clk(priv, 24000000); if (ret) @@ -676,7 +685,6 @@ static int sunxi_mmc_bind(struct udevice *dev) } static const struct sunxi_mmc_variant sun4i_a10_variant = { - .gate_offset = 0x60, .mclk_offset = 0x88, }; From a7ae159978a5e6de5587389fc099efbe8c238771 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:14 +0000 Subject: [PATCH 08/13] sunxi: board: do MMC pinmux setup for DM_MMC builds Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this is supposed to be handled by the MMC driver, using DT information. However we don't have a pinctrl driver yet, but would still like to keep the working pinmux setup for our MMC devices. So bring this particular call back to the DM_MMC code flow. When booting from either SD card or eMMC, the SPL does the setup for us, but when booting from SPI or USB we must not skip this part. Fixes, boot via FEL or SPI flash, where the SPL won't setup the pinmux Signed-off-by: Andre Przywara Acked-by: Jagan Teki [jagan: add Fix details on commit message] Signed-off-by: Jagan Teki --- board/sunxi/board.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ad14837291..98bc3cd0c1 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -208,6 +208,10 @@ enum env_location env_get_location(enum env_operation op, int prio) } #endif +#ifdef CONFIG_DM_MMC +static void mmc_pinmux_setup(int sdc); +#endif + /* add board specific code here */ int board_init(void) { @@ -269,6 +273,17 @@ int board_init(void) i2c_init_board(); #endif +#ifdef CONFIG_DM_MMC + /* + * Temporary workaround for enabling MMC clocks until a sunxi DM + * pinctrl driver lands. + */ + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif +#endif /* CONFIG_DM_MMC */ + /* Uses dm gpio code so do this here and not in i2c_init_board() */ return soft_i2c_board_init(); } From 4233698dd37536f2595ec773ca841360195cd310 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sat, 19 Jan 2019 01:30:53 +0000 Subject: [PATCH 09/13] mmc: sunxi: Honour non-removable property in DT If a board DT describes a cd-gpios property, but also marks the storage as non-removable, we must ignore the GPIO (as Linux does). Teach the DM_MMC part of the Allwinner MMC driver about the non-removable DT property, to fix DM_MMC access on the SoPine and Pine64-LTS board. Signed-off-by: Andre Przywara Acked-by: Jagan Teki --- drivers/mmc/sunxi_mmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 488e772881..9f426661c4 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -658,7 +658,8 @@ static int sunxi_mmc_probe(struct udevice *dev) return ret; /* This GPIO is optional */ - if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, + if (!dev_read_bool(dev, "non-removable") && + !gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN)) { int cd_pin = gpio_get_number(&priv->cd_gpio); From 13b0867dc3d2f911e0eb2636394ad79dfffc54e6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:08 +0000 Subject: [PATCH 10/13] sunxi: clk: enable clk and reset for CCU devices Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara Acked-by: Jagan Teki --- drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = { int sunxi_clk_probe(struct udevice *dev) { struct ccu_priv *priv = dev_get_priv(dev); + struct clk_bulk clk_bulk; + struct reset_ctl_bulk rst_bulk; + int ret; priv->base = dev_read_addr_ptr(dev); if (!priv->base) @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev) if (!priv->desc) return -EINVAL; + ret = clk_get_bulk(dev, &clk_bulk); + if (!ret) + clk_enable_bulk(&clk_bulk); + + ret = reset_get_bulk(dev, &rst_bulk); + if (!ret) + reset_deassert_bulk(&rst_bulk); + return 0; } From 708b5da38a19d41e6ccb9bff14f54b5f2d1db43c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 21 Jan 2019 16:01:15 +0530 Subject: [PATCH 11/13] arm: dts: sunxi: Alter mmc2 auto-numbering to mmc1 Environment and fastboot mmc devices are configured based on the number of mmc slots defined on particular board configs, MMC_SUNXI_SLOT_EXTRA. If MMC_SUNXI_SLOT_EXTRA is more than 1, the default env and fastboot mmc devices is mmc1 by assuming mmc0 is SD and mmc1 is emmc device. But with DM_MMC the mmc devices are numbered as per the dts node enablement. If there is a chance of having enabling all mmc nodes in dts say mmc0, mmc1, mmc2 then the default env and fastboot devices will failed to assign proper emmc device since mmc2 is emmc in most of the Allwinner platforms. So, we need to alter the auto-numbering by aliasing mmc2 to mmc1 since aliases take precedence over auto-numbering. If the dts enables mmc0, mmc1, mmc2, then all the nodes will probe sequentially and auto-numbered as it is. but when aliases mmc1 with mmc2 the resulting number should be that mmc0 is till mmc0, mmc2 become mmc1 and mmc2 become mmc1 Without aliases of mmc1 = &mmc2; ------------------------------- MMC: mmc@1c0f000: 0, mmc@1c10000: 1, mmc@1c11000: 2 With aliases of mmc1 = &mmc2; ---------------------------- MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000' mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1 Loading Environment from FAT... OK Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files. Signed-off-by: Jagan Teki --- arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include / { + aliases { + mmc1 = &mmc2; + }; + binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>; From cebeba9fdf1e15f8af709ca37f1f0e048fe73209 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 25 Jan 2019 13:58:25 +0530 Subject: [PATCH 12/13] sunxi: A64: pinebook-u-boot: Include sunxi-u-boot.dtsi Like other Allwinner A64 boards, pinebook also need altering auto-numbering of mmc2 to mmc1 which is available in common sunxi dsti file, sunxi-u-boot.dtsi Pinebook has a separate sun50i-a64-pinebook-u-boot.dtsi which takes more precedence for u-boot.dtsi inclusion and it eventually failed to include the sunxi-u-boot.dtsi. So, this patch add support to include the sunxi-u-boot.dtsi in the sun50i-a64-pinebook-u-boot.dtsi Signed-off-by: Jagan Teki Tested-by: Vasily Khoruzhick # Pinebook --- arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi index a99b7171d0..650ab97ec9 100644 --- a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi +++ b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi @@ -4,6 +4,8 @@ * */ +#include "sunxi-u-boot.dtsi" + /* The ANX6345 eDP-bridge is on r_i2c */ &r_i2c { anx6345: edp-bridge@38 { From a7cca5793774ee139b75a704d6efaa4d29f09f93 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Jan 2019 15:54:15 +0000 Subject: [PATCH 13/13] arm: sunxi: Enable DM_MMC Enable DM_MMC for all Allwinner SoCs, this will eventually enable BLK. Also removed DM_MMC enablement in few parts of sunxi configurations. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cefa8f40d0..f0edb10003 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -851,6 +851,7 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_KEYBOARD + select DM_MMC if MMC select DM_SERIAL select DM_USB if DISTRO_DEFAULTS select OF_BOARD_SETUP diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3c54f5106d..74e234cded 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -154,7 +154,6 @@ config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A select ARM_CORTEX_CPU_IS_UP - select DM_MMC if MMC select DM_SCSI if SCSI select PHY_SUN4I_USB select DRAM_SUN4I diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 9156f132d1..18f658e96b 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y