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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

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This commit is contained in:
Tom Rini
2020-12-18 13:06:02 -05:00
parent 233a4d47e7 936a645609
commit 549e7cb708
27 changed files with 1092 additions and 171 deletions
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5
arch/arc/dts/axs10x_mb.dtsi
View File

@@ -90,14 +90,15 @@
};
spi0: spi@0 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&apbclk>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;

5
arch/arc/dts/hsdk-common.dtsi
View File

@@ -128,14 +128,15 @@
};
spi0: spi@f0020000 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;

6
arch/arm/dts/socfpga.dtsi
View File

@@ -804,7 +804,8 @@
};
spi0: spi@fff00000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff00000 0x1000>;
@@ -816,7 +817,8 @@
};
spi1: spi@fff01000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;

6
arch/arm/dts/socfpga_agilex.dtsi
View File

@@ -366,7 +366,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@@ -379,7 +380,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,agilex-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

6
arch/arm/dts/socfpga_arria10.dtsi
View File

@@ -604,7 +604,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x100>;
@@ -617,7 +618,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "altr,socfpga-arria10-spi",
"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x100>;

6
arch/arm/dts/socfpga_stratix10.dtsi
View File

@@ -268,7 +268,8 @@
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@@ -281,7 +282,8 @@
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
compatible = "intel,stratix10-spi",
"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;

2
arch/mips/dts/mscc,jr2.dtsi
View File

@@ -94,7 +94,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

2
arch/mips/dts/mscc,ocelot.dtsi
View File

@@ -100,7 +100,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;

46
arch/riscv/dts/k210-maix-bit.dts
View File

@@ -152,7 +152,7 @@
pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
<K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
<K210_FPIOA(28, K210_PCF_SPI1_D0)>,
<K210_FPIOA(29, K210_PCF_GPIOHS13)>;
<K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
};
};
@@ -160,3 +160,47 @@
pinctrl-0 = <&fpioa_dvp>;
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&fpioa_spi0>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 20 0>;
panel@0 {
compatible = "sitronix,st7789v";
reg = <0>;
reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
dc-gpios = <&gpio0 22 0>;
spi-max-frequency = <15000000>;
status = "disabled";
};
};
&spi1 {
pinctrl-0 = <&fpioa_spi1>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 13 0>;
status = "okay";
slot@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <25000000>;
voltage-ranges = <3300 3300>;
broken-cd;
};
};
&spi3 {
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
broken-flash-reset;
};
};

15
arch/riscv/dts/k210.dtsi
View File

@@ -284,7 +284,8 @@
};
spi2: spi@50240000 {
compatible = "kendryte,k120-spislave",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
spi-slave;
reg = <0x50240000 0x100>;
@@ -495,6 +496,8 @@
interrupts = <24>;
clocks = <&sysclk K210_CLK_DVP>;
resets = <&sysrst K210_RST_DVP>;
kendryte,sysctl = <&sysctl>;
kendryte,misc-offset = <K210_SYSCTL_MISC>;
status = "disabled";
};
@@ -557,7 +560,8 @@
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x52000000 0x100>;
interrupts = <1>;
@@ -573,7 +577,8 @@
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
compatible = "canaan,kendryte-k210-spi",
"snps,dw-apb-ssi-4.01",
"snps,dw-apb-ssi";
reg = <0x53000000 0x100>;
interrupts = <2>;
@@ -589,8 +594,8 @@
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
compatible = "canaan,kendryte-k210-ssi",
"snps,dwc-ssi-1.01a";
reg = <0x54000000 0x200>;
interrupts = <4>;
clocks = <&sysclk K210_CLK_SPI3>;