rockchip: move ROCKCHIP_STIMER_BASE to Kconfig

Move ROCKCHIP_STIMER_BASE to Kconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker 2022-04-09 18:55:02 +02:00 committed by Kever Yang
parent 60be6e0860
commit 54562045e5
22 changed files with 44 additions and 14 deletions

View File

@ -339,6 +339,16 @@ config ROCKCHIP_BOOT_MODE_REG
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.
config ROCKCHIP_STIMER
bool "Rockchip STIMER support"
default y
help
Enable Rockchip STIMER support.
config ROCKCHIP_STIMER_BASE
hex
depends on ROCKCHIP_STIMER
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0

View File

@ -38,6 +38,9 @@ config TARGET_PX30_CORE
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
config ROCKCHIP_STIMER_BASE
default 0xff220020
config SYS_SOC
default "px30"

View File

@ -16,6 +16,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x200081c8
config ROCKCHIP_STIMER_BASE
default 0x200440a0
config SYS_SOC
default "rk3036"

View File

@ -16,6 +16,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x100a0038
config ROCKCHIP_STIMER_BASE
default 0x200440a0
config SYS_SOC
default "rk3128"

View File

@ -8,6 +8,9 @@ config TARGET_EVB_RK3229
config ROCKCHIP_BOOT_MODE_REG
default 0x110005c8
config ROCKCHIP_STIMER_BASE
default 0x110d0020
config SYS_SOC
default "rk322x"

View File

@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL
config ROCKCHIP_BOOT_MODE_REG
default 0xff730094
config ROCKCHIP_STIMER_BASE
default 0xff810020
config SYS_SOC
default "rk3288"

View File

@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC
bool "Firefly roc-rk3308-cc"
select BOARD_LATE_INIT
config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
config ROCKCHIP_STIMER_BASE
default 0xff1b00a0
config SYS_SOC
default "rk3308"
@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN
config SPL_SERIAL
default y
config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"

View File

@ -15,6 +15,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff1005c8
config ROCKCHIP_STIMER_BASE
default 0xff1d0020
config SYS_SOC
default "rk3328"

View File

@ -45,6 +45,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff738200
config ROCKCHIP_STIMER_BASE
default 0xff830020
config SYS_SOC
default "rk3368"

View File

@ -125,6 +125,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff320300
config ROCKCHIP_STIMER_BASE
default 0xff8680a0
config SYS_SOC
default "rk3399"

View File

@ -9,6 +9,9 @@ config TARGET_EVB_RK3568
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
config ROCKCHIP_STIMER_BASE
default 0xfdd1c020
config SYS_SOC
default "rk3568"

View File

@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_SPL_TEXT_BASE=0x10080800
CONFIG_ROCKCHIP_RK3188=y
# CONFIG_ROCKCHIP_STIMER is not set
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEBUG_UART_BASE=0x20064000

View File

@ -12,7 +12,6 @@
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
#define COUNTER_FREQUENCY 24000000
/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */

View File

@ -10,7 +10,6 @@
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000

View File

@ -11,7 +11,6 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000

View File

@ -11,7 +11,6 @@
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000

View File

@ -13,7 +13,6 @@
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000

View File

@ -15,7 +15,6 @@
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
#define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
#define CONFIG_SPL_STACK 0x00400000

View File

@ -10,7 +10,6 @@
#define CONFIG_IRAM_BASE 0xff090000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_CBSIZE 1024

View File

@ -15,7 +15,6 @@
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_IRAM_BASE 0xff8c0000

View File

@ -11,7 +11,6 @@
#define CONFIG_SYS_CBSIZE 1024
#define COUNTER_FREQUENCY 24000000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
#define CONFIG_IRAM_BASE 0xff8c0000

View File

@ -11,7 +11,6 @@
#define CONFIG_SYS_CBSIZE 1024
#define COUNTER_FREQUENCY 24000000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
#define CONFIG_IRAM_BASE 0xfdcc0000