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Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini
2016-04-13 12:53:11 -04:00
parent 3f8085e94a 58ed7f6693
commit 541c9be880
46 changed files with 3063 additions and 297 deletions
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3
arch/arm/Kconfig
View File

@@ -580,6 +580,7 @@ config ARCH_ZYNQ
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_SPI
@@ -592,8 +593,6 @@ config ARCH_ZYNQMP
select ARM64
select DM
select OF_CONTROL
select DM_ETH
select DM_MMC
select DM_SERIAL
config TEGRA

7
arch/arm/dts/Makefile
View File

@@ -81,7 +81,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb
zynqmp-ep108.dtb \
zynqmp-zcu102.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

14
arch/arm/dts/zynq-7000.dtsi
View File

@@ -96,8 +96,10 @@
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
#interrupt-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
@@ -270,6 +272,13 @@
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
@@ -297,7 +306,12 @@
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
global_timer: timer@f8f00200 {

38
arch/arm/dts/zynq-microzed.dts
View File

@@ -1,7 +1,7 @@
/*
* Xilinx MicroZED board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2013 - 2016 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -15,12 +15,27 @@
aliases {
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&qspi {
@@ -32,3 +47,24 @@
u-boot,dm-pre-reloc;
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};

29
arch/arm/dts/zynq-zc702.dts
View File

@@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -91,6 +91,8 @@
phy-handle = <&ethernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
phy-reset-gpio = <&gpio0 11 0>;
phy-reset-active-low;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
@@ -128,6 +130,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "right";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -370,6 +387,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@@ -384,11 +406,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

27
arch/arm/dts/zynq-zc706.dts
View File

@@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -84,6 +84,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "evenly";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -291,6 +306,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@@ -305,11 +325,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

44
arch/arm/dts/zynq-zc770-xm010.dts
View File

@@ -21,7 +21,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -36,27 +36,6 @@
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&qspi {
status = "okay";
};
&can0 {
status = "okay";
};
@@ -82,10 +61,31 @@
};
&qspi {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";

3
arch/arm/dts/zynq-zc770-xm011.dts
View File

@@ -7,6 +7,7 @@
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
model = "Xilinx Zynq";
@@ -18,7 +19,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};

2
arch/arm/dts/zynq-zc770-xm012.dts
View File

@@ -20,7 +20,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};

9
arch/arm/dts/zynq-zc770-xm013.dts
View File

@@ -16,11 +16,12 @@
ethernet0 = &gem1;
i2c0 = &i2c1;
serial0 = &uart0;
spi0 = &spi0;
spi0 = &qspi;
spi1 = &spi0;
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -58,6 +59,10 @@
};
};
&qspi {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <4>;

12
arch/arm/dts/zynq-zed.dts
View File

@@ -26,7 +26,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
@@ -50,6 +50,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@@ -60,11 +65,6 @@
status = "okay";
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

14
arch/arm/dts/zynq-zybo.dts
View File

@@ -26,13 +26,13 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reset-gpios = <&gpio0 46 1>;
};
};
@@ -51,6 +51,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
@@ -61,11 +66,6 @@
status = "okay";
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

202
arch/arm/dts/zynqmp-clk.dtsi Normal file
View File

@@ -0,0 +1,202 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
&amba {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
clk600: clk600 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
dp_aclk: clock0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-accuracy = <100>;
};
dpdma_clk: dpdma_clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
drm_clock: drm_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
clock-accuracy = <0x64>;
};
};
&can0 {
clocks = <&clk100 &clk100>;
};
&can1 {
clocks = <&clk100 &clk100>;
};
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&nand0 {
clocks = <&clk100 &clk100>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem2 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem3 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gpio {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&qspi {
clocks = <&clk300 &clk300>;
};
&sata {
clocks = <&clk250>;
};
&sdhci0 {
clocks = <&clk200 &clk200>;
};
&sdhci1 {
clocks = <&clk200 &clk200>;
};
&spi0 {
clocks = <&clk200 &clk200>;
};
&spi1 {
clocks = <&clk200 &clk200>;
};
&uart0 {
clocks = <&clk100 &clk100>;
};
&uart1 {
clocks = <&clk100 &clk100>;
};
&usb0 {
clocks = <&clk250>, <&clk250>;
};
&usb1 {
clocks = <&clk250>, <&clk250>;
};
&xilinx_drm {
clocks = <&drm_clock>;
};
&xlnx_dp {
clocks = <&dp_aclk>, <&dp_aud_clk>;
};
&xlnx_dpdma {
clocks = <&dpdma_clk>;
};
&xlnx_dp_snd_codec0 {
clocks = <&dp_aud_clk>;
};

4
arch/arm/dts/zynqmp-ep108-clk.dtsi
View File

@@ -62,6 +62,10 @@
clocks = <&i2c_clk>;
};
&nand0 {
clocks = <&misc_clk &misc_clk>;
};
&qspi {
clocks = <&misc_clk &misc_clk>;
};

61
arch/arm/dts/zynqmp-ep108.dts
View File

@@ -10,17 +10,21 @@
/dts-v1/;
/include/ "zynqmp.dtsi"
/include/ "zynqmp-ep108-clk.dtsi"
#include "zynqmp.dtsi"
#include "zynqmp-ep108-clk.dtsi"
/ {
model = "ZynqMP EP108";
aliases {
mmc0 = &sdhci0;
mmc1 = &sdhci1;
serial0 = &uart0;
spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
@@ -29,7 +33,7 @@
memory {
device_type = "memory";
reg = <0x0 0x0 0x40000000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
};
@@ -69,10 +73,41 @@
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <1>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "n25q512a11";
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
@@ -101,10 +136,20 @@
&sata {
status = "okay";
ceva,broken-gen2;
/* SATA Phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
};
&sdhci0 {
status = "okay";
bus-width = <8>;
};
&sdhci1 {
@@ -151,12 +196,20 @@
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
&usb1 {
status = "okay";
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "high-speed";
};

211
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts Normal file
View File

@@ -0,0 +1,211 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
compatible = "at,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
/* eMMC */
&sdhci0 {
status = "okay";
bus-width = <8>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
};
&uart0 {
status = "okay";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&xilinx_drm {
status = "okay";
};
&xlnx_dp {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

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arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts Normal file
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/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &gem2;
gpio0 = &gpio;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem2 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* IRQ not connected */
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <2>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
partition@6 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x1 0x0 0x400000>;
};
partition@7 { /* for testing purpose */
label = "nand1-linux";
reg = <0x1 0x400000 0x1400000>;
};
partition@8 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x1 0x1800000 0x400000>;
};
partition@9 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x1 0x1C00000 0x1400000>;
};
partition@10 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x1 0x3000000 0x400000>;
};
partition@11 { /* for testing purpose */
label = "nand1-misc";
reg = <0x1 0x3400000 0xFCC00000>;
};
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <1>;
spi0_flash0: spi0_flash0@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi0_flash0@00000000 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
};
};
&spi1 {
status = "okay";
num-cs = <1>;
spi1_flash0: spi1_flash0@0 {
compatible = "mtd_dataflash";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi1_flash0@00000000 {
label = "spi1_flash0";
reg = <0x0 0x84000>;
};
};
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

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arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts Normal file
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/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
ethernet0 = &gem1;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem1 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
};
/* FIXME: Add device */
&i2c0 {
status = "okay";
};
/* FIXME: Add device */
&i2c1 {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

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arch/arm/dts/zynqmp-zcu102-revB.dts Normal file
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/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
* (C) Copyright 2016, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "zynqmp-zcu102.dts"
/ {
model = "ZynqMP ZCU102 RevB";
};
&gem3 {
phy-handle = <&phyc>;
phyc: phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
/* Cleanup from RevA */
/delete-node/ phy@21;
};
/* Different qspi 512Mbit version */
/* Fix collision with u61 */
&i2c0 {
i2cswitch@75 {
i2c@2 {
max15303@1b { /* u8 */
compatible = "max15303";
reg = <0x1b>;
};
/delete-node/ max15303@20;
};
};
};

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arch/arm/dts/zynqmp-zcu102.dts Normal file
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/*
* dts file for Xilinx ZynqMP ZCU102
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
/ {
model = "ZynqMP ZCU102 RevA";
compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&can1 {
status = "okay";
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
};
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
tca6416_u97: gpio@20 {
/*
* Enable all GTs to out from U-Boot
* i2c mw 20 6 0 - setup IO to output
* i2c mw 20 2 ef - setup output values on pins 0-7
* i2c mw 20 3 ff - setup output values on pins 10-17
*/
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - PS_GTR_LAN_SEL0
* 1 - PS_GTR_LAN_SEL1
* 2 - PS_GTR_LAN_SEL2
* 3 - PS_GTR_LAN_SEL3
* 4 - PCI_CLK_DIR_SEL
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 7, 10 - 17 - not connected
*/
gtr_sel0 {
gpio-hog;
gpios = <0 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr_sel1 {
gpio-hog;
gpios = <1 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel1";
};
gtr_sel2 {
gpio-hog;
gpios = <2 0>;
output-high; /* PCIE = 0, USB0 = 1 */
line-name = "sel2";
};
gtr_sel3 {
gpio-hog;
gpios = <3 0>;
output-high; /* PCIE = 0, SATA = 1 */
line-name = "sel3";
};
};
tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - VCCPSPLL_EN
* 1 - MGTRAVCC_EN
* 2 - MGTRAVTT_EN
* 3 - VCCPSDDRPLL_EN
* 4 - MIO26_PMU_INPUT_LS
* 5 - PL_PMBUS_ALERT
* 6 - PS_PMBUS_ALERT
* 7 - MAXIM_PMBUS_ALERT
* 10 - PL_DDR4_VTERM_EN
* 11 - PL_DDR4_VPP_2V5_EN
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
* 13 - PS_DIMM_SUSPEND_EN
* 14 - PS_DDR4_VTERM_EN
* 15 - PS_DDR4_VPP_2V5_EN
* 16 - 17 - not connected
*/
};
i2cswitch@75 { /* u60 */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
ina226@40 { /* u76 */
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <5000>;
};
ina226@41 { /* u77 */
compatible = "ti,ina226";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u78 */
compatible = "ti,ina226";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u87 */
compatible = "ti,ina226";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u85 */
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u86 */
compatible = "ti,ina226";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u93 */
compatible = "ti,ina226";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u88 */
compatible = "ti,ina226";
reg = <0x47>;
shunt-resistor = <5000>;
};
ina226@4a { /* u15 */
compatible = "ti,ina226";
reg = <0x4a>;
shunt-resistor = <5000>;
};
ina226@4b { /* u92 */
compatible = "ti,ina226";
reg = <0x4b>;
shunt-resistor = <5000>;
};
};
i2c@1 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* PL_PMBUS */
ina226@40 { /* u79 */
compatible = "ti,ina226";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina226@41 { /* u81 */
compatible = "ti,ina226";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u80 */
compatible = "ti,ina226";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u84 */
compatible = "ti,ina226";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u16 */
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u65 */
compatible = "ti,ina226";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u74 */
compatible = "ti,ina226";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u75 */
compatible = "ti,ina226";
reg = <0x47>;
shunt-resistor = <5000>;
};
};
i2c@2 { /* i2c mw 75 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* MAXIM_PMBUS - 00 */
max15301@a { /* u46 */
compatible = "max15301";
reg = <0xa>;
};
max15303@b { /* u4 */
compatible = "max15303";
reg = <0xb>;
};
max15303@10 { /* u13 */
compatible = "max15303";
reg = <0x10>;
};
max15301@13 { /* u47 */
compatible = "max15301";
reg = <0x13>;
};
max15303@14 { /* u7 */
compatible = "max15303";
reg = <0x14>;
};
max15303@15 { /* u6 */
compatible = "max15303";
reg = <0x15>;
};
max15303@16 { /* u10 */
compatible = "max15303";
reg = <0x16>;
};
max15303@17 { /* u9 */
compatible = "max15303";
reg = <0x17>;
};
max15301@18 { /* u63 */
compatible = "max15301";
reg = <0x18>;
};
max15303@1a { /* u49 */
compatible = "max15303";
reg = <0x1a>;
};
max15303@1d { /* u18 */
compatible = "max15303";
reg = <0x1d>;
};
max15303@20 { /* u8 */
compatible = "max15303";
status = "disabled"; /* unreachable */
reg = <0x20>;
};
/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
*/
max20751@72 { /* u95 FIXME - not detected */
compatible = "max20751";
reg = <0x72>;
};
max20751@73 { /* u96 FIXME - not detected */
compatible = "max20751";
reg = <0x73>;
};
};
/* Bus 3 is not connected */
};
/* FIXME PL connection - u55 , PMOD - j160 */
/* FIXME MSP430F - u41 - not detected */
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
/* FIXME PL i2c via PCA9306 - u45 */
/* FIXME MSP430 - u41 - not detected */
i2cswitch@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 { /* i2c mw 74 0 1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* IIC_EEPROM 1kB memory which uses 256B blocks
* where every block has different address.
* 0 - 256B address 0x54
* 256B - 512B address 0x55
* 512B - 768B address 0x56
* 768B - 1024B address 0x57
*/
eeprom@54 { /* u23 */
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@1 { /* i2c mw 74 0 2 */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
si5341: clock-generator1@36 { /* SI5341 - u69 */
compatible = "si5341";
reg = <0x36>;
};
};
i2c@2 { /* i2c mw 74 0 4 */
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
si570_1: clock-generator2@5d { /* USER SI570 - u42 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
};
};
i2c@3 { /* i2c mw 74 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@4 { /* i2c mw 74 0 10 */
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator4@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
};
};
/* 5 - 7 unconnected */
};
i2cswitch@75 {
compatible = "nxp,pca9548"; /* u135 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* HPC0_IIC */
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* HPC1_IIC */
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
/* SYSMON */
};
i2c@3 { /* i2c mw 75 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
dev@19 { /* u-boot detection */
compatible = "xxx";
reg = <0x19>;
};
dev@30 { /* u-boot detection */
compatible = "xxx";
reg = <0x30>;
};
dev@35 { /* u-boot detection */
compatible = "xxx";
reg = <0x35>;
};
dev@36 { /* u-boot detection */
compatible = "xxx";
reg = <0x36>;
};
dev@51 { /* u-boot detection - maybe SPD */
compatible = "xxx";
reg = <0x51>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* SEP 3 */
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
/* SEP 2 */
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/* SEP 1 */
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
/* SEP 0 */
};
};
};
&pcie {
/* status = "okay"; */
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "m25p80"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
};
&xilinx_drm {
status = "okay";
clocks = <&si570_1>;
};
&xlnx_dp {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

382
arch/arm/dts/zynqmp.dtsi
View File

@@ -10,7 +10,7 @@
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <1>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
@@ -45,8 +45,179 @@
};
};
power-domains {
compatible = "xlnx,zynqmp-genpd";
pd_usb0: pd-usb0 {
#power-domain-cells = <0x0>;
pd-id = <0x16>;
};
pd_usb1: pd-usb1 {
#power-domain-cells = <0x0>;
pd-id = <0x17>;
};
pd_sata: pd-sata {
#power-domain-cells = <0x0>;
pd-id = <0x1c>;
};
pd_spi0: pd-spi0 {
#power-domain-cells = <0x0>;
pd-id = <0x23>;
};
pd_spi1: pd-spi1 {
#power-domain-cells = <0x0>;
pd-id = <0x24>;
};
pd_uart0: pd-uart0 {
#power-domain-cells = <0x0>;
pd-id = <0x21>;
};
pd_uart1: pd-uart1 {
#power-domain-cells = <0x0>;
pd-id = <0x22>;
};
pd_eth0: pd-eth0 {
#power-domain-cells = <0x0>;
pd-id = <0x1d>;
};
pd_eth1: pd-eth1 {
#power-domain-cells = <0x0>;
pd-id = <0x1e>;
};
pd_eth2: pd-eth2 {
#power-domain-cells = <0x0>;
pd-id = <0x1f>;
};
pd_eth3: pd-eth3 {
#power-domain-cells = <0x0>;
pd-id = <0x20>;
};
pd_i2c0: pd-i2c0 {
#power-domain-cells = <0x0>;
pd-id = <0x25>;
};
pd_i2c1: pd-i2c1 {
#power-domain-cells = <0x0>;
pd-id = <0x26>;
};
pd_dp: pd-dp {
/* fixme: what to attach to */
#power-domain-cells = <0x0>;
pd-id = <0x29>;
};
pd_gdma: pd-gdma {
#power-domain-cells = <0x0>;
pd-id = <0x2a>;
};
pd_adma: pd-adma {
#power-domain-cells = <0x0>;
pd-id = <0x2b>;
};
pd_ttc0: pd-ttc0 {
#power-domain-cells = <0x0>;
pd-id = <0x18>;
};
pd_ttc1: pd-ttc1 {
#power-domain-cells = <0x0>;
pd-id = <0x19>;
};
pd_ttc2: pd-ttc2 {
#power-domain-cells = <0x0>;
pd-id = <0x1a>;
};
pd_ttc3: pd-ttc3 {
#power-domain-cells = <0x0>;
pd-id = <0x1b>;
};
pd_sd0: pd-sd0 {
#power-domain-cells = <0x0>;
pd-id = <0x27>;
};
pd_sd1: pd-sd1 {
#power-domain-cells = <0x0>;
pd-id = <0x28>;
};
pd_nand: pd-nand {
#power-domain-cells = <0x0>;
pd-id = <0x2c>;
};
pd_qspi: pd-qspi {
#power-domain-cells = <0x0>;
pd-id = <0x2d>;
};
pd_gpio: pd-gpio {
#power-domain-cells = <0x0>;
pd-id = <0x2e>;
};
pd_can0: pd-can0 {
#power-domain-cells = <0x0>;
pd-id = <0x2f>;
};
pd_can1: pd-can1 {
#power-domain-cells = <0x0>;
pd-id = <0x30>;
};
pd_ddr: pd-ddr {
#power-domain-cells = <0x0>;
pd-id = <0x37>;
};
pd_apll: pd-apll {
#power-domain-cells = <0x0>;
pd-id = <0x32>;
};
pd_vpll: pd-vpll {
#power-domain-cells = <0x0>;
pd-id = <0x33>;
};
pd_dpll: pd-dpll {
#power-domain-cells = <0x0>;
pd-id = <0x34>;
};
pd_rpll: pd-rpll {
#power-domain-cells = <0x0>;
pd-id = <0x35>;
};
pd_iopll: pd-iopll {
#power-domain-cells = <0x0>;
pd-id = <0x36>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <0 143 4>,
<0 144 4>,
<0 145 4>,
@@ -76,7 +247,7 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
@@ -95,7 +266,7 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
ranges = <0 0 0 0 0xffffffff>;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
@@ -106,6 +277,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <&pd_can0>;
};
can1: can@ff070000 {
@@ -117,6 +289,26 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
power-domains = <&pd_can1>;
};
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
reg = <0x0 0xfd6e0000 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupt-parent = <&gic>;
interrupts = <0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>,
<0 123 4>;
};
};
/* GDMA */
@@ -126,8 +318,10 @@
reg = <0x0 0xfd500000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <0>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan2: dma@fd510000 {
@@ -136,8 +330,10 @@
reg = <0x0 0xfd510000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <1>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan3: dma@fd520000 {
@@ -146,8 +342,10 @@
reg = <0x0 0xfd520000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <2>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan4: dma@fd530000 {
@@ -156,8 +354,10 @@
reg = <0x0 0xfd530000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <3>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan5: dma@fd540000 {
@@ -166,8 +366,10 @@
reg = <0x0 0xfd540000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <4>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan6: dma@fd550000 {
@@ -176,8 +378,10 @@
reg = <0x0 0xfd550000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <5>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan7: dma@fd560000 {
@@ -186,8 +390,10 @@
reg = <0x0 0xfd560000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <6>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan8: dma@fd570000 {
@@ -196,8 +402,10 @@
reg = <0x0 0xfd570000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,id = <7>;
xlnx,bus-width = <128>;
power-domains = <&pd_gdma>;
};
gpu: gpu@fd4b0000 {
@@ -218,6 +426,7 @@
interrupts = <0 77 4>;
xlnx,id = <0>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan2: dma@ffa90000 {
@@ -228,6 +437,7 @@
interrupts = <0 78 4>;
xlnx,id = <1>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan3: dma@ffaa0000 {
@@ -238,6 +448,7 @@
interrupts = <0 79 4>;
xlnx,id = <2>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan4: dma@ffab0000 {
@@ -248,6 +459,7 @@
interrupts = <0 80 4>;
xlnx,id = <3>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan5: dma@ffac0000 {
@@ -258,6 +470,7 @@
interrupts = <0 81 4>;
xlnx,id = <4>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan6: dma@ffad0000 {
@@ -268,6 +481,7 @@
interrupts = <0 82 4>;
xlnx,id = <5>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan7: dma@ffae0000 {
@@ -278,6 +492,7 @@
interrupts = <0 83 4>;
xlnx,id = <6>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
lpd_dma_chan8: dma@ffaf0000 {
@@ -288,6 +503,14 @@
interrupts = <0 84 4>;
xlnx,id = <7>;
xlnx,bus-width = <64>;
power-domains = <&pd_adma>;
};
mc: memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
nand0: nand@ff100000 {
@@ -299,10 +522,11 @@
interrupts = <0 14 4>;
#address-cells = <2>;
#size-cells = <1>;
power-domains = <&pd_nand>;
};
gem0: ethernet@ff0b0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
@@ -310,12 +534,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth0>;
};
gem1: ethernet@ff0c0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
@@ -323,12 +547,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth1>;
};
gem2: ethernet@ff0d0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
@@ -336,12 +560,12 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth2>;
};
gem3: ethernet@ff0e0000 {
compatible = "cdns,gem";
compatible = "cdns,zynqmp-gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
@@ -349,17 +573,20 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
jumbo-max-len = <10240>;
jumbo-supported;
#stream-id-cells = <1>;
power-domains = <&pd_eth3>;
};
gpio: gpio@ff0a0000 {
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
reg = <0x0 0xff0a0000 0x1000>;
power-domains = <&pd_gpio>;
};
i2c0: i2c@ff020000 {
@@ -370,6 +597,7 @@
reg = <0x0 0xff020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c0>;
};
i2c1: i2c@ff030000 {
@@ -380,6 +608,7 @@
reg = <0x0 0xff030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c1>;
};
pcie: pcie@fd0e0000 {
@@ -390,16 +619,26 @@
#interrupt-cells = <1>;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = < 0 118 4>,
< 0 116 4>,
< 0 115 4>, /* MSI_1 [63...32] */
< 0 114 4 >; /* MSI_0 [31...0] */
interrupts = <0 118 4>,
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
interrupt-names = "misc", "intx", "msi_1", "msi_0";
reg = <0x0 0xfd0e0000 0x1000>,
<0x0 0xfd480000 0x1000>,
<0x0 0xe0000000 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
qspi: spi@ff0f0000 {
@@ -409,9 +648,11 @@
interrupts = <0 15 4>;
interrupt-parent = <&gic>;
num-cs = <1>;
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
reg = <0x0 0xff0f0000 0x1000>,
<0x0 0xc0000000 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_qspi>;
};
rtc: rtc@ffa60000 {
@@ -429,6 +670,7 @@
reg = <0x0 0xfd0c0000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
};
sdhci0: sdhci@ff160000 {
@@ -438,6 +680,8 @@
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
broken-tuning;
power-domains = <&pd_sd0>;
};
sdhci1: sdhci@ff170000 {
@@ -447,6 +691,8 @@
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
broken-tuning;
power-domains = <&pd_sd1>;
};
smmu: smmu@fd800000 {
@@ -454,11 +700,15 @@
reg = <0x0 0xfd800000 0x20000>;
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
interrupts = <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
mmu-masters = < &gem0 0x874
&gem1 0x875
&gem2 0x876
&gem3 0x877 >;
};
spi0: spi@ff040000 {
@@ -470,6 +720,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_spi0>;
};
spi1: spi@ff050000 {
@@ -481,6 +732,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_spi1>;
};
ttc0: timer@ff110000 {
@@ -490,6 +742,7 @@
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc0>;
};
ttc1: timer@ff120000 {
@@ -499,6 +752,7 @@
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc1>;
};
ttc2: timer@ff130000 {
@@ -508,6 +762,7 @@
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc2>;
};
ttc3: timer@ff140000 {
@@ -517,42 +772,69 @@
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc3>;
};
uart0: serial@ff000000 {
compatible = "cdns,uart-r1p12";
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart0>;
};
uart1: serial@ff010000 {
compatible = "cdns,uart-r1p12";
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart1>;
};
usb0: usb@fe200000 {
compatible = "snps,dwc3";
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
power-domains = <&pd_usb0>;
ranges;
dwc3_0: dwc3@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
snps,refclk_fladj;
};
};
usb1: usb@fe300000 {
compatible = "snps,dwc3";
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
power-domains = <&pd_usb1>;
ranges;
dwc3_1: dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
snps,refclk_fladj;
};
};
watchdog0: watchdog@fd4d0000 {
@@ -583,10 +865,11 @@
};
};
xlnx_dp: dp@43c00000 {
xlnx_dp: dp@fd4a0000 {
compatible = "xlnx,v-dp";
status = "disabled";
reg = <0x0 0xfd4a0000 0x1000>;
reg = <0x0 0xfd4a0000 0x1000>,
<0x0 0xfd400000 0x20000>;
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
@@ -599,6 +882,7 @@
xlnx,bpc = <8>;
xlnx,audio-chan = <2>;
xlnx,dp-sub = <&xlnx_dp_sub>;
xlnx,max-pclock-frequency = <300000>;
};
xlnx_dp_snd_card: dp_snd_card {
@@ -628,12 +912,16 @@
dma-names = "tx";
};
xlnx_dp_sub: dp_sub@43c0a000 {
xlnx_dp_sub: dp_sub@fd4aa000 {
compatible = "xlnx,dp-sub";
status = "disabled";
reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
reg = <0x0 0xfd4aa000 0x1000>,
<0x0 0xfd4ab000 0x1000>,
<0x0 0xfd4ac000 0x1000>;
reg-names = "blend", "av_buf", "aud";
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
};
xlnx_dpdma: dma@fd4c0000 {
@@ -645,22 +933,22 @@
clock-names = "axi_clk";
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel@43c10000 {
dma-video0channel@fd4c0000 {
compatible = "xlnx,video0";
};
dma-video1channel@43c10000 {
dma-video1channel@fd4c0000 {
compatible = "xlnx,video1";
};
dma-video2channel@43c10000 {
dma-video2channel@fd4c0000 {
compatible = "xlnx,video2";
};
dma-graphicschannel@43c10000 {
dma-graphicschannel@fd4c0000 {
compatible = "xlnx,graphics";
};
dma-audio0channel@43c10000 {
dma-audio0channel@fd4c0000 {
compatible = "xlnx,audio0";
};
dma-audio1channel@43c10000 {
dma-audio1channel@fd4c0000 {
compatible = "xlnx,audio1";
};
};

63
arch/arm/mach-zynq/include/mach/gpio.h
View File

@@ -8,67 +8,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK 4
#define ZYNQ_GPIO_BANK0_NGPIO 32
#define ZYNQ_GPIO_BANK1_NGPIO 22
#define ZYNQ_GPIO_BANK2_NGPIO 32
#define ZYNQ_GPIO_BANK3_NGPIO 32
#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
ZYNQ_GPIO_BANK1_NGPIO + \
ZYNQ_GPIO_BANK2_NGPIO + \
ZYNQ_GPIO_BANK3_NGPIO)
#define ZYNQ_GPIO_BANK0_PIN_MIN 0
#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
ZYNQ_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
ZYNQ_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
ZYNQ_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
ZYNQ_GPIO_BANK3_NGPIO - 1)
/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
#endif /* _ZYNQ_GPIO_H */