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Merge branch '2022-02-08-TI-platform-updates'

Browse Source 
- J721S2 support, IPU support on DRA7, SIERRA PHY mulitlink
  configuration support, Nokia RX-51 DM_KEYBOARD conversion
This commit is contained in:
Tom Rini 2022-02-08 12:28:04 -05:00
commit 531c008945
93 changed files with 17338 additions and 279 deletions
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4
MAINTAINERS
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@ -520,6 +520,8 @@ ARM TI
M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-ti.git
F: arch/arm/dts/am57xx*
F: arch/arm/dts/dra7*
F: arch/arm/mach-davinci/
F: arch/arm/mach-k3/
F: arch/arm/mach-keystone/
@ -539,9 +541,11 @@ F: drivers/phy/omap-usb2-phy.c
F: drivers/phy/phy-ti-am654.c
F: drivers/phy/ti-pipe3-phy.c
F: drivers/ram/k3*
F: drivers/remoteproc/ipu_rproc.c
F: drivers/remoteproc/k3_system_controller.c
F: drivers/remoteproc/pruc_rpoc.c
F: drivers/remoteproc/ti*
F: drivers/reset/reset-dra7.c
F: drivers/reset/reset-ti-sci.c
F: drivers/rtc/davinci.c
F: drivers/serial/serial_omap.c

2
arch/arm/dts/Makefile
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@ -1140,6 +1140,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \

7
arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"

7
arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"

7
arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"

7
arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"

1
arch/arm/dts/am57xx-idk-common-u-boot.dtsi
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@ -3,6 +3,7 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"
/ {
xtal25mhz: xtal25mhz {

7
arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"

1
arch/arm/dts/dra7-evm-u-boot.dtsi
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@ -4,6 +4,7 @@
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;

113
arch/arm/dts/dra7-ipu-common-early-boot.dtsi Normal file
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@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
/ {
chosen {
firmware-loader = &fs_loader0;
};
fs_loader0: fs_loader@0 {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc1 1>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-spl;
ipu2_memory_region: ipu2-memory@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "okay";
u-boot,dm-spl;
};
ipu1_memory_region: ipu1-memory@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
u-boot,dm-spl;
};
ipu1_pgtbl: ipu1-pgtbl@95700000 {
reg = <0x0 0x95700000 0x0 0x40000>;
no-map;
u-boot,dm-spl;
};
ipu2_pgtbl: ipu2-pgtbl@95740000 {
reg = <0x0 0x95740000 0x0 0x40000>;
no-map;
u-boot,dm-spl;
};
};
};
&timer3 {
u-boot,dm-spl;
};
&timer4 {
u-boot,dm-spl;
};
&timer7 {
u-boot,dm-spl;
};
&timer8 {
u-boot,dm-spl;
};
&timer9 {
u-boot,dm-spl;
};
&timer11 {
u-boot,dm-spl;
};
&mmu_ipu1 {
u-boot,dm-spl;
};
&mmu_ipu2 {
u-boot,dm-spl;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_memory_region>;
pg-tbl = <&ipu1_pgtbl>;
u-boot,dm-spl;
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_memory_region>;
pg-tbl = <&ipu2_pgtbl>;
u-boot,dm-spl;
};
&l4_wkup {
u-boot,dm-spl;
};
&prm {
u-boot,dm-spl;
};
&ipu1_rst {
u-boot,dm-spl;
};
&ipu2_rst {
u-boot,dm-spl;
};

45
arch/arm/dts/dra7.dtsi
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@ -41,6 +41,8 @@
d_can0 = &dcan1;
d_can1 = &dcan2;
spi0 = &qspi;
remoteproc0 = &ipu1;
remoteproc1 = &ipu2;
};
timer {
@ -263,9 +265,12 @@
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
@ -274,6 +279,20 @@
prm_clockdomains: clockdomains {
};
ipu1_rst: ipu1_rst@510 {
compatible = "ti,dra7-reset";
reg = <0x510 0x8>;
ti,nresets = <3>;
#reset-cells = <1>;
};
ipu2_rst: ipu2_rst@910 {
compatible = "ti,dra7-reset";
reg = <0x910 0x8>;
ti,nresets = <3>;
#reset-cells = <1>;
};
};
scm_wkup: scm_conf@c000 {
@ -2032,6 +2051,30 @@
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
ipu1: ipu@58820000 {
compatible = "ti,dra7-ipu";
reg = <0x58820000 0x10000>;
reg-names = "l2ram";
ti,hwmods = "ipu1";
resets = <&ipu1_rst 0>, <&ipu1_rst 1>, <&ipu1_rst 2>;
iommus = <&mmu_ipu1>;
ti,rproc-standby-info = <0x4a005520>;
timers = <&timer11>;
watchdog-timers = <&timer7>, <&timer8>;
};
ipu2: ipu@55020000 {
compatible = "ti,dra7-ipu";
reg = <0x55020000 0x10000>;
reg-names = "l2ram";
ti,hwmods = "ipu2";
resets = <&ipu2_rst 0>, <&ipu2_rst 1>, <&ipu2_rst 2>;
iommus = <&mmu_ipu2>;
ti,rproc-standby-info = <0x4a008920>;
timers = <&timer3>;
watchdog-timers = <&timer4>, <&timer9>;
};
};
thermal_zones: thermal-zones {

1
arch/arm/dts/dra71-evm-u-boot.dtsi
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@ -4,6 +4,7 @@
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;

1
arch/arm/dts/dra72-evm-revc-u-boot.dtsi
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@ -4,6 +4,7 @@
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"
&pcf_gpio_21{
u-boot,i2c-offset-len = <0>;

1
arch/arm/dts/dra76-evm-u-boot.dtsi
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@ -4,6 +4,7 @@
*/
#include "omap5-u-boot.dtsi"
#include "dra7-ipu-common-early-boot.dtsi"
&cpsw_emac0 {
phy-handle = <&dp83867_0>;

15
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
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@ -232,3 +232,18 @@
&usb_serdes_mux {
u-boot,mux-autoprobe;
};
&serdes0 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&serdes0_pcie_link {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
};
&serdes0_qsgmii_link {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
};

14
arch/arm/dts/k3-j721e-common-proc-board.dts
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@ -345,7 +345,7 @@
};
&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
@ -671,8 +671,8 @@
};
&serdes0 {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@ -681,6 +681,14 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
serdes0_qsgmii_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz0 2>;
};
};
&serdes1 {

32
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
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@ -8,6 +8,7 @@
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
#include <dt-bindings/phy/phy-cadence.h>
/ {
aliases {
@ -361,3 +362,34 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
&wiz0_pll1_refclk {
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz0_refclk_dig {
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&cmn_refclk1>;
};
&serdes0 {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: link@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
serdes0_qsgmii_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz0 2>;
};
};

149
arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi Normal file
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@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart8;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &mcu_i2c1;
i2c3 = &main_i2c0;
ethernet0 = &cpsw_port1;
};
};
&wkup_i2c0 {
u-boot,dm-spl;
};
&cbass_main {
u-boot,dm-spl;
};
&main_navss {
u-boot,dm-spl;
};
&cbass_mcu_wakeup {
u-boot,dm-spl;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
u-boot,dm-spl;
};
chipid@43000014 {
u-boot,dm-spl;
};
};
&mcu_navss {
u-boot,dm-spl;
};
&mcu_ringacc {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
&secure_proxy_main {
u-boot,dm-spl;
};
&sms {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
};
&main_uart8_pins_default {
u-boot,dm-spl;
};
&main_mmc1_pins_default {
u-boot,dm-spl;
};
&wkup_pmx0 {
u-boot,dm-spl;
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&main_uart8 {
u-boot,dm-spl;
};
&mcu_uart0 {
u-boot,dm-spl;
};
&wkup_uart0 {
u-boot,dm-spl;
};
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@40f04040 {
compatible = "ti,am654-cpsw-phy-sel";
reg= <0x0 0x40f04040 0x0 0x4>;
reg-names = "gmii-sel";
};
};
&main_sdhci0 {
u-boot,dm-spl;
};
&main_sdhci1 {
u-boot,dm-spl;
};

430
arch/arm/dts/k3-j721s2-common-proc-board.dts Normal file
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@ -0,0 +1,430 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
* Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
*/
/dts-v1/;
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
model = "Texas Instruments J721S2 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000";
};
aliases {
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
};
evm_12v0: fixedregulator-evm12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixedregulator-sd {
/* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv: gpio-regulator-TLV71033 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
transceiver1: can-phy1 {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>;
enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
};
transceiver2: can-phy2 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
>;
};
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
};
&main_gpio2 {
status = "disabled";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&wkup_gpio1 {
status = "disabled";
};
&wkup_uart0 {
status = "reserved";
};
&main_uart0 {
status = "disabled";
};
&main_uart1 {
status = "disabled";
};
&main_uart2 {
status = "disabled";
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "disabled";
};
&main_uart7 {
status = "disabled";
};
&main_uart8 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
&main_uart9 {
status = "disabled";
};
&main_i2c0 {
clock-frequency = <400000>;
exp1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
"PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
"PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
"PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
"EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
};
exp2: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
"USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
"MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
"MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
"CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
"ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
};
};
&main_i2c1 {
status = "disabled";
};
&main_i2c2 {
status = "disabled";
};
&main_i2c3 {
status = "disabled";
};
&main_i2c4 {
status = "disabled";
};
&main_i2c5 {
status = "disabled";
};
&main_i2c6 {
status = "disabled";
};
&main_sdhci0 {
/* eMMC */
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD card */
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
};
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
};
&mcu_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
};
&main_mcan0 {
status = "disabled";
};
&main_mcan1 {
status = "disabled";
};
&main_mcan2 {
status = "disabled";
};
&main_mcan3 {
status = "disabled";
};
&main_mcan4 {
status = "disabled";
};
&main_mcan5 {
status = "disabled";
};
&main_mcan6 {
status = "disabled";
};
&main_mcan7 {
status = "disabled";
};
&main_mcan8 {
status = "disabled";
};
&main_mcan9 {
status = "disabled";
};
&main_mcan10 {
status = "disabled";
};
&main_mcan11 {
status = "disabled";
};
&main_mcan12 {
status = "disabled";
};
&main_mcan13 {
status = "disabled";
};
&main_mcan14 {
status = "disabled";
};
&main_mcan15 {
status = "disabled";
};
&main_mcan17 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family Main Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x400000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
l3cache-sram@200000 {
reg = <0x200000 0x200000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
ti,interrupt-ranges = <8 360 56>;
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x200>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x200>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x200>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x200>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x200>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x200>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x200>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x200>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <145>, <146>, <147>, <148>, <149>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00610000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <154>, <155>, <156>, <157>, <158>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00620000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <163>, <164>, <165>, <166>, <167>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00630000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <172>, <173>, <174>, <175>, <176>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 214 1>;
clock-names = "fck";
power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02010000 0x00 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02020000 0x00 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02030000 0x00 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02040000 0x00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02050000 0x00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02060000 0x00 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
};
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
<0x00 0x04f88000 0x00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 98 1>;
assigned-clock-parents = <&k3_clks 98 2>;
bus-width = <8>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
};
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x00 0x04fb0000 0x00 0x1000>,
<0x00 0x04fb8000 0x00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 99 1>;
assigned-clock-parents = <&k3_clks 99 2>;
bus-width = <4>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
/* Masking support for SDR104 capability */
// sdhci-caps-mask = <0x00000003 0x00000000>;
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <224>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <227>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x00 0x33d00000 0x00 0x100000>;
interrupt-controller;
#interrupt-cells = <0>;
interrupt-parent = <&main_navss_intr>;
msi-controller;
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
};
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f80000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster1: mailbox@31f81000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f81000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster2: mailbox@31f82000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f82000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster3: mailbox@31f83000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f83000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster4: mailbox@31f84000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f84000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster5: mailbox@31f85000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f85000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster6: mailbox@31f86000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f86000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster7: mailbox@31f87000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f87000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster8: mailbox@31f88000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f88000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster9: mailbox@31f89000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f89000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster10: mailbox@31f8a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster11: mailbox@31f8b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster0: mailbox@31f90000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f90000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster1: mailbox@31f91000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f91000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster2: mailbox@31f92000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f92000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster3: mailbox@31f93000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f93000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster4: mailbox@31f94000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f94000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster5: mailbox@31f95000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f95000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster6: mailbox@31f96000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f96000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster7: mailbox@31f97000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f97000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster8: mailbox@31f98000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f98000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster9: mailbox@31f99000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f99000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster10: mailbox@31f9a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster11: mailbox@31f9b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <259>;
msi-parent = <&main_udmass_inta>;
};
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x80000>,
<0x0 0x35000000 0x0 0x200000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <263>;
ti,ringacc = <&main_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>, /* TX_HCHAN */
<0x10>; /* TX_UHCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>, /* RX_HCHAN */
<0x0c>; /* RX_UHCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
};
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
<0x00 0x02708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan1: can@2711000 {
compatible = "bosch,m_can";
reg = <0x00 0x02711000 0x00 0x200>,
<0x00 0x02718000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan2: can@2721000 {
compatible = "bosch,m_can";
reg = <0x00 0x02721000 0x00 0x200>,
<0x00 0x02728000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan3: can@2731000 {
compatible = "bosch,m_can";
reg = <0x00 0x02731000 0x00 0x200>,
<0x00 0x02738000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan4: can@2741000 {
compatible = "bosch,m_can";
reg = <0x00 0x02741000 0x00 0x200>,
<0x00 0x02748000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan5: can@2751000 {
compatible = "bosch,m_can";
reg = <0x00 0x02751000 0x00 0x200>,
<0x00 0x02758000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan6: can@2761000 {
compatible = "bosch,m_can";
reg = <0x00 0x02761000 0x00 0x200>,
<0x00 0x02768000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan7: can@2771000 {
compatible = "bosch,m_can";
reg = <0x00 0x02771000 0x00 0x200>,
<0x00 0x02778000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan8: can@2781000 {
compatible = "bosch,m_can";
reg = <0x00 0x02781000 0x00 0x200>,
<0x00 0x02788000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan9: can@2791000 {
compatible = "bosch,m_can";
reg = <0x00 0x02791000 0x00 0x200>,
<0x00 0x02798000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan10: can@27a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027a1000 0x00 0x200>,
<0x00 0x027a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan11: can@27b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027b1000 0x00 0x200>,
<0x00 0x027b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan12: can@27c1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027c1000 0x00 0x200>,
<0x00 0x027c8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan13: can@27d1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027d1000 0x00 0x200>,
<0x00 0x027d8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan14: can@2681000 {
compatible = "bosch,m_can";
reg = <0x00 0x02681000 0x00 0x200>,
<0x00 0x02688000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan15: can@2691000 {
compatible = "bosch,m_can";
reg = <0x00 0x02691000 0x00 0x200>,
<0x00 0x02698000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan16: can@26a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026a1000 0x00 0x200>,
<0x00 0x026a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan17: can@26b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026b1000 0x00 0x200>,
<0x00 0x026b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
sms: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
ranges = <0x00 0x00 0x41c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
ti,interrupt-ranges = <16 928 16>;
};
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x200>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
};
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 115 0>;
clock-names = "gpio";
};
wkup_gpio1: gpio@42100000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 116 0>;
clock-names = "gpio";
};
wkup_i2c0: i2c@42120000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x42120000 0x00 0x100>;
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b00000 0x00 0x100>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
};
mcu_i2c1: i2c@40b10000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b10000 0x00 0x100>;
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
};
mcu_mcan0: can@40528000 {
compatible = "bosch,m_can";
reg = <0x00 0x40528000 0x00 0x200>,
<0x00 0x40500000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
mcu_mcan1: can@40568000 {
compatible = "bosch,m_can";
reg = <0x00 0x40568000 0x00 0x200>,
<0x00 0x40540000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
mcu_navss: bus@28380000{
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <267>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <272>;
msi-parent = <&main_udmass_inta>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <273>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>; /* TX_HCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x46000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
dma-coherent;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
dmas = <&mcu_udmap 0xf000>,
<&mcu_udmap 0xf001>,
<&mcu_udmap 0xf002>,
<&mcu_udmap 0xf003>,
<&mcu_udmap 0xf004>,
<&mcu_udmap 0xf005>,
<&mcu_udmap 0xf006>,
<&mcu_udmap 0xf007>,
<&mcu_udmap 0x7000>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
phys = <&phy_gmii_sel 1>;
};
};
davinci_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j721s2-som-p0.dtsi"
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
/ {
chosen {
firmware-loader = &fs_loader0;
stdout-path = &main_uart8;
tick-timer = &timer1;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
fs_loader0: fs_loader@0 {
compatible = "u-boot,fs-loader";
u-boot,dm-pre-reloc;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <2000000000>;
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
u-boot,dm-spl;
};
};
&cbass_mcu_wakeup {
sa3_secproxy: secproxy@44880000 {
u-boot,dm-spl;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x44880000 0x0 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
};
mcu_secproxy: secproxy@2a380000 {
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
u-boot,dm-spl;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
mbox-names = "tx", "rx", "boot_notify";
u-boot,dm-spl;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
};
};
&wkup_pmx0 {
mcu_uart0_pins_default: mcu-uart0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
wkup_uart0_pins_default: wkup-uart0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
};
};
&sms {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
u-boot,dm-spl;
};
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
};
&main_sdhci0 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
non-removable;
bus-width = <8>;
};
&main_sdhci1 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
ti,driver-strength-ohm = <50>;
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
#include "k3-j721s2-common-proc-board-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j721s2.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
memory@80000000 {
device_type = "memory";
/* 16 GB RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x03 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
};
transceiver0: can-phy0 {
/* standby pin has been grounded by default */
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
>;
};
main_mcan16_pins_default: main-mcan16-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
>;
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
exp_som: gpio@21 {
compatible = "ti,tca6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
"GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
"GPIO_LIN_EN", "CAN_STB";
};
};
&main_mcan16 {
pinctrl-0 = <&main_mcan16_pins_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
&mailbox0_cluster0 {
status = "disabled";
};
&mailbox0_cluster1 {
status = "disabled";
};
&mailbox0_cluster2 {
status = "disabled";
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "disabled";
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&mailbox0_cluster8 {
status = "disabled";
};
&mailbox0_cluster9 {
status = "disabled";
};
&mailbox0_cluster10 {
status = "disabled";
};
&mailbox0_cluster11 {
status = "disabled";
};
&mailbox1_cluster0 {
status = "disabled";
};
&mailbox1_cluster1 {
status = "disabled";
};
&mailbox1_cluster2 {
status = "disabled";
};
&mailbox1_cluster3 {
status = "disabled";
};
&mailbox1_cluster4 {
status = "disabled";
};
&mailbox1_cluster5 {
status = "disabled";
};
&mailbox1_cluster6 {
status = "disabled";
};
&mailbox1_cluster7 {
status = "disabled";
};
&mailbox1_cluster8 {
status = "disabled";
};
&mailbox1_cluster9 {
status = "disabled";
};
&mailbox1_cluster10 {
status = "disabled";
};
&mailbox1_cluster11 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family
*
* TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J721S2 SoC";
compatible = "ti,j721s2";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a72_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
};
/* Now include peripherals from each bus segment */
#include "k3-j721s2-main.dtsi"
#include "k3-j721s2-mcu-wakeup.dtsi"

3
arch/arm/include/asm/arch-omap5/clock.h
View File

@ -135,6 +135,9 @@
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */
#define IPU1_CLKCTRL_CLKSEL_MASK BIT(24)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)

10
arch/arm/include/asm/omap_common.h
View File

@ -362,6 +362,10 @@ struct prcm_regs {
/* IPU */
u32 cm_ipu_clkstctrl;
u32 cm_ipu_i2c5_clkctrl;
u32 cm_ipu1_clkstctrl;
u32 cm_ipu1_ipu1_clkctrl;
u32 cm_ipu2_clkstctrl;
u32 cm_ipu2_ipu2_clkctrl;
/*l3main1 edma*/
u32 cm_l3main1_tptc1_clkctrl;
@ -632,6 +636,12 @@ void do_disable_clocks(u32 const *clk_domains,
u8 wait_for_disable);
#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
void do_enable_ipu_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
void enable_ipu1_clocks(void);
void enable_ipu2_clocks(void);
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);

15
arch/arm/mach-k3/Kconfig
View File

@ -10,6 +10,9 @@ config SOC_K3_AM6
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
config SOC_K3_J721S2
bool "TI's K3 based J721S2 SoC Family Support"
config SOC_K3_AM642
bool "TI's K3 based AM642 SoC Family Support"
@ -21,7 +24,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E
default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c0000 if SOC_K3_AM642
help
Describes the total size of the MCU or OCMC MSRAM present on
@ -32,7 +35,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E
default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x180000 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
@ -41,14 +44,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
default 0x40280000 if SOC_K3_J721E
default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
default 0x200 if SOC_K3_J721E
default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
help
Describes the size of MCU Scratchpad RAM.
@ -56,6 +59,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
@ -156,7 +160,7 @@ config K3_ATF_LOAD_ADDR
config K3_DM_FW
bool "Separate DM firmware image"
depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@ -169,4 +173,5 @@ source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
source "board/ti/j721s2/Kconfig"
endif

1
arch/arm/mach-k3/Makefile
View File

@ -5,6 +5,7 @@
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o

41
arch/arm/mach-k3/arm64-mmu.c
View File

@ -181,6 +181,47 @@ struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_SOC_K3_J721E */
#ifdef CONFIG_SOC_K3_J721S2
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
/* ToDo: Add 64bit IO */
struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721s2_mem_map;
#endif /* CONFIG_SOC_K3_J721S2 */
#ifdef CONFIG_SOC_K3_AM642
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)

10
arch/arm/mach-k3/common.c
View File

@ -156,13 +156,15 @@ void init_env(void)
#endif
}
#ifdef CONFIG_FS_LOADER
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
{
struct udevice *fsdev;
char *name = NULL;
int size = 0;
if (!IS_ENABLED(CONFIG_FS_LOADER))
return 0;
*loadaddr = 0;
#ifdef CONFIG_SPL_ENV_SUPPORT
switch (spl_boot_device()) {
@ -186,12 +188,6 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
return size;
}
#else
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
{
return 0;
}
#endif
__weak void release_resources_for_core_shutdown(void)
{

4
arch/arm/mach-k3/include/mach/hardware.h
View File

@ -14,6 +14,10 @@
#include "j721e_hardware.h"
#endif
#ifdef CONFIG_SOC_K3_J721S2
#include "j721s2_hardware.h"
#endif
#ifdef CONFIG_SOC_K3_AM642
#include "am64_hardware.h"
#endif

60
arch/arm/mach-k3/include/mach/j721s2_hardware.h Normal file
View File

@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* K3: J721S2 SoC definitions, structures etc.
*
* (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#ifndef __ASM_ARCH_J721S2_HARDWARE_H
#define __ASM_ARCH_J721S2_HARDWARE_H
#include <config.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
#define CTRL_MMR0_BASE 0x00100000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
#define WKUP_CTRL_MMR0_BASE 0x43000000
#define MCU_CTRL_MMR0_BASE 0x40f00000
#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
/*
* The CTRL_MMR0 memory space is divided into several equally-spaced
* partitions, so defining the partition size allows us to determine
* register addresses common to those partitions.
*/
#define CTRL_MMR0_PARTITION_SIZE 0x4000
/*
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
* shared register definitions.
*/
#define CTRLMMR_LOCK_KICK0 0x01008
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
/* ROM HANDOFF Structure location */
#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00
/* MCU SCRATCHPAD usage */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
#endif /* __ASM_ARCH_J721S2_HARDWARE_H */

46
arch/arm/mach-k3/include/mach/j721s2_spl.h Normal file
View File

@ -0,0 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* David Huang <d-huang@ti.com>
*/
#ifndef _ASM_ARCH_J721S2_SPL_H_
#define _ASM_ARCH_J721S2_SPL_H_
/* With BootMode B = 0 */
#include <linux/bitops.h>
#define BOOT_DEVICE_HYPERFLASH 0x00
#define BOOT_DEVICE_OSPI 0x01
#define BOOT_DEVICE_QSPI 0x02
#define BOOT_DEVICE_SPI 0x03
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
/* With BootMode B = 1 */
#define BOOT_DEVICE_MMC2 0x10
#define BOOT_DEVICE_MMC1 0x11
#define BOOT_DEVICE_DFU 0x12
#define BOOT_DEVICE_UFS 0x13
#define BOOT_DEVIE_GPMC 0x14
#define BOOT_DEVICE_PCIE 0x15
#define BOOT_DEVICE_XSPI 0x16
#define BOOT_DEVICE_RAM 0x17
#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */
/* Backup boot modes with MCU Only = 0 */
#define BACKUP_BOOT_DEVICE_RAM 0x0
#define BACKUP_BOOT_DEVICE_USB 0x1
#define BACKUP_BOOT_DEVICE_UART 0x3
#define BACKUP_BOOT_DEVICE_ETHERNET 0x4
#define BACKUP_BOOT_DEVICE_MMC2 0x5
#define BACKUP_BOOT_DEVICE_SPI 0x6
#define BACKUP_BOOT_DEVICE_I2C 0x7
#define BOOT_MODE_B_SHIFT 4
#define BOOT_MODE_B_MASK BIT(4)
#define K3_PRIMARY_BOOTMODE 0x0
#define K3_BACKUP_BOOTMODE 0x1
#endif

4
arch/arm/mach-k3/include/mach/spl.h
View File

@ -14,6 +14,10 @@
#include "j721e_spl.h"
#endif
#ifdef CONFIG_SOC_K3_J721S2
#include "j721s2_spl.h"
#endif
#ifdef CONFIG_SOC_K3_AM642
#include "am64_spl.h"
#endif

5
arch/arm/mach-k3/j721s2/Makefile Normal file
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o

403
arch/arm/mach-k3/j721s2/clk-data.c Normal file
View File

@ -0,0 +1,403 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721S2 specific clock platform data
*
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
#include "k3-clk.h"
static const char * const gluelogic_hfosc0_clkout_parents[] = {
"osc_19_2_mhz",
"osc_20_mhz",
"osc_24_mhz",
"osc_25_mhz",
"osc_26_mhz",
"osc_27_mhz",
};
static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
"board_0_mcu_ospi0_dqs_out",
"fss_mcu_0_ospi_0_ospi_oclk_clk",
};
static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
"board_0_mcu_ospi1_dqs_out",
"fss_mcu_0_ospi_1_ospi_oclk_clk",
};
static const char * const wkup_fref_clksel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
NULL,
};
static const char * const main_pll_hfosc_sel_out1_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
"wkup_fref_clksel_out0",
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
};
static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
static const char * const mcu_usart_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv3_16fft_main_1_hsdivout5_clk",
};
static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"gluelogic_hfosc0_clkout",
};
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out12_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out19_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out2_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out3_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out7_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out8_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const usb0_refclk_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const emmcsd1_lb_clksel_out0_parents[] = {
"board_0_mmc1_clklb_out",
"board_0_mmc1_clk_out",
};
static const char * const mcu_clkout_mux_out0_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
};
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
"main_pll_hfosc_sel_out0",
"hsdiv4_16fft_main_0_hsdivout0_clk",
};
static const char * const dpi0_ext_clksel_out0_parents[] = {
"hsdiv1_16fft_main_19_hsdivout0_clk",
"board_0_vout0_extpclkin_out",
};
static const char * const emmcsd_refclk_sel_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const emmcsd_refclk_sel_out1_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const gtc_clk_mux_out0_parents[] = {
"hsdiv4_16fft_main_3_hsdivout1_clk",
"postdiv3_16fft_main_0_hsdivout6_clk",
"board_0_mcu_cpts0_rft_clk_out",
"board_0_cpts0_rft_clk_out",
"board_0_mcu_ext_refclk0_out",
"board_0_ext_refclk1_out",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0),
CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0),
CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0),
CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0),
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0),
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0),
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
};
static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
DEV_CLK(43, 3, "board_0_hfosc1_clk_out"),
DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(43, 7, "board_0_hfosc1_clk_out"),
DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"),
DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"),
DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(61, 1, "gtc_clk_mux_out0"),
DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"),
DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"),
DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"),
DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"),
DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"),
DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"),
DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"),
DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"),
DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"),
DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(138, 3, "board_0_ddr0_ckn_out"),
DEV_CLK(138, 5, "board_0_ddr0_ckp_out"),
DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"),
DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(139, 3, "board_0_ddr1_ckn_out"),
DEV_CLK(139, 5, "board_0_ddr1_ckp_out"),
DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"),
DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(149, 3, "mcu_usart_clksel_out0"),
DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"),
DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"),
DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"),
DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"),
DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"),
DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(360, 16, "usb0_refclk_sel_out0"),
DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"),
DEV_CLK(360, 18, "board_0_hfosc1_clk_out"),
DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
.clk_list = clk_list,
.clk_list_cnt = 104,
.soc_dev_clk_data = soc_dev_clk_data,
.soc_dev_clk_data_cnt = 122,
};

85
arch/arm/mach-k3/j721s2/dev-data.c Normal file
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@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721S2 specific device platform data
*
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
static struct ti_psc soc_psc_list[] = {
[0] = PSC(0, 0x42000000),
[1] = PSC(1, 0x00400000),
};
static struct ti_pd soc_pd_list[] = {
[0] = PSC_PD(0, &soc_psc_list[0], NULL),
[1] = PSC_PD(0, &soc_psc_list[1], NULL),
[2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]),
[3] = PSC_PD(14, &soc_psc_list[1], NULL),
[4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]),
[5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]),
};
static struct ti_lpsc soc_lpsc_list[] = {
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
[1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL),
[2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL),
[3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL),
[4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL),
[5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL),
[6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]),
[7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
[8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL),
[9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]),
[10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL),
[11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
[12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
[13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
[14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL),
[15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL),
[16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL),
[17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]),
[18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]),
};
static struct ti_dev soc_dev_list[] = {
PSC_DEV(108, &soc_lpsc_list[0]),
PSC_DEV(109, &soc_lpsc_list[0]),
PSC_DEV(110, &soc_lpsc_list[0]),
PSC_DEV(180, &soc_lpsc_list[0]),
PSC_DEV(149, &soc_lpsc_list[0]),
PSC_DEV(115, &soc_lpsc_list[1]),
PSC_DEV(223, &soc_lpsc_list[1]),
PSC_DEV(109, &soc_lpsc_list[2]),
PSC_DEV(110, &soc_lpsc_list[3]),
PSC_DEV(108, &soc_lpsc_list[4]),
PSC_DEV(43, &soc_lpsc_list[5]),
PSC_DEV(61, &soc_lpsc_list[6]),
PSC_DEV(96, &soc_lpsc_list[7]),
PSC_DEV(138, &soc_lpsc_list[8]),
PSC_DEV(97, &soc_lpsc_list[9]),
PSC_DEV(139, &soc_lpsc_list[10]),
PSC_DEV(360, &soc_lpsc_list[11]),
PSC_DEV(99, &soc_lpsc_list[12]),
PSC_DEV(98, &soc_lpsc_list[13]),
PSC_DEV(146, &soc_lpsc_list[14]),
PSC_DEV(357, &soc_lpsc_list[15]),
PSC_DEV(4, &soc_lpsc_list[16]),
PSC_DEV(202, &soc_lpsc_list[17]),
PSC_DEV(203, &soc_lpsc_list[18]),
};
const struct ti_k3_pd_platdata j721s2_pd_platdata = {
.psc = soc_psc_list,
.pd = soc_pd_list,
.lpsc = soc_lpsc_list,
.devs = soc_dev_list,
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 19,
.num_devs = 24,
};

312
arch/arm/mach-k3/j721s2_init.c Normal file
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@ -0,0 +1,312 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721E: SoC specific initialization
*
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* David Huang <d-huang@ti.com>
*/
#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/armv7_mpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sysfw-loader.h>
#include "common.h"
#include <asm/arch/sys_proto.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#include <mmc.h>
#include <remoteproc.h>
#ifdef CONFIG_SPL_BUILD
static void ctrl_mmr_unlock(void)
{
/* Unlock all WKUP_CTRL_MMR0 module registers */
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
/* Unlock all MCU_CTRL_MMR0 module registers */
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
/* Unlock all CTRL_MMR0 module registers */
mmr_unlock(CTRL_MMR0_BASE, 0);
mmr_unlock(CTRL_MMR0_BASE, 1);
mmr_unlock(CTRL_MMR0_BASE, 2);
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 7);
}
void k3_mmc_stop_clock(void)
{
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
struct mmc *mmc = find_mmc_device(0);
if (!mmc)
return;
mmc->saved_clock = mmc->clock;
mmc_set_clock(mmc, 0, true);
}
}
}
void k3_mmc_restart_clock(void)
{
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
struct mmc *mmc = find_mmc_device(0);
if (!mmc)
return;
mmc_set_clock(mmc, mmc->saved_clock, false);
}
}
}
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
* it to the .data section.
*/
u32 bootindex __attribute__((section(".data")));
static struct rom_extended_boot_data bootdata __section(".data");
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
sizeof(struct rom_extended_boot_data));
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
/*
* Cannot delay this further as there is a chance that
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
*/
store_boot_info_from_rom();
/* Make all control module registers accessible */
ctrl_mmr_unlock();
if (IS_ENABLED(CONFIG_CPU_V7R)) {
disable_linefill_optimization();
setup_k3_mpu_regions();
}
/* Init DM early */
spl_early_init();
/* Prepare console output */
preloader_console_init();
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
/*
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
* regardless of the result of pinctrl. Do this without probing the
* device, but instead by searching the device that would request the
* given sequence number if probed. The UART will be used by the system
* firmware (SYSFW) image for various purposes and SYSFW depends on us
* to initialize its pin settings.
*/
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
if (!ret)
pinctrl_select_state(dev, "default");
/*
* Load, start up, and configure system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
* output.
*/
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
k3_mmc_stop_clock, k3_mmc_restart_clock);
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done for enabling PM services.
*/
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(ti_clk),
&dev);
if (ret)
panic("Failed to initialize clk-k3!\n");
}
}
/* Output System Firmware version info */
k3_sysfw_print_ver();
if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
if (ret)
panic("Probe of msmc failed: %d\n", ret);
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("DRAM 0 init failed: %d\n", ret);
ret = uclass_next_device(&dev);
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
spl_enable_dcache();
}
u32 spl_mmc_boot_mode(const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
return MMCSD_MODE_RAW;
}
}
static u32 __get_backup_bootmedia(u32 main_devstat)
{
u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
switch (bkup_boot) {
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC2:
{
u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
if (port == 0x0)
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_MMC2;
}
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
}
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
{
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
BOOT_MODE_B_SHIFT;
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
bootmode == BOOT_DEVICE_XSPI)
bootmode = BOOT_DEVICE_SPI;
if (bootmode == BOOT_DEVICE_MMC2) {
u32 port = (main_devstat &
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
if (port == 0x0)
bootmode = BOOT_DEVICE_MMC1;
}
return bootmode;
}
u32 spl_boot_device(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
u32 main_devstat;
if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
printf("ERROR: MCU only boot is not yet supported\n");
return BOOT_DEVICE_RAM;
}
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
if (bootindex == K3_PRIMARY_BOOTMODE)
return __get_primary_bootmedia(main_devstat, wkup_devstat);
else
return __get_backup_bootmedia(main_devstat);
}
#endif
#define J721S2_DEV_MCU_RTI0 295
#define J721S2_DEV_MCU_RTI1 296
#define J721S2_DEV_MCU_ARMSS0_CPU0 284
#define J721S2_DEV_MCU_ARMSS0_CPU1 285
void release_resources_for_core_shutdown(void)
{
if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
struct ti_sci_handle *ti_sci;
struct ti_sci_dev_ops *dev_ops;
struct ti_sci_proc_ops *proc_ops;
int ret;
u32 i;
const u32 put_device_ids[] = {
J721S2_DEV_MCU_RTI0,
J721S2_DEV_MCU_RTI1,
};
ti_sci = get_ti_sci_handle();
dev_ops = &ti_sci->ops.dev_ops;
proc_ops = &ti_sci->ops.proc_ops;
/* Iterate through list of devices to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
u32 id = put_device_ids[i];
ret = dev_ops->put_device(ti_sci, id);
if (ret)
panic("Failed to put device %u (%d)\n", id, ret);
}
const u32 put_core_ids[] = {
J721S2_DEV_MCU_ARMSS0_CPU1,
J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
};
/* Iterate through list of cores to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
u32 id = put_core_ids[i];
/*
* Queue up the core shutdown request. Note that this call
* needs to be followed up by an actual invocation of an WFE
* or WFI CPU instruction.
*/
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
if (ret)
panic("Failed sending core %u shutdown message (%d)\n",
id, ret);
}
}
}

95
arch/arm/mach-omap2/boot-common.c
View File

@ -10,6 +10,8 @@
#include <common.h>
#include <ahci.h>
#include <log.h>
#include <dm/uclass.h>
#include <fs_loader.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/omap_common.h>
@ -19,9 +21,14 @@
#include <watchdog.h>
#include <scsi.h>
#include <i2c.h>
#include <remoteproc.h>
DECLARE_GLOBAL_DATA_PTR;
#define IPU1_LOAD_ADDR (0xa17ff000)
#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
__weak u32 omap_sys_boot_device(void)
{
return BOOT_DEVICE_NONE;
@ -194,6 +201,91 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
return gd->arch.omap_boot_mode;
}
int load_firmware(char *name_fw, u32 *loadaddr)
{
struct udevice *fsdev;
int size = 0;
if (!IS_ENABLED(CONFIG_FS_LOADER))
return 0;
if (!*loadaddr)
return 0;
if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
size = request_firmware_into_buf(fsdev, name_fw,
(void *)*loadaddr, 0, 0);
}
return size;
}
void spl_boot_ipu(void)
{
int ret, size;
u32 loadaddr = IPU1_LOAD_ADDR;
if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
return;
size = load_firmware("dra7-ipu1-fw.xem4", &loadaddr);
if (size <= 0) {
pr_err("Firmware loading failed\n");
goto skip_ipu1;
}
enable_ipu1_clocks();
ret = rproc_dev_init(0);
if (ret) {
debug("%s: IPU1 failed to initialize on rproc (%d)\n",
__func__, ret);
goto skip_ipu1;
}
ret = rproc_load(0, IPU1_LOAD_ADDR, 0x2000000);
if (ret) {
debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
ret);
goto skip_ipu1;
}
debug("Starting IPU1...\n");
ret = rproc_start(0);
if (ret)
debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
skip_ipu1:
loadaddr = IPU2_LOAD_ADDR;
size = load_firmware("dra7-ipu2-fw.xem4", &loadaddr);
if (size <= 0) {
pr_err("Firmware loading failed for ipu2\n");
return;
}
enable_ipu2_clocks();
ret = rproc_dev_init(1);
if (ret) {
debug("%s: IPU2 failed to initialize on rproc (%d)\n", __func__,
ret);
return;
}
ret = rproc_load(1, IPU2_LOAD_ADDR, 0x2000000);
if (ret) {
debug("%s: IPU2 failed to load on rproc (%d)\n", __func__,
ret);
return;
}
debug("Starting IPU2...\n");
ret = rproc_start(1);
if (ret)
debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
}
void spl_board_init(void)
{
/* Prepare console output */
@ -214,6 +306,9 @@ void spl_board_init(void)
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
spl_boot_ipu();
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)

33
arch/arm/mach-omap2/clocks-common.c
View File

@ -858,6 +858,39 @@ void do_enable_clocks(u32 const *clk_domains,
}
}
void do_enable_ipu_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable)
{
u32 i, max = 10;
if (!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
return;
/* Put the clock domains in SW_WKUP mode */
for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
/* Clock modules that need to be put in HW_AUTO */
for (i = 0; (i < max) && clk_modules_hw_auto &&
clk_modules_hw_auto[i]; i++) {
enable_clock_module(clk_modules_hw_auto[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
};
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
for (i = 0; (i < max) && clk_modules_explicit_en &&
clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
};
}
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable)

92
arch/arm/mach-omap2/omap5/hw_data.c
View File

@ -376,6 +376,85 @@ struct vcores_data omap5430_volts_es2 = {
.mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
};
/*
* Enable IPU1 clock domains, modules and
* do some additional special settings needed
*/
void enable_ipu1_clocks(void)
{
if (!IS_ENABLED(CONFIG_DRA7XX) ||
!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
return;
u32 const clk_domains[] = {
(*prcm)->cm_ipu_clkstctrl,
(*prcm)->cm_ipu1_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_ipu1_ipu1_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
0
};
do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential, 0);
/* Enable optional additional functional clock for IPU1 */
setbits_le32((*prcm)->cm_ipu1_ipu1_clkctrl,
IPU1_CLKCTRL_CLKSEL_MASK);
/* Enable optional additional functional clock for IPU1 */
setbits_le32((*prcm)->cm1_abe_timer7_clkctrl,
IPU1_CLKCTRL_CLKSEL_MASK);
/* Enable optional additional functional clock for IPU1 */
setbits_le32((*prcm)->cm1_abe_timer8_clkctrl,
IPU1_CLKCTRL_CLKSEL_MASK);
}
/*
* Enable IPU2 clock domains, modules and
* do some additional special settings needed
*/
void enable_ipu2_clocks(void)
{
if (!IS_ENABLED(CONFIG_DRA7XX) ||
!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
return;
u32 const clk_domains[] = {
(*prcm)->cm_ipu_clkstctrl,
(*prcm)->cm_ipu2_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_ipu2_ipu2_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
0
};
do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential, 0);
/* Enable optional additional functional clock for IPU2 */
setbits_le32((*prcm)->cm_l4per_gptimer4_clkctrl,
IPU1_CLKCTRL_CLKSEL_MASK);
/* Enable optional additional functional clock for IPU2 */
setbits_le32((*prcm)->cm_l4per_gptimer9_clkctrl,
IPU1_CLKCTRL_CLKSEL_MASK);
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@ -478,12 +557,13 @@ void enable_basic_clocks(void)
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
#if defined(CONFIG_DRA7XX)
(*prcm)->cm_ipu_clkstctrl,
#endif
0
};
u32 cm_ipu_clkstctrl = 0;
if (IS_ENABLED(CONFIG_DRA7XX) &&
!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
cm_ipu_clkstctrl = (*prcm)->cm_ipu_clkstctrl;
u32 const clk_domains_essential[] = {cm_ipu_clkstctrl, 0};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbtll_clkctrl,

9
arch/arm/mach-omap2/omap5/prcm-regs.c
View File

@ -832,7 +832,10 @@ struct prcm_regs const dra7xx_prcm = {
/* cm IPU */
.cm_ipu_clkstctrl = 0x4a005540,
.cm_ipu_i2c5_clkctrl = 0x4a005578,
.cm_ipu1_clkstctrl = 0x4a005500,
.cm_ipu1_ipu1_clkctrl = 0x4a005520,
.cm_ipu2_clkstctrl = 0x4a008900,
.cm_ipu2_ipu2_clkctrl = 0x4a008920,
/* prm irqstatus regs */
.prm_irqstatus_mpu = 0x4ae06010,
.prm_irqstatus_mpu_2 = 0x4ae06014,
@ -1013,6 +1016,10 @@ struct prcm_regs const dra7xx_prcm = {
/*l3main1 edma*/
.cm_l3main1_tptc1_clkctrl = 0x4a008778,
.cm_l3main1_tptc2_clkctrl = 0x4a008780,
/* cm1.abe */
.cm1_abe_timer7_clkctrl = 0x4a005568,
.cm1_abe_timer8_clkctrl = 0x4a005570,
};
void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)

37
board/nokia/rx51/rx51.c
View File

@ -31,6 +31,7 @@
#include <twl4030.h>
#include <i2c.h>
#include <video_fb.h>
#include <keyboard.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/setup.h>
@ -579,10 +580,10 @@ static u8 keybuf_head;
static u8 keybuf_tail;
/*
* Routine: rx51_kp_init
* Routine: rx51_kp_start
* Description: Initialize HW keyboard.
*/
int rx51_kp_init(void)
static int rx51_kp_start(struct udevice *dev)
{
int ret = 0;
u8 ctrl;
@ -656,7 +657,7 @@ static void rx51_kp_fill(u8 k, u8 mods)
* Routine: rx51_kp_tstc
* Description: Test if key was pressed (from buffer).
*/
int rx51_kp_tstc(struct stdio_dev *sdev)
static int rx51_kp_tstc(struct udevice *dev)
{
u8 c, r, dk, i;
u8 intr;
@ -712,14 +713,36 @@ int rx51_kp_tstc(struct stdio_dev *sdev)
* Routine: rx51_kp_getc
* Description: Get last pressed key (from buffer).
*/
int rx51_kp_getc(struct stdio_dev *sdev)
static int rx51_kp_getc(struct udevice *dev)
{
keybuf_head %= KEYBUF_SIZE;
while (!rx51_kp_tstc(sdev))
while (!rx51_kp_tstc(dev))
WATCHDOG_RESET();
return keybuf[keybuf_head++];
}
static int rx51_kp_probe(struct udevice *dev)
{
struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
struct stdio_dev *sdev = &uc_priv->sdev;
strcpy(sdev->name, "keyboard");
return input_stdio_register(sdev);
}
static const struct keyboard_ops rx51_kp_ops = {
.start = rx51_kp_start,
.tstc = rx51_kp_tstc,
.getc = rx51_kp_getc,
};
U_BOOT_DRIVER(rx51_kp) = {
.name = "rx51_kp",
.id = UCLASS_KEYBOARD,
.probe = rx51_kp_probe,
.ops = &rx51_kp_ops,
};
static const struct mmc_config rx51_mmc_cfg = {
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
.f_min = 400000,
@ -753,3 +776,7 @@ U_BOOT_DRVINFOS(rx51_i2c) = {
U_BOOT_DRVINFOS(rx51_watchdog) = {
{ "rx51_watchdog" },
};
U_BOOT_DRVINFOS(rx51_kp) = {
{ "rx51_kp" },
};

37
board/ti/j721e/evm.c
View File

@ -413,6 +413,40 @@ void configure_serdes_torrent(void)
printf("phy_power_on failed !!\n");
}
void configure_serdes_sierra(void)
{
struct udevice *dev, *lnk_dev;
struct phy serdes;
int ret, count, i;
if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
return;
ret = uclass_get_device_by_driver(UCLASS_PHY,
DM_DRIVER_GET(sierra_phy_provider),
&dev);
if (ret)
printf("Sierra init failed:%d\n", ret);
serdes.dev = dev;
serdes.id = 0;
count = device_get_child_count(dev);
for (i = 0; i < count; i++) {
ret = device_get_child(dev, i, &lnk_dev);
if (ret)
printf("probe of sierra child node %d failed\n", i);
}
ret = generic_phy_init(&serdes);
if (ret)
printf("phy_init failed!!\n");
ret = generic_phy_power_on(&serdes);
if (ret)
printf("phy_power_on failed !!\n");
}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@ -426,6 +460,9 @@ int board_late_init(void)
if (board_is_j7200_som())
configure_serdes_torrent();
if (board_is_j721e_som())
configure_serdes_sierra();
return 0;
}

63
board/ti/j721s2/Kconfig Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
# David Huang <d-huang@ti.com>
choice
prompt "K3 J721S2 board"
optional
config TARGET_J721S2_A72_EVM
bool "TI K3 based J721S2 EVM running on A72"
select ARM64
select SOC_K3_J721S2
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
config TARGET_J721S2_R5_EVM
bool "TI K3 based J721S2 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select SOC_K3_J721S2
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
if TARGET_J721S2_A72_EVM
config SYS_BOARD
default "j721s2"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "j721s2_evm"
source "board/ti/common/Kconfig"
endif
if TARGET_J721S2_R5_EVM
config SYS_BOARD
default "j721s2"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "j721s2_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

16
board/ti/j721s2/MAINTAINERS Normal file
View File

@ -0,0 +1,16 @@
J721S2 BOARD
M: Aswath Govindraju <a-govindraju@ti.com>
S: Maintained
F: board/ti/j721s2
F: include/configs/j721s2_evm.h
F: configs/j721s2_evm_r5_defconfig
F: configs/j721s2_evm_a72_defconfig
F: arch/arm/dts/k3-j721s2.dtsi
F: arch/arm/dts/k3-j721s2-main.dtsi
F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
F: arch/arm/dts/k3-j721s2-som-p0.dtsi
F: arch/arm/dts/k3-j721s2-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-ddr.dtsi
F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi

8
board/ti/j721s2/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
# David Huang <d-huang@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evm.o

180
board/ti/j721s2/evm.c Normal file
View File

@ -0,0 +1,180 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board specific initialization for J721S2 EVM
*
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
* David Huang <d-huang@ti.com>
*
*/
#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include "../common/board_detect.h"
#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
if (gd->ram_top > 0x100000000)
return 0x100000000;
#endif
return gd->ram_top;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (!strcmp(name, "k3-j721s2-common-proc-board"))
return 0;
return -1;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
int ret;
ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
if (ret < 0)
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
"sram@70000000");
if (ret)
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
return ret;
}
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
int do_board_detect(void)
{
int ret;
ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (ret)
pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
CONFIG_EEPROM_CHIP_ADDRESS, ret);
return ret;
}
int checkboard(void)
{
struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
if (do_board_detect())
/* EEPROM not populated */
printf("Board: %s rev %s\n", "J721S2X-PM1-SOM", "E1");
else
printf("Board: %s rev %s\n", ep->name, ep->version);
return 0;
}
static void setup_board_eeprom_env(void)
{
char *name = "j721s2";
if (do_board_detect())
goto invalid_eeprom;
if (board_is_j721s2_som())
name = "j721s2";
else
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
invalid_eeprom:
set_board_info_env_am6(name);
}
static void setup_serial(void)
{
struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
unsigned long board_serial;
char *endp;
char serial_string[17] = { 0 };
if (env_get("serial#"))
return;
board_serial = simple_strtoul(ep->serial, &endp, 16);
if (*endp != '\0') {
pr_err("Error: Can't set serial# to %s\n", ep->serial);
return;
}
snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
env_set("serial#", serial_string);
}
#endif
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
setup_board_eeprom_env();
setup_serial();
}
return 0;
}
void spl_board_init(void)
{
}

2
configs/dra7xx_evm_defconfig
View File

@ -54,7 +54,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set

1
configs/j7200_evm_r5_defconfig
View File

@ -91,6 +91,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y

2
configs/j721e_evm_a72_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y

1
configs/j721e_evm_r5_defconfig
View File

@ -88,6 +88,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y

1
configs/j721e_hs_evm_r5_defconfig
View File

@ -82,6 +82,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y

207
configs/j721s2_evm_a72_defconfig Normal file
View File

@ -0,0 +1,207 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721S2=y
CONFIG_TARGET_J721S2_A72_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0x6A0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_THERMAL=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_CLK_CCF=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HS512T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_QSPI_PHY=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
CONFIG_OF_LIBFDT_OVERLAY=y

172
configs/j721s2_evm_r5_defconfig Normal file
View File

@ -0,0 +1,172 @@
CONFIG_PANIC_HANG=y
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SOC_K3_J721S2=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J721S2_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_THERMAL=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
# CONFIG_CLK_TI_SCI is not set
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HS512T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
# CONFIG_TI_SCI_POWER_DOMAIN is not set
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_QSPI_PHY=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_TI_POWER_DOMAIN=y
CONFIG_SPL_CLK_CCF=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_K3_DM_FW=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_DM_GPIO=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y

2
configs/nokia_rx51_defconfig
View File

@ -66,6 +66,7 @@ CONFIG_DM=y
# CONFIG_DM_SEQ_ALIAS is not set
# CONFIG_BLOCK_CACHE is not set
CONFIG_DM_I2C=y
CONFIG_DM_KEYBOARD=y
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_OMAP_HS=y
@ -78,7 +79,6 @@ CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_CFB_CONSOLE=y
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
CONFIG_SPLASH_SCREEN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=31000
CONFIG_WDT=y

1
configs/socfpga_arria10_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y

3
doc/device-tree-bindings/remoteproc/k3-system-controller.txt
View File

@ -13,6 +13,9 @@ Required properties:
"rx" for Receive channel
- mboxes: Corresponding phandles to mailbox channels.
Optional properties:
--------------------
- mbox-names: "boot_notify" for Optional alternate boot notification channel.
Example:
--------

5
drivers/clk/ti/clk-k3.c
View File

@ -68,6 +68,11 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = &j7200_clk_platdata,
},
#elif CONFIG_SOC_K3_J721S2
{
.family = "J721S2",
.data = &j721s2_clk_platdata,
},
#endif
{ /* sentinel */ }
};

1
drivers/dma/ti/Makefile
View File

@ -5,4 +5,5 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o

167
drivers/dma/ti/k3-psil-j721s2.c Normal file
View File

@ -0,0 +1,167 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
*/
#include <linux/kernel.h>
#include "k3-psil-priv.h"
#define PSIL_PDMA_XY_TR(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_PDMA_XY, \
}, \
}
#define PSIL_PDMA_XY_PKT(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_PDMA_XY, \
.pkt_mode = 1, \
}, \
}
#define PSIL_PDMA_MCASP(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_PDMA_XY, \
.pdma_acc32 = 1, \
.pdma_burst = 1, \
}, \
}
#define PSIL_ETHERNET(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_NATIVE, \
.pkt_mode = 1, \
.needs_epib = 1, \
.psd_size = 16, \
}, \
}
#define PSIL_SA2UL(x, tx) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_NATIVE, \
.pkt_mode = 1, \
.needs_epib = 1, \
.psd_size = 64, \
.notdpkt = tx, \
}, \
}
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
static struct psil_ep j721s2_src_ep_map[] = {
/* PDMA_MCASP - McASP0-4 */
PSIL_PDMA_MCASP(0x4400),
PSIL_PDMA_MCASP(0x4401),
PSIL_PDMA_MCASP(0x4402),
PSIL_PDMA_MCASP(0x4403),
PSIL_PDMA_MCASP(0x4404),
/* PDMA_SPI_G0 - SPI0-3 */
PSIL_PDMA_XY_PKT(0x4600),
PSIL_PDMA_XY_PKT(0x4601),
PSIL_PDMA_XY_PKT(0x4602),
PSIL_PDMA_XY_PKT(0x4603),
PSIL_PDMA_XY_PKT(0x4604),
PSIL_PDMA_XY_PKT(0x4605),
PSIL_PDMA_XY_PKT(0x4606),
PSIL_PDMA_XY_PKT(0x4607),
PSIL_PDMA_XY_PKT(0x4608),
PSIL_PDMA_XY_PKT(0x4609),
PSIL_PDMA_XY_PKT(0x460a),
PSIL_PDMA_XY_PKT(0x460b),
PSIL_PDMA_XY_PKT(0x460c),
PSIL_PDMA_XY_PKT(0x460d),
PSIL_PDMA_XY_PKT(0x460e),
PSIL_PDMA_XY_PKT(0x460f),
/* PDMA_SPI_G1 - SPI4-7 */
PSIL_PDMA_XY_PKT(0x4610),
PSIL_PDMA_XY_PKT(0x4611),
PSIL_PDMA_XY_PKT(0x4612),
PSIL_PDMA_XY_PKT(0x4613),
PSIL_PDMA_XY_PKT(0x4614),
PSIL_PDMA_XY_PKT(0x4615),
PSIL_PDMA_XY_PKT(0x4616),
PSIL_PDMA_XY_PKT(0x4617),
PSIL_PDMA_XY_PKT(0x4618),
PSIL_PDMA_XY_PKT(0x4619),
PSIL_PDMA_XY_PKT(0x461a),
PSIL_PDMA_XY_PKT(0x461b),
PSIL_PDMA_XY_PKT(0x461c),
PSIL_PDMA_XY_PKT(0x461d),
PSIL_PDMA_XY_PKT(0x461e),
PSIL_PDMA_XY_PKT(0x461f),
/* PDMA_USART_G0 - UART0-1 */
PSIL_PDMA_XY_PKT(0x4700),
PSIL_PDMA_XY_PKT(0x4701),
/* PDMA_USART_G1 - UART2-3 */
PSIL_PDMA_XY_PKT(0x4702),
PSIL_PDMA_XY_PKT(0x4703),
/* PDMA_USART_G2 - UART4-9 */
PSIL_PDMA_XY_PKT(0x4704),
PSIL_PDMA_XY_PKT(0x4705),
PSIL_PDMA_XY_PKT(0x4706),
PSIL_PDMA_XY_PKT(0x4707),
PSIL_PDMA_XY_PKT(0x4708),
PSIL_PDMA_XY_PKT(0x4709),
/* CPSW0 */
PSIL_ETHERNET(0x7000),
/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
PSIL_PDMA_XY_PKT(0x7100),
PSIL_PDMA_XY_PKT(0x7101),
PSIL_PDMA_XY_PKT(0x7102),
PSIL_PDMA_XY_PKT(0x7103),
/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
PSIL_PDMA_XY_PKT(0x7200),
PSIL_PDMA_XY_PKT(0x7201),
PSIL_PDMA_XY_PKT(0x7202),
PSIL_PDMA_XY_PKT(0x7203),
PSIL_PDMA_XY_PKT(0x7204),
PSIL_PDMA_XY_PKT(0x7205),
PSIL_PDMA_XY_PKT(0x7206),
PSIL_PDMA_XY_PKT(0x7207),
/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
PSIL_PDMA_XY_PKT(0x7300),
/* MCU_PDMA_ADC - ADC0-1 */
PSIL_PDMA_XY_TR(0x7400),
PSIL_PDMA_XY_TR(0x7401),
PSIL_PDMA_XY_TR(0x7402),
PSIL_PDMA_XY_TR(0x7403),
/* SA2UL */
PSIL_SA2UL(0x7500, 0),
PSIL_SA2UL(0x7501, 0),
PSIL_SA2UL(0x7502, 0),
PSIL_SA2UL(0x7503, 0),
};
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
static struct psil_ep j721s2_dst_ep_map[] = {
/* CPSW0 */
PSIL_ETHERNET(0xf000),
PSIL_ETHERNET(0xf001),
PSIL_ETHERNET(0xf002),
PSIL_ETHERNET(0xf003),
PSIL_ETHERNET(0xf004),
PSIL_ETHERNET(0xf005),
PSIL_ETHERNET(0xf006),
PSIL_ETHERNET(0xf007),
/* SA2UL */
PSIL_SA2UL(0xf500, 1),
PSIL_SA2UL(0xf501, 1),
};
struct psil_ep_map j721s2_ep_map = {
.name = "j721s2",
.src = j721s2_src_ep_map,
.src_count = ARRAY_SIZE(j721s2_src_ep_map),
.dst = j721s2_dst_ep_map,
.dst_count = ARRAY_SIZE(j721s2_dst_ep_map),
};

1
drivers/dma/ti/k3-psil-priv.h
View File

@ -39,6 +39,7 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
/* SoC PSI-L endpoint maps */
extern struct psil_ep_map am654_ep_map;
extern struct psil_ep_map j721e_ep_map;
extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am64_ep_map;
#endif /* K3_PSIL_PRIV_H_ */

2
drivers/dma/ti/k3-psil.c
View File

@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721S2))
soc_ep_map = &j721s2_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
soc_ep_map = &am64_ep_map;
}

40
drivers/firmware/ti_sci_static_data.h
View File

@ -56,21 +56,21 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
{
.dev_id = 235,
.subtype = 1,
.range_start = 144,
.range_start = 124,
.range_num = 32,
},
/* TX channels */
{
.dev_id = 236,
.subtype = 13,
.range_start = 7,
.range_start = 6,
.range_num = 2,
},
/* RX channels */
{
.dev_id = 236,
.subtype = 10,
.range_start = 7,
.range_start = 6,
.range_num = 2,
},
/* RX Free flows */
@ -84,6 +84,40 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
};
#endif /* CONFIG_TARGET_J7200_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* Free rings */
{
.dev_id = 272,
.subtype = 1,
.range_start = 180,
.range_num = 32,
},
/* TX channels */
{
.dev_id = 273,
.subtype = 13,
.range_start = 12,
.range_num = 2,
},
/* RX channels */
{
.dev_id = 273,
.subtype = 10,
.range_start = 12,
.range_num = 2,
},
/* RX Free flows */
{
.dev_id = 273,
.subtype = 0,
.range_start = 80,
.range_num = 8,
},
{ },
};
#endif /* CONFIG_TARGET_J721S2_R5_EVM */
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
{ },

9
drivers/misc/Kconfig
View File

@ -453,6 +453,15 @@ config FS_LOADER
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
config SPL_FS_LOADER
bool "Enable loader driver for file system"
help
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
config GDSYS_SOC
bool "Enable gdsys SOC driver"
depends on MISC

2
drivers/misc/Makefile
View File

@ -37,7 +37,7 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_FS_LOADER) += fs_loader.o
obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o

1539
drivers/phy/cadence/phy-cadence-sierra.c
View File

File diff suppressed because it is too large Load Diff

2
drivers/phy/ti/phy-j721e-wiz.c
View File

@ -523,7 +523,7 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
return ret;
}
if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE)
if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);

5
drivers/power/domain/ti-power-domain.c
View File

@ -79,6 +79,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "J7200",
.data = &j7200_pd_platdata,
},
#elif CONFIG_SOC_K3_J721S2
{
.family = "J721S2",
.data = &j721s2_pd_platdata,
},
#endif
{ /* sentinel */ }
};

2
drivers/ram/Kconfig
View File

@ -62,7 +62,7 @@ choice
depends on K3_DDRSS
prompt "K3 DDRSS Arch Support"
default K3_J721E_DDRSS if SOC_K3_J721E
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
default K3_AM64_DDRSS if SOC_K3_AM642
config K3_J721E_DDRSS

296
drivers/ram/k3-ddrss/k3-ddrss.c
View File

@ -30,6 +30,78 @@
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM 0x2
#define MULTI_DDR_CFG0 0x00114100
#define MULTI_DDR_CFG1 0x00114104
#define DDR_CFG_LOAD 0x00114110
enum intrlv_gran {
GRAN_128B,
GRAN_512B,
GRAN_2KB,
GRAN_4KB,
GRAN_16KB,
GRAN_32KB,
GRAN_512KB,
GRAN_1GB,
GRAN_1_5GB,
GRAN_2GB,
GRAN_3GB,
GRAN_4GB,
GRAN_6GB,
GRAN_8GB,
GRAN_16GB
};
enum intrlv_size {
SIZE_0,
SIZE_128MB,
SIZE_256MB,
SIZE_512MB,
SIZE_1GB,
SIZE_2GB,
SIZE_3GB,
SIZE_4GB,
SIZE_6GB,
SIZE_8GB,
SIZE_12GB,
SIZE_16GB,
SIZE_32GB
};
struct k3_ddrss_data {
u32 flags;
};
enum ecc_enable {
DISABLE_ALL = 0,
ENABLE_0,
ENABLE_1,
ENABLE_ALL
};
enum emif_config {
INTERLEAVE_ALL = 0,
SEPR0,
SEPR1
};
enum emif_active {
EMIF_0 = 1,
EMIF_1,
EMIF_ALL
};
struct k3_msmc {
enum intrlv_gran gran;
enum intrlv_size size;
enum ecc_enable enable;
enum emif_config config;
enum emif_active active;
};
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@ -42,14 +114,12 @@ struct k3_ddrss_desc {
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
u32 instance;
lpddr4_obj *driverdt;
lpddr4_config config;
lpddr4_privatedata pd;
};
static lpddr4_obj *driverdt;
static lpddr4_config config;
static lpddr4_privatedata pd;
static struct k3_ddrss_desc *ddrss;
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
@ -83,15 +153,16 @@ struct reginitdata {
offset = offset * 10 + (*i - '0'); } \
} while (0)
static u32 k3_lpddr4_read_ddr_type(void)
static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
@ -102,23 +173,23 @@ static u32 k3_lpddr4_read_ddr_type(void)
return dram_class;
}
static void k3_lpddr4_freq_update(void)
static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
true, 10000, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
debug("%s: received freq change req: req type = %d, req no. = %d\n",
__func__, req_type, counter);
debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
__func__, req_type, counter, ddrss->instance);
if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
@ -132,31 +203,32 @@ static void k3_lpddr4_freq_update(void)
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
}
}
static void k3_lpddr4_ack_freq_upd_req(void)
static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
dram_class = k3_lpddr4_read_ddr_type();
dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
k3_lpddr4_freq_update();
k3_lpddr4_freq_update(ddrss);
break;
default:
printf("Unrecognized dram_class cannot update frequency!\n");
@ -167,8 +239,9 @@ static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{
u32 dram_class;
int ret;
lpddr4_privatedata *pd = &ddrss->pd;
dram_class = k3_lpddr4_read_ddr_type();
dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
@ -196,7 +269,7 @@ static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
lpddr4_infotype infotype)
{
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
k3_lpddr4_ack_freq_upd_req();
k3_lpddr4_ack_freq_upd_req(pd);
}
static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
@ -235,6 +308,7 @@ static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
{
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
phys_addr_t reg;
int ret;
@ -274,6 +348,17 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
if (ret)
dev_err(dev, "clk get failed for osc clk %d\n", ret);
/* Reading instance number for multi ddr subystems */
if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
ret = dev_read_u32(dev, "instance", &ddrss->instance);
if (ret) {
dev_err(dev, "missing instance property");
return -EINVAL;
}
} else {
ddrss->instance = 0;
}
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
if (ret)
dev_err(dev, "ddr freq1 not populated %d\n", ret);
@ -289,12 +374,13 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
return ret;
}
void k3_lpddr4_probe(void)
void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
u16 configsize = 0U;
lpddr4_config *config = &ddrss->config;
status = driverdt->probe(&config, &configsize);
status = ddrss->driverdt->probe(config, &configsize);
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|| (configsize > SRAM_MAX)) {
@ -305,25 +391,30 @@ void k3_lpddr4_probe(void)
}
}
void k3_lpddr4_init(void)
void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
lpddr4_config *config = &ddrss->config;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
if ((sizeof(pd) != sizeof(lpddr4_privatedata))
|| (sizeof(pd) > SRAM_MAX)) {
if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
printf("%s: FAIL\n", __func__);
hang();
}
config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
status = driverdt->init(&pd, &config);
status = driverdt->init(pd, config);
/* linking ddr instance to lpddr4 */
pd->ddr_instance = (void *)ddrss;
if ((status > 0U) ||
(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
(pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
(pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
(pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
(pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
printf("%s: FAIL\n", __func__);
hang();
} else {
@ -331,7 +422,8 @@ void k3_lpddr4_init(void)
}
}
void populate_data_array_from_dt(struct reginitdata *reginit_data)
void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
struct reginitdata *reginit_data)
{
int ret, i;
@ -363,22 +455,24 @@ void populate_data_array_from_dt(struct reginitdata *reginit_data)
reginit_data->phy_regs_offs[i] = i;
}
void k3_lpddr4_hardware_reg_init(void)
void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
struct reginitdata reginitdata;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
populate_data_array_from_dt(&reginitdata);
populate_data_array_from_dt(ddrss, &reginitdata);
status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
reginitdata.ctl_regs_offs,
LPDDR4_INTR_CTL_REG_COUNT);
if (!status)
status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
reginitdata.pi_regs_offs,
LPDDR4_INTR_PHY_INDEP_REG_COUNT);
if (!status)
status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
reginitdata.phy_regs_offs,
LPDDR4_INTR_PHY_REG_COUNT);
if (status) {
@ -387,27 +481,29 @@ void k3_lpddr4_hardware_reg_init(void)
}
}
void k3_lpddr4_start(void)
void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
{
u32 status = 0U;
u32 regval = 0U;
u32 offset = 0U;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
printf("%s: Pre start FAIL\n", __func__);
hang();
}
status = driverdt->start(&pd);
status = driverdt->start(pd);
if (status > 0U) {
printf("%s: FAIL\n", __func__);
hang();
}
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
printf("%s: Post start FAIL\n", __func__);
hang();
@ -419,8 +515,7 @@ void k3_lpddr4_start(void)
static int k3_ddrss_probe(struct udevice *dev)
{
int ret;
ddrss = dev_get_priv(dev);
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
debug("%s(dev=%p)\n", __func__, dev);
@ -439,16 +534,17 @@ static int k3_ddrss_probe(struct udevice *dev)
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
#endif
driverdt = lpddr4_getinstance();
k3_lpddr4_probe();
k3_lpddr4_init();
k3_lpddr4_hardware_reg_init();
ddrss->driverdt = lpddr4_getinstance();
k3_lpddr4_probe(ddrss);
k3_lpddr4_init(ddrss);
k3_lpddr4_hardware_reg_init(ddrss);
ret = k3_ddrss_init_freq(ddrss);
if (ret)
return ret;
k3_lpddr4_start();
k3_lpddr4_start(ddrss);
return ret;
}
@ -462,9 +558,18 @@ static struct ram_ops k3_ddrss_ops = {
.get_info = k3_ddrss_get_info,
};
static const struct k3_ddrss_data k3_data = {
.flags = SINGLE_DDR_SUBSYSTEM,
};
static const struct k3_ddrss_data j721s2_data = {
.flags = MULTI_DDR_SUBSYSTEM,
};
static const struct udevice_id k3_ddrss_ids[] = {
{.compatible = "ti,am64-ddrss"},
{.compatible = "ti,j721e-ddrss"},
{.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
{}
};
@ -476,3 +581,92 @@ U_BOOT_DRIVER(k3_ddrss) = {
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};
static int k3_msmc_set_config(struct k3_msmc *msmc)
{
u32 ddr_cfg0 = 0;
u32 ddr_cfg1 = 0;
ddr_cfg0 |= msmc->gran << 24;
ddr_cfg0 |= msmc->size << 16;
/* heartbeat_per, bit[4:0] setting to 3 is advisable */
ddr_cfg0 |= 3;
/* Program MULTI_DDR_CFG0 */
writel(ddr_cfg0, MULTI_DDR_CFG0);
ddr_cfg1 |= msmc->enable << 16;
ddr_cfg1 |= msmc->config << 8;
ddr_cfg1 |= msmc->active;
/* Program MULTI_DDR_CFG1 */
writel(ddr_cfg1, MULTI_DDR_CFG1);
/* Program DDR_CFG_LOAD */
writel(0x60000000, DDR_CFG_LOAD);
return 0;
}
static int k3_msmc_probe(struct udevice *dev)
{
struct k3_msmc *msmc = dev_get_priv(dev);
int ret = 0;
/* Read the granular size from DT */
ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
if (ret) {
dev_err(dev, "missing intrlv-gran property");
return -EINVAL;
}
/* Read the interleave region from DT */
ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
if (ret) {
dev_err(dev, "missing intrlv-size property");
return -EINVAL;
}
/* Read ECC enable config */
ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
if (ret) {
dev_err(dev, "missing ecc-enable property");
return -EINVAL;
}
/* Read EMIF configuration */
ret = dev_read_u32(dev, "emif-config", &msmc->config);
if (ret) {
dev_err(dev, "missing emif-config property");
return -EINVAL;
}
/* Read EMIF active */
ret = dev_read_u32(dev, "emif-active", &msmc->active);
if (ret) {
dev_err(dev, "missing emif-active property");
return -EINVAL;
}
ret = k3_msmc_set_config(msmc);
if (ret) {
dev_err(dev, "error setting msmc config");
return -EINVAL;
}
return 0;
}
static const struct udevice_id k3_msmc_ids[] = {
{ .compatible = "ti,j721s2-msmc"},
{}
};
U_BOOT_DRIVER(k3_msmc) = {
.name = "k3_msmc",
.of_match = k3_msmc_ids,
.id = UCLASS_MISC,
.probe = k3_msmc_probe,
.priv_auto = sizeof(struct k3_msmc),
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};

1
drivers/ram/k3-ddrss/lpddr4_structs_if.h
View File

@ -24,6 +24,7 @@ struct lpddr4_privatedata_s {
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
void *ddr_instance;
};
struct lpddr4_debuginfo_s {

10
drivers/remoteproc/Kconfig
View File

@ -92,4 +92,14 @@ config REMOTEPROC_TI_PRU
help
Say 'y' here to add support for TI' K3 remoteproc driver.
config REMOTEPROC_TI_IPU
bool "Support for TI's K3 based IPU remoteproc driver"
select REMOTEPROC
depends on DM
depends on SPL_DRIVERS_MISC
depends on SPL_FS_LOADER
depends on OF_CONTROL
help
Say 'y' here to add support for TI' K3 remoteproc driver.
endmenu

1
drivers/remoteproc/Makefile
View File

@ -15,3 +15,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_IPU) += ipu_rproc.o

759
drivers/remoteproc/ipu_rproc.c Normal file
View File

@ -0,0 +1,759 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IPU remoteproc driver for various SoCs
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Angela Stegmaier <angelabaker@ti.com>
* Venkateswara Rao Mandela <venkat.mandela@ti.com>
* Keerthy <j-keerthy@ti.com>
*/
#include <common.h>
#include <hang.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <elf.h>
#include <env.h>
#include <dm/of_access.h>
#include <fs_loader.h>
#include <remoteproc.h>
#include <errno.h>
#include <clk.h>
#include <reset.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <misc.h>
#include <power-domain.h>
#include <timer.h>
#include <fs.h>
#include <spl.h>
#include <timer.h>
#include <reset.h>
#include <linux/bitmap.h>
#define IPU1_LOAD_ADDR (0xa17ff000)
#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
enum ipu_num {
IPU1 = 0,
IPU2,
RPROC_END_ENUMS,
};
#define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
#define PAGE_SHIFT 12
#define PAGESIZE_1M 0x0
#define PAGESIZE_64K 0x1
#define PAGESIZE_4K 0x2
#define PAGESIZE_16M 0x3
#define LE 0
#define BE 1
#define ELEMSIZE_8 0x0
#define ELEMSIZE_16 0x1
#define ELEMSIZE_32 0x2
#define MIXED_TLB 0x0
#define MIXED_CPU 0x1
#define PGT_SMALLPAGE_SIZE 0x00001000
#define PGT_LARGEPAGE_SIZE 0x00010000
#define PGT_SECTION_SIZE 0x00100000
#define PGT_SUPERSECTION_SIZE 0x01000000
#define PGT_L1_DESC_PAGE 0x00001
#define PGT_L1_DESC_SECTION 0x00002
#define PGT_L1_DESC_SUPERSECTION 0x40002
#define PGT_L1_DESC_PAGE_MASK 0xfffffC00
#define PGT_L1_DESC_SECTION_MASK 0xfff00000
#define PGT_L1_DESC_SUPERSECTION_MASK 0xff000000
#define PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT 12
#define PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT 16
#define PGT_L1_DESC_SECTION_INDEX_SHIFT 20
#define PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT 24
#define PGT_L2_DESC_SMALLPAGE 0x02
#define PGT_L2_DESC_LARGEPAGE 0x01
#define PGT_L2_DESC_SMALLPAGE_MASK 0xfffff000
#define PGT_L2_DESC_LARGEPAGE_MASK 0xffff0000
/*
* The memory for the page tables (256 KB per IPU) is placed just before
* the carveout memories for the remote processors. 16 KB of memory is
* needed for the L1 page table (4096 entries * 4 bytes per 1 MB section).
* Any smaller page (64 KB or 4 KB) entries are supported through L2 page
* tables (1 KB per table). The remaining 240 KB can provide support for
* 240 L2 page tables. Any remoteproc firmware image requiring more than
* 240 L2 page table entries would need more memory to be reserved.
*/
#define PAGE_TABLE_SIZE_L1 (0x00004000)
#define PAGE_TABLE_SIZE_L2 (0x400)
#define MAX_NUM_L2_PAGE_TABLES (240)
#define PAGE_TABLE_SIZE_L2_TOTAL (MAX_NUM_L2_PAGE_TABLES * PAGE_TABLE_SIZE_L2)
#define PAGE_TABLE_SIZE (PAGE_TABLE_SIZE_L1 + (PAGE_TABLE_SIZE_L2_TOTAL))
/**
* struct omap_rproc_mem - internal memory structure
* @cpu_addr: MPU virtual address of the memory region
* @bus_addr: bus address used to access the memory region
* @dev_addr: device address of the memory region from DSP view
* @size: size of the memory region
*/
struct omap_rproc_mem {
void __iomem *cpu_addr;
phys_addr_t bus_addr;
u32 dev_addr;
size_t size;
};
struct ipu_privdata {
struct omap_rproc_mem mem;
struct list_head mappings;
const char *fw_name;
u32 bootaddr;
int id;
struct udevice *rdev;
};
typedef int (*handle_resource_t) (void *, int offset, int avail);
unsigned int *page_table_l1 = (unsigned int *)0x0;
unsigned int *page_table_l2 = (unsigned int *)0x0;
/*
* Set maximum carveout size to 96 MB
*/
#define DRA7_RPROC_MAX_CO_SIZE (96 * 0x100000)
/*
* These global variables are used for deriving the MMU page tables. They
* are initialized for each core with the appropriate values. The length
* of the array mem_bitmap is set as per a 96 MB carveout which the
* maximum set aside in the current memory map.
*/
unsigned long mem_base;
unsigned long mem_size;
unsigned long
mem_bitmap[BITS_TO_LONGS(DRA7_RPROC_MAX_CO_SIZE >> PAGE_SHIFT)];
unsigned long mem_count;
unsigned int pgtable_l2_map[MAX_NUM_L2_PAGE_TABLES];
unsigned int pgtable_l2_cnt;
void *ipu_alloc_mem(struct udevice *dev, unsigned long len, unsigned long align)
{
unsigned long mask;
unsigned long pageno;
int count;
count = ((len + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1)) >> PAGE_SHIFT;
mask = (1 << align) - 1;
pageno =
bitmap_find_next_zero_area(mem_bitmap, mem_count, 0, count, mask);
debug("%s: count %d mask %#lx pageno %#lx\n", __func__, count, mask,
pageno);
if (pageno >= mem_count) {
debug("%s: %s Error allocating memory; "
"Please check carveout size\n", __FILE__, __func__);
return NULL;
}
bitmap_set(mem_bitmap, pageno, count);
return (void *)(mem_base + (pageno << PAGE_SHIFT));
}
int find_pagesz(unsigned int virt, unsigned int phys, unsigned int len)
{
int pg_sz_ind = -1;
unsigned int min_align = __ffs(virt);
if (min_align > __ffs(phys))
min_align = __ffs(phys);
if (min_align >= PGT_L1_DESC_SUPERSECTION_INDEX_SHIFT &&
len >= 0x1000000) {
pg_sz_ind = PAGESIZE_16M;
goto ret_block;
}
if (min_align >= PGT_L1_DESC_SECTION_INDEX_SHIFT &&
len >= 0x100000) {
pg_sz_ind = PAGESIZE_1M;
goto ret_block;
}
if (min_align >= PGT_L1_DESC_LARGEPAGE_INDEX_SHIFT &&
len >= 0x10000) {
pg_sz_ind = PAGESIZE_64K;
goto ret_block;
}
if (min_align >= PGT_L1_DESC_SMALLPAGE_INDEX_SHIFT &&
len >= 0x1000) {
pg_sz_ind = PAGESIZE_4K;
goto ret_block;
}
ret_block:
return pg_sz_ind;
}
int get_l2_pg_tbl_addr(unsigned int virt, unsigned int *pg_tbl_addr)
{
int ret = -1;
int i = 0;
int match_found = 0;
unsigned int tag = (virt & PGT_L1_DESC_SECTION_MASK);
*pg_tbl_addr = 0;
for (i = 0; (i < pgtable_l2_cnt) && (match_found == 0); i++) {
if (tag == pgtable_l2_map[i]) {
*pg_tbl_addr =
((unsigned int)page_table_l2) +
(i * PAGE_TABLE_SIZE_L2);
match_found = 1;
ret = 0;
}
}
if (match_found == 0 && i < MAX_NUM_L2_PAGE_TABLES) {
pgtable_l2_map[i] = tag;
pgtable_l2_cnt++;
*pg_tbl_addr =
((unsigned int)page_table_l2) + (i * PAGE_TABLE_SIZE_L2);
ret = 0;
}
return ret;
}
int
config_l2_pagetable(unsigned int virt, unsigned int phys,
unsigned int pg_sz, unsigned int pg_tbl_addr)
{
int ret = -1;
unsigned int desc = 0;
int i = 0;
unsigned int *pg_tbl = (unsigned int *)pg_tbl_addr;
/*
* Pick bit 19:12 of the virtual address as index
*/
unsigned int index = (virt & (~PGT_L1_DESC_SECTION_MASK)) >> PAGE_SHIFT;
switch (pg_sz) {
case PAGESIZE_64K:
desc =
(phys & PGT_L2_DESC_LARGEPAGE_MASK) | PGT_L2_DESC_LARGEPAGE;
for (i = 0; i < 16; i++)
pg_tbl[index + i] = desc;
ret = 0;
break;
case PAGESIZE_4K:
desc =
(phys & PGT_L2_DESC_SMALLPAGE_MASK) | PGT_L2_DESC_SMALLPAGE;
pg_tbl[index] = desc;
ret = 0;
break;
default:
break;
}
return ret;
}
unsigned int
ipu_config_pagetable(struct udevice *dev, unsigned int virt, unsigned int phys,
unsigned int len)
{
unsigned int index;
unsigned int l = len;
unsigned int desc;
int pg_sz = 0;
int i = 0, err = 0;
unsigned int pg_tbl_l2_addr = 0;
unsigned int tmp_pgsz;
if ((len & 0x0FFF) != 0)
return 0;
while (l > 0) {
pg_sz = find_pagesz(virt, phys, l);
index = virt >> PGT_L1_DESC_SECTION_INDEX_SHIFT;
switch (pg_sz) {
/*
* 16 MB super section
*/
case PAGESIZE_16M:
/*
* Program the next 16 descriptors
*/
desc =
(phys & PGT_L1_DESC_SUPERSECTION_MASK) |
PGT_L1_DESC_SUPERSECTION;
for (i = 0; i < 16; i++)
page_table_l1[index + i] = desc;
l -= PGT_SUPERSECTION_SIZE;
phys += PGT_SUPERSECTION_SIZE;
virt += PGT_SUPERSECTION_SIZE;
break;
/*
* 1 MB section
*/
case PAGESIZE_1M:
desc =
(phys & PGT_L1_DESC_SECTION_MASK) |
PGT_L1_DESC_SECTION;
page_table_l1[index] = desc;
l -= PGT_SECTION_SIZE;
phys += PGT_SECTION_SIZE;
virt += PGT_SECTION_SIZE;
break;
/*
* 64 KB large page
*/
case PAGESIZE_64K:
case PAGESIZE_4K:
if (pg_sz == PAGESIZE_64K)
tmp_pgsz = 0x10000;
else
tmp_pgsz = 0x1000;
err = get_l2_pg_tbl_addr(virt, &pg_tbl_l2_addr);
if (err != 0) {
debug
("Unable to get level 2 PT address\n");
hang();
}
err =
config_l2_pagetable(virt, phys, pg_sz,
pg_tbl_l2_addr);
desc =
(pg_tbl_l2_addr & PGT_L1_DESC_PAGE_MASK) |
PGT_L1_DESC_PAGE;
page_table_l1[index] = desc;
l -= tmp_pgsz;
phys += tmp_pgsz;
virt += tmp_pgsz;
break;
case -1:
default:
return 0;
}
}
return len;
}
int da_to_pa(struct udevice *dev, int da)
{
struct rproc_mem_entry *maps = NULL;
struct ipu_privdata *priv = dev_get_priv(dev);
list_for_each_entry(maps, &priv->mappings, node) {
if (da >= maps->da && da < (maps->da + maps->len))
return maps->dma + (da - maps->da);
}
return 0;
}
u32 ipu_config_mmu(u32 core_id, struct rproc *cfg)
{
u32 i = 0;
u32 reg = 0;
/*
* Clear the entire pagetable location before programming the
* address into the MMU
*/
memset((void *)cfg->page_table_addr, 0x00, PAGE_TABLE_SIZE);
for (i = 0; i < cfg->num_iommus; i++) {
u32 mmu_base = cfg->mmu_base_addr[i];
__raw_writel((int)cfg->page_table_addr, mmu_base + 0x4c);
reg = __raw_readl(mmu_base + 0x88);
/*
* enable bus-error back
*/
__raw_writel(reg | 0x1, mmu_base + 0x88);
/*
* Enable the MMU IRQs during MMU programming for the
* late attachcase. This is to allow the MMU fault to be
* detected by the kernel.
*
* MULTIHITFAULT|EMMUMISS|TRANSLATIONFAULT|TABLEWALKFAULT
*/
__raw_writel(0x1E, mmu_base + 0x1c);
/*
* emutlbupdate|TWLENABLE|MMUENABLE
*/
__raw_writel(0x6, mmu_base + 0x44);
}
return 0;
}
/**
* enum ipu_mem - PRU core memory range identifiers
*/
enum ipu_mem {
PRU_MEM_IRAM = 0,
PRU_MEM_CTRL,
PRU_MEM_DEBUG,
PRU_MEM_MAX,
};
static int ipu_start(struct udevice *dev)
{
struct ipu_privdata *priv;
struct reset_ctl reset;
struct rproc *cfg = NULL;
int ret;
priv = dev_get_priv(dev);
cfg = rproc_cfg_arr[priv->id];
if (cfg->config_peripherals)
cfg->config_peripherals(priv->id, cfg);
/*
* Start running the remote core
*/
ret = reset_get_by_index(dev, 0, &reset);
if (ret < 0) {
dev_err(dev, "%s: error getting reset index %d\n", __func__, 0);
return ret;
}
ret = reset_deassert(&reset);
if (ret < 0) {
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 0);
return ret;
}
ret = reset_get_by_index(dev, 1, &reset);
if (ret < 0) {
dev_err(dev, "%s: error getting reset index %d\n", __func__, 1);
return ret;
}
ret = reset_deassert(&reset);
if (ret < 0) {
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 1);
return ret;
}
return 0;
}
static int ipu_stop(struct udevice *dev)
{
return 0;
}
/**
* ipu_init() - Initialize the remote processor
* @dev: rproc device pointer
*
* Return: 0 if all went ok, else return appropriate error
*/
static int ipu_init(struct udevice *dev)
{
return 0;
}
static int ipu_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
{
struct ipu_privdata *priv = dev_get_priv(dev);
list_add_tail(&mapping->node, &priv->mappings);
return 0;
}
static int ipu_load(struct udevice *dev, ulong addr, ulong size)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
Elf32_Phdr proghdr;
int va;
int pa;
int i;
ehdr = (Elf32_Ehdr *)addr;
phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
/*
* Load each program header
*/
for (i = 0; i < ehdr->e_phnum; ++i) {
memcpy(&proghdr, phdr, sizeof(Elf32_Phdr));
if (proghdr.p_type != PT_LOAD) {
++phdr;
continue;
}
va = proghdr.p_paddr;
pa = da_to_pa(dev, va);
if (pa)
proghdr.p_paddr = pa;
void *dst = (void *)(uintptr_t)proghdr.p_paddr;
void *src = (void *)addr + proghdr.p_offset;
debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst,
proghdr.p_filesz);
if (proghdr.p_filesz)
memcpy(dst, src, proghdr.p_filesz);
flush_cache((unsigned long)dst, proghdr.p_memsz);
++phdr;
}
return 0;
}
static const struct dm_rproc_ops ipu_ops = {
.init = ipu_init,
.start = ipu_start,
.stop = ipu_stop,
.load = ipu_load,
.add_res = ipu_add_res,
.config_pagetable = ipu_config_pagetable,
.alloc_mem = ipu_alloc_mem,
};
/*
* If the remotecore binary expects any peripherals to be setup before it has
* booted, configure them here.
*
* These functions are left empty by default as their operation is usecase
* specific.
*/
u32 ipu1_config_peripherals(u32 core_id, struct rproc *cfg)
{
return 0;
}
u32 ipu2_config_peripherals(u32 core_id, struct rproc *cfg)
{
return 0;
}
struct rproc_intmem_to_l3_mapping ipu1_intmem_to_l3_mapping = {
.num_entries = 1,
.mappings = {
/*
* L2 SRAM
*/
{
.priv_addr = 0x55020000,
.l3_addr = 0x58820000,
.len = (64 * 1024)},
}
};
struct rproc_intmem_to_l3_mapping ipu2_intmem_to_l3_mapping = {
.num_entries = 1,
.mappings = {
/*
* L2 SRAM
*/
{
.priv_addr = 0x55020000,
.l3_addr = 0x55020000,
.len = (64 * 1024)},
}
};
struct rproc ipu1_config = {
.num_iommus = 1,
.mmu_base_addr = {0x58882000, 0},
.load_addr = IPU1_LOAD_ADDR,
.core_name = "IPU1",
.firmware_name = "dra7-ipu1-fw.xem4",
.config_mmu = ipu_config_mmu,
.config_peripherals = ipu1_config_peripherals,
.intmem_to_l3_mapping = &ipu1_intmem_to_l3_mapping
};
struct rproc ipu2_config = {
.num_iommus = 1,
.mmu_base_addr = {0x55082000, 0},
.load_addr = IPU2_LOAD_ADDR,
.core_name = "IPU2",
.firmware_name = "dra7-ipu2-fw.xem4",
.config_mmu = ipu_config_mmu,
.config_peripherals = ipu2_config_peripherals,
.intmem_to_l3_mapping = &ipu2_intmem_to_l3_mapping
};
struct rproc *rproc_cfg_arr[2] = {
[IPU2] = &ipu2_config,
[IPU1] = &ipu1_config,
};
u32 spl_pre_boot_core(struct udevice *dev, u32 core_id)
{
struct rproc *cfg = NULL;
unsigned long load_elf_status = 0;
int tablesz;
cfg = rproc_cfg_arr[core_id];
/*
* Check for valid elf image
*/
if (!valid_elf_image(cfg->load_addr))
return 1;
if (rproc_find_resource_table(dev, cfg->load_addr, &tablesz))
cfg->has_rsc_table = 1;
else
cfg->has_rsc_table = 0;
/*
* Configure the MMU
*/
if (cfg->config_mmu && cfg->has_rsc_table)
cfg->config_mmu(core_id, cfg);
/*
* Load the remote core. Fill the page table of the first(possibly
* only) IOMMU during ELF loading. Copy the page table to the second
* IOMMU before running the remote core.
*/
page_table_l1 = (unsigned int *)cfg->page_table_addr;
page_table_l2 =
(unsigned int *)(cfg->page_table_addr + PAGE_TABLE_SIZE_L1);
mem_base = cfg->cma_base;
mem_size = cfg->cma_size;
memset(mem_bitmap, 0x00, sizeof(mem_bitmap));
mem_count = (cfg->cma_size >> PAGE_SHIFT);
/*
* Clear variables used for level 2 page table allocation
*/
memset(pgtable_l2_map, 0x00, sizeof(pgtable_l2_map));
pgtable_l2_cnt = 0;
load_elf_status = rproc_parse_resource_table(dev, cfg);
if (load_elf_status == 0) {
debug("load_elf_image_phdr returned error for core %s\n",
cfg->core_name);
return 1;
}
flush_cache(cfg->page_table_addr, PAGE_TABLE_SIZE);
return 0;
}
static fdt_addr_t ipu_parse_mem_nodes(struct udevice *dev, char *name,
int privid, fdt_size_t *sizep)
{
int ret;
u32 sp;
ofnode mem_node;
ret = ofnode_read_u32(dev_ofnode(dev), name, &sp);
if (ret) {
dev_err(dev, "memory-region node fetch failed %d\n", ret);
return ret;
}
mem_node = ofnode_get_by_phandle(sp);
if (!ofnode_valid(mem_node))
return -EINVAL;
return ofnode_get_addr_size_index(mem_node, 0, sizep);
}
/**
* ipu_probe() - Basic probe
* @dev: corresponding k3 remote processor device
*
* Return: 0 if all goes good, else appropriate error message.
*/
static int ipu_probe(struct udevice *dev)
{
struct ipu_privdata *priv;
struct rproc *cfg = NULL;
struct reset_ctl reset;
static const char *const ipu_mem_names[] = { "l2ram" };
int ret;
fdt_size_t sizep;
priv = dev_get_priv(dev);
priv->mem.bus_addr =
devfdt_get_addr_size_name(dev,
ipu_mem_names[0],
(fdt_addr_t *)&priv->mem.size);
ret = reset_get_by_index(dev, 2, &reset);
if (ret < 0) {
dev_err(dev, "%s: error getting reset index %d\n", __func__, 2);
return ret;
}
ret = reset_deassert(&reset);
if (ret < 0) {
dev_err(dev, "%s: error deasserting reset %d\n", __func__, 2);
return ret;
}
if (priv->mem.bus_addr == FDT_ADDR_T_NONE) {
dev_err(dev, "%s bus address not found\n", ipu_mem_names[0]);
return -EINVAL;
}
priv->mem.cpu_addr = map_physmem(priv->mem.bus_addr,
priv->mem.size, MAP_NOCACHE);
if (devfdt_get_addr(dev) == 0x58820000)
priv->id = 0;
else
priv->id = 1;
cfg = rproc_cfg_arr[priv->id];
cfg->cma_base = ipu_parse_mem_nodes(dev, "memory-region", priv->id,
&sizep);
cfg->cma_size = sizep;
cfg->page_table_addr = ipu_parse_mem_nodes(dev, "pg-tbl", priv->id,
&sizep);
dev_info(dev,
"ID %d memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
priv->id, ipu_mem_names[0], &priv->mem.bus_addr,
priv->mem.size, priv->mem.cpu_addr, priv->mem.dev_addr);
INIT_LIST_HEAD(&priv->mappings);
if (spl_pre_boot_core(dev, priv->id))
return -EINVAL;
return 0;
}
static const struct udevice_id ipu_ids[] = {
{.compatible = "ti,dra7-ipu"},
{}
};
U_BOOT_DRIVER(ipu) = {
.name = "ipu",
.of_match = ipu_ids,
.id = UCLASS_REMOTEPROC,
.ops = &ipu_ops,
.probe = ipu_probe,
.priv_auto = sizeof(struct ipu_privdata),
};

20
drivers/remoteproc/k3_system_controller.c
View File

@ -77,14 +77,18 @@ struct k3_sysctrler_desc {
* struct k3_sysctrler_privdata - Structure representing System Controller data.
* @chan_tx: Transmit mailbox channel
* @chan_rx: Receive mailbox channel
* @chan_boot_notify: Boot notification channel
* @desc: SoC description for this instance
* @seq_nr: Counter for number of messages sent.
* @has_boot_notify: Has separate boot notification channel
*/
struct k3_sysctrler_privdata {
struct mbox_chan chan_tx;
struct mbox_chan chan_rx;
struct mbox_chan chan_boot_notify;
struct k3_sysctrler_desc *desc;
u32 seq_nr;
bool has_boot_notify;
};
static inline
@ -223,7 +227,8 @@ static int k3_sysctrler_start(struct udevice *dev)
debug("%s(dev=%p)\n", __func__, dev);
/* Receive the boot notification. Note that it is sent only once. */
ret = mbox_recv(&priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
ret = mbox_recv(priv->has_boot_notify ? &priv->chan_boot_notify :
&priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
if (ret) {
dev_err(dev, "%s: Boot Notification response failed. ret = %d\n",
__func__, ret);
@ -272,6 +277,19 @@ static int k3_of_to_priv(struct udevice *dev,
return ret;
}
/* Some SoCs may have a optional channel for boot notification. */
priv->has_boot_notify = 1;
ret = mbox_get_by_name(dev, "boot_notify", &priv->chan_boot_notify);
if (ret == -ENODATA) {
dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret = %d. Using Rx\n",
__func__, ret);
priv->has_boot_notify = 0;
} else if (ret) {
dev_err(dev, "%s: Acquiring boot_notify channel failed. ret = %d\n",
__func__, ret);
return ret;
}
return 0;
}

534
drivers/remoteproc/rproc-uclass.c
View File

@ -8,15 +8,31 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
#include <elf.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <virtio_ring.h>
#include <remoteproc.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <linux/compat.h>
DECLARE_GLOBAL_DATA_PTR;
struct resource_table {
u32 ver;
u32 num;
u32 reserved[2];
u32 offset[0];
} __packed;
typedef int (*handle_resource_t) (struct udevice *, void *, int offset, int avail);
static struct resource_table *rsc_table;
/**
* for_each_remoteproc_device() - iterate through the list of rproc devices
@ -196,6 +212,80 @@ static int rproc_post_probe(struct udevice *dev)
return 0;
}
/**
* rproc_add_res() - After parsing the resource table add the mappings
* @dev: device we finished probing
* @mapping: rproc_mem_entry for the resource
*
* Return: if the remote proc driver has a add_res routine, invokes it and
* hands over the return value. overall, 0 if all went well, else appropriate
* error value.
*/
static int rproc_add_res(struct udevice *dev, struct rproc_mem_entry *mapping)
{
const struct dm_rproc_ops *ops = rproc_get_ops(dev);
if (!ops->add_res)
return -ENOSYS;
return ops->add_res(dev, mapping);
}
/**
* rproc_alloc_mem() - After parsing the resource table allocat mem
* @dev: device we finished probing
* @len: rproc_mem_entry for the resource
* @align: alignment for the resource
*
* Return: if the remote proc driver has a add_res routine, invokes it and
* hands over the return value. overall, 0 if all went well, else appropriate
* error value.
*/
static void *rproc_alloc_mem(struct udevice *dev, unsigned long len,
unsigned long align)
{
const struct dm_rproc_ops *ops;
ops = rproc_get_ops(dev);
if (!ops) {
debug("%s driver has no ops?\n", dev->name);
return NULL;
}
if (ops->alloc_mem)
return ops->alloc_mem(dev, len, align);
return NULL;
}
/**
* rproc_config_pagetable() - Configure page table for remote processor
* @dev: device we finished probing
* @virt: Virtual address of the resource
* @phys: Physical address the resource
* @len: length the resource
*
* Return: if the remote proc driver has a add_res routine, invokes it and
* hands over the return value. overall, 0 if all went well, else appropriate
* error value.
*/
static int rproc_config_pagetable(struct udevice *dev, unsigned int virt,
unsigned int phys, unsigned int len)
{
const struct dm_rproc_ops *ops;
ops = rproc_get_ops(dev);
if (!ops) {
debug("%s driver has no ops?\n", dev->name);
return -EINVAL;
}
if (ops->config_pagetable)
return ops->config_pagetable(dev, virt, phys, len);
return 0;
}
UCLASS_DRIVER(rproc) = {
.id = UCLASS_REMOTEPROC,
.name = "remoteproc",
@ -426,3 +516,447 @@ int rproc_is_running(int id)
{
return _rproc_ops_wrapper(id, RPROC_RUNNING);
};
static int handle_trace(struct udevice *dev, struct fw_rsc_trace *rsc,
int offset, int avail)
{
if (sizeof(*rsc) > avail) {
debug("trace rsc is truncated\n");
return -EINVAL;
}
/*
* make sure reserved bytes are zeroes
*/
if (rsc->reserved) {
debug("trace rsc has non zero reserved bytes\n");
return -EINVAL;
}
debug("trace rsc: da 0x%x, len 0x%x\n", rsc->da, rsc->len);
return 0;
}
static int handle_devmem(struct udevice *dev, struct fw_rsc_devmem *rsc,
int offset, int avail)
{
struct rproc_mem_entry *mapping;
if (sizeof(*rsc) > avail) {
debug("devmem rsc is truncated\n");
return -EINVAL;
}
/*
* make sure reserved bytes are zeroes
*/
if (rsc->reserved) {
debug("devmem rsc has non zero reserved bytes\n");
return -EINVAL;
}
debug("devmem rsc: pa 0x%x, da 0x%x, len 0x%x\n",
rsc->pa, rsc->da, rsc->len);
rproc_config_pagetable(dev, rsc->da, rsc->pa, rsc->len);
mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
if (!mapping)
return -ENOMEM;
/*
* We'll need this info later when we'll want to unmap everything
* (e.g. on shutdown).
*
* We can't trust the remote processor not to change the resource
* table, so we must maintain this info independently.
*/
mapping->dma = rsc->pa;
mapping->da = rsc->da;
mapping->len = rsc->len;
rproc_add_res(dev, mapping);
debug("mapped devmem pa 0x%x, da 0x%x, len 0x%x\n",
rsc->pa, rsc->da, rsc->len);
return 0;
}
static int handle_carveout(struct udevice *dev, struct fw_rsc_carveout *rsc,
int offset, int avail)
{
struct rproc_mem_entry *mapping;
if (sizeof(*rsc) > avail) {
debug("carveout rsc is truncated\n");
return -EINVAL;
}
/*
* make sure reserved bytes are zeroes
*/
if (rsc->reserved) {
debug("carveout rsc has non zero reserved bytes\n");
return -EINVAL;
}
debug("carveout rsc: da %x, pa %x, len %x, flags %x\n",
rsc->da, rsc->pa, rsc->len, rsc->flags);
rsc->pa = (uintptr_t)rproc_alloc_mem(dev, rsc->len, 8);
if (!rsc->pa) {
debug
("failed to allocate carveout rsc: da %x, pa %x, len %x, flags %x\n",
rsc->da, rsc->pa, rsc->len, rsc->flags);
return -ENOMEM;
}
rproc_config_pagetable(dev, rsc->da, rsc->pa, rsc->len);
/*
* Ok, this is non-standard.
*
* Sometimes we can't rely on the generic iommu-based DMA API
* to dynamically allocate the device address and then set the IOMMU
* tables accordingly, because some remote processors might
* _require_ us to use hard coded device addresses that their
* firmware was compiled with.
*
* In this case, we must use the IOMMU API directly and map
* the memory to the device address as expected by the remote
* processor.
*
* Obviously such remote processor devices should not be configured
* to use the iommu-based DMA API: we expect 'dma' to contain the
* physical address in this case.
*/
mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
if (!mapping)
return -ENOMEM;
/*
* We'll need this info later when we'll want to unmap
* everything (e.g. on shutdown).
*
* We can't trust the remote processor not to change the
* resource table, so we must maintain this info independently.
*/
mapping->dma = rsc->pa;
mapping->da = rsc->da;
mapping->len = rsc->len;
rproc_add_res(dev, mapping);
debug("carveout mapped 0x%x to 0x%x\n", rsc->da, rsc->pa);
return 0;
}
#define RPROC_PAGE_SHIFT 12
#define RPROC_PAGE_SIZE BIT(RPROC_PAGE_SHIFT)
#define RPROC_PAGE_ALIGN(x) (((x) + (RPROC_PAGE_SIZE - 1)) & ~(RPROC_PAGE_SIZE - 1))
static int alloc_vring(struct udevice *dev, struct fw_rsc_vdev *rsc, int i)
{
struct fw_rsc_vdev_vring *vring = &rsc->vring[i];
int size;
int order;
void *pa;
debug("vdev rsc: vring%d: da %x, qsz %d, align %d\n",
i, vring->da, vring->num, vring->align);
/*
* verify queue size and vring alignment are sane
*/
if (!vring->num || !vring->align) {
debug("invalid qsz (%d) or alignment (%d)\n", vring->num,
vring->align);
return -EINVAL;
}
/*
* actual size of vring (in bytes)
*/
size = RPROC_PAGE_ALIGN(vring_size(vring->num, vring->align));
order = vring->align >> RPROC_PAGE_SHIFT;
pa = rproc_alloc_mem(dev, size, order);
if (!pa) {
debug("failed to allocate vring rsc\n");
return -ENOMEM;
}
debug("alloc_mem(%#x, %d): %p\n", size, order, pa);
vring->da = (uintptr_t)pa;
return !pa;
}
static int handle_vdev(struct udevice *dev, struct fw_rsc_vdev *rsc,
int offset, int avail)
{
int i, ret;
void *pa;
/*
* make sure resource isn't truncated
*/
if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct fw_rsc_vdev_vring)
+ rsc->config_len > avail) {
debug("vdev rsc is truncated\n");
return -EINVAL;
}
/*
* make sure reserved bytes are zeroes
*/
if (rsc->reserved[0] || rsc->reserved[1]) {
debug("vdev rsc has non zero reserved bytes\n");
return -EINVAL;
}
debug("vdev rsc: id %d, dfeatures %x, cfg len %d, %d vrings\n",
rsc->id, rsc->dfeatures, rsc->config_len, rsc->num_of_vrings);
/*
* we currently support only two vrings per rvdev
*/
if (rsc->num_of_vrings > 2) {
debug("too many vrings: %d\n", rsc->num_of_vrings);
return -EINVAL;
}
/*
* allocate the vrings
*/
for (i = 0; i < rsc->num_of_vrings; i++) {
ret = alloc_vring(dev, rsc, i);
if (ret)
goto alloc_error;
}
pa = rproc_alloc_mem(dev, RPMSG_TOTAL_BUF_SPACE, 6);
if (!pa) {
debug("failed to allocate vdev rsc\n");
return -ENOMEM;
}
debug("vring buffer alloc_mem(%#x, 6): %p\n", RPMSG_TOTAL_BUF_SPACE,
pa);
return 0;
alloc_error:
return ret;
}
/*
* A lookup table for resource handlers. The indices are defined in
* enum fw_resource_type.
*/
static handle_resource_t loading_handlers[RSC_LAST] = {
[RSC_CARVEOUT] = (handle_resource_t)handle_carveout,
[RSC_DEVMEM] = (handle_resource_t)handle_devmem,
[RSC_TRACE] = (handle_resource_t)handle_trace,
[RSC_VDEV] = (handle_resource_t)handle_vdev,
};
/*
* handle firmware resource entries before booting the remote processor
*/
static int handle_resources(struct udevice *dev, int len,
handle_resource_t handlers[RSC_LAST])
{
handle_resource_t handler;
int ret = 0, i;
for (i = 0; i < rsc_table->num; i++) {
int offset = rsc_table->offset[i];
struct fw_rsc_hdr *hdr = (void *)rsc_table + offset;
int avail = len - offset - sizeof(*hdr);
void *rsc = (void *)hdr + sizeof(*hdr);
/*
* make sure table isn't truncated
*/
if (avail < 0) {
debug("rsc table is truncated\n");
return -EINVAL;
}
debug("rsc: type %d\n", hdr->type);
if (hdr->type >= RSC_LAST) {
debug("unsupported resource %d\n", hdr->type);
continue;
}
handler = handlers[hdr->type];
if (!handler)
continue;
ret = handler(dev, rsc, offset + sizeof(*hdr), avail);
if (ret)
break;
}
return ret;
}
static int
handle_intmem_to_l3_mapping(struct udevice *dev,
struct rproc_intmem_to_l3_mapping *l3_mapping)
{
u32 i = 0;
for (i = 0; i < l3_mapping->num_entries; i++) {
struct l3_map *curr_map = &l3_mapping->mappings[i];
struct rproc_mem_entry *mapping;
mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
if (!mapping)
return -ENOMEM;
mapping->dma = curr_map->l3_addr;
mapping->da = curr_map->priv_addr;
mapping->len = curr_map->len;
rproc_add_res(dev, mapping);
}
return 0;
}
static Elf32_Shdr *rproc_find_table(unsigned int addr)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Shdr *shdr; /* Section header structure pointer */
Elf32_Shdr sectionheader;
int i;
u8 *elf_data;
char *name_table;
struct resource_table *ptable;
ehdr = (Elf32_Ehdr *)(uintptr_t)addr;
elf_data = (u8 *)ehdr;
shdr = (Elf32_Shdr *)(elf_data + ehdr->e_shoff);
memcpy(&sectionheader, &shdr[ehdr->e_shstrndx], sizeof(sectionheader));
name_table = (char *)(elf_data + sectionheader.sh_offset);
for (i = 0; i < ehdr->e_shnum; i++, shdr++) {
memcpy(&sectionheader, shdr, sizeof(sectionheader));
u32 size = sectionheader.sh_size;
u32 offset = sectionheader.sh_offset;
if (strcmp
(name_table + sectionheader.sh_name, ".resource_table"))
continue;
ptable = (struct resource_table *)(elf_data + offset);
/*
* make sure table has at least the header
*/
if (sizeof(struct resource_table) > size) {
debug("header-less resource table\n");
return NULL;
}
/*
* we don't support any version beyond the first
*/
if (ptable->ver != 1) {
debug("unsupported fw ver: %d\n", ptable->ver);
return NULL;
}
/*
* make sure reserved bytes are zeroes
*/
if (ptable->reserved[0] || ptable->reserved[1]) {
debug("non zero reserved bytes\n");
return NULL;
}
/*
* make sure the offsets array isn't truncated
*/
if (ptable->num * sizeof(ptable->offset[0]) +
sizeof(struct resource_table) > size) {
debug("resource table incomplete\n");
return NULL;
}
return shdr;
}
return NULL;
}
struct resource_table *rproc_find_resource_table(struct udevice *dev,
unsigned int addr,
int *tablesz)
{
Elf32_Shdr *shdr;
Elf32_Shdr sectionheader;
struct resource_table *ptable;
u8 *elf_data = (u8 *)(uintptr_t)addr;
shdr = rproc_find_table(addr);
if (!shdr) {
debug("%s: failed to get resource section header\n", __func__);
return NULL;
}
memcpy(&sectionheader, shdr, sizeof(sectionheader));
ptable = (struct resource_table *)(elf_data + sectionheader.sh_offset);
if (tablesz)
*tablesz = sectionheader.sh_size;
return ptable;
}
unsigned long rproc_parse_resource_table(struct udevice *dev, struct rproc *cfg)
{
struct resource_table *ptable = NULL;
int tablesz;
int ret;
unsigned long addr;
addr = cfg->load_addr;
ptable = rproc_find_resource_table(dev, addr, &tablesz);
if (!ptable) {
debug("%s : failed to find resource table\n", __func__);
return 0;
}
debug("%s : found resource table\n", __func__);
rsc_table = kzalloc(tablesz, GFP_KERNEL);
if (!rsc_table) {
debug("resource table alloc failed!\n");
return 0;
}
/*
* Copy the resource table into a local buffer before handling the
* resource table.
*/
memcpy(rsc_table, ptable, tablesz);
if (cfg->intmem_to_l3_mapping)
handle_intmem_to_l3_mapping(dev, cfg->intmem_to_l3_mapping);
ret = handle_resources(dev, tablesz, loading_handlers);
if (ret) {
debug("handle_resources failed: %d\n", ret);
return 0;
}
/*
* Instead of trying to mimic the kernel flow of copying the
* processed resource table into its post ELF load location in DDR
* copying it into its original location.
*/
memcpy(ptable, rsc_table, tablesz);
free(rsc_table);
rsc_table = NULL;
return 1;
}

6
drivers/reset/Kconfig
View File

@ -206,4 +206,10 @@ config RESET_ZYNQMP
passing request via Xilinx firmware interface to TF-A and PMU
firmware.
config RESET_DRA7
bool "Support for TI's DRA7 Reset driver"
depends on DM_RESET
help
Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
is supported.
endmenu

1
drivers/reset/Makefile
View File

@ -30,3 +30,4 @@ obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o

97
drivers/reset/reset-dra7.c Normal file
View File

@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments DRA7 reset driver
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Author: Keerthy <j-keerthy@ti.com>
*/
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <reset-uclass.h>
#include <dm/device_compat.h>
struct dra7_reset_priv {
u32 rstctrl;
u32 rstst;
u8 nreset;
};
static int dra7_reset_request(struct reset_ctl *reset_ctl)
{
return 0;
}
static int dra7_reset_free(struct reset_ctl *reset_ctl)
{
return 0;
}
static inline void dra7_reset_rmw(u32 addr, u32 value, u32 mask)
{
writel(((readl(addr) & (~mask)) | (value & mask)), addr);
}
static int dra7_reset_deassert(struct reset_ctl *reset_ctl)
{
struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int mask = 1 << reset_ctl->id;
if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
return -EINVAL;
dra7_reset_rmw(priv->rstctrl, 0x0, mask);
while ((readl(priv->rstst) & mask) != mask)
;
return 0;
}
static int dra7_reset_assert(struct reset_ctl *reset_ctl)
{
struct dra7_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int mask = 1 << reset_ctl->id;
if (reset_ctl->id < 0 || reset_ctl->id >= priv->nreset)
return -EINVAL;
dra7_reset_rmw(priv->rstctrl, mask, 0x0);
return 0;
}
struct reset_ops dra7_reset_ops = {
.request = dra7_reset_request,
.rfree = dra7_reset_free,
.rst_assert = dra7_reset_assert,
.rst_deassert = dra7_reset_deassert,
};
static const struct udevice_id dra7_reset_ids[] = {
{ .compatible = "ti,dra7-reset" },
{ }
};
static int dra7_reset_probe(struct udevice *dev)
{
struct dra7_reset_priv *priv = dev_get_priv(dev);
priv->rstctrl = dev_read_addr(dev);
priv->rstst = priv->rstctrl + 0x4;
priv->nreset = dev_read_u32_default(dev, "ti,nresets", 1);
dev_info(dev, "dra7-reset successfully probed %s\n", dev->name);
return 0;
}
U_BOOT_DRIVER(dra7_reset) = {
.name = "dra7_reset",
.id = UCLASS_RESET,
.of_match = dra7_reset_ids,
.probe = dra7_reset_probe,
.ops = &dra7_reset_ops,
.priv_auto = sizeof(struct dra7_reset_priv),
};

44
drivers/soc/soc_ti_k3.c
View File

@ -14,9 +14,7 @@
#define J721E 0xbb64
#define J7200 0xbb6d
#define AM64X 0xbb38
#define REV_SR1_0 0
#define REV_SR2_0 1
#define J721S2 0xbb75
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
@ -48,6 +46,9 @@ static const char *get_family_string(u32 idreg)
case AM64X:
family = "AM64X";
break;
case J721S2:
family = "J721S2";
break;
default:
family = "Unknown Silicon";
};
@ -55,25 +56,42 @@ static const char *get_family_string(u32 idreg)
return family;
}
static char *j721e_rev_string_map[] = {
"1.0", "1.1",
};
static char *am65x_rev_string_map[] = {
"1.0", "2.0",
};
static const char *get_rev_string(u32 idreg)
{
const char *revision;
u32 rev;
u32 soc;
rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
switch (rev) {
case REV_SR1_0:
revision = "1.0";
break;
case REV_SR2_0:
revision = "2.0";
break;
switch (soc) {
case J721E:
if (rev > ARRAY_SIZE(j721e_rev_string_map))
goto bail;
return j721e_rev_string_map[rev];
case AM65X:
if (rev > ARRAY_SIZE(am65x_rev_string_map))
goto bail;
return am65x_rev_string_map[rev];
case AM64X:
case J7200:
default:
revision = "Unknown Revision";
if (!rev)
return "1.0";
};
return revision;
bail:
return "Unknown Revision";
}
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)

19
include/configs/j721e_evm.h
View File

@ -119,6 +119,16 @@
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
"dorprocboot=1\0" \
"do_main_cpsw0_qsgmii_phyinit=1\0" \
"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
"gpio clear gpio@22_16\0" \
"main_cpsw0_qsgmii_phyinit=" \
"if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
"test ${boot} = mmc; then " \
"run init_main_cpsw0_qsgmii_phy;" \
"fi;\0"
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
@ -136,15 +146,6 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
"do_main_cpsw0_qsgmii_phyinit=1\0" \
"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
"gpio clear gpio@22_16\0" \
"main_cpsw0_qsgmii_phyinit=" \
"if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
"test ${boot} = mmc; then " \
"run init_main_cpsw0_qsgmii_phy;" \
"fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "

191
include/configs/j721s2_evm.h Normal file
View File

@ -0,0 +1,191 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration header file for K3 J721S2 EVM
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*/
#ifndef __CONFIG_J721S2_EVM_H
#define __CONFIG_J721S2_EVM_H
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#include <environment/ti/k3_rproc.h>
#include <environment/ti/ufs.h>
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
#define CONFIG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
#define CONFIG_SYS_UBOOT_BASE 0x50080000
/*
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
* possible (to allow the build to go through), as this directly affects
* our memory footprint. The less we use for BSS the more we have available
* for everything else.
*/
#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
/*
* Link BSS to be within SPL in a dedicated region located near the top of
* the MCU SRAM, this way making it available also before relocation. Note
* that we are not using the actual top of the MCU SRAM as there is a memory
* location filled in by the boot ROM that we want to read out without any
* interference from the C context.
*/
#define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\
CONFIG_SPL_BSS_MAX_SIZE)
/* Set the stack right below the SPL BSS section */
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
/* Configure R5 SPL post-relocation malloc pool in DDR */
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
/* Image load address in RAM for DFU boot*/
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_CQSPI_REF_CLK 133333333
/* HyperFlash related configuration */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
/* U-Boot general configuration */
#define EXTRA_ENV_J721S2_BOARD_SETTINGS \
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"findfdt=" \
"setenv name_fdt ${default_device_tree};" \
"setenv fdtfile ${name_fdt}\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 " \
"${mtdparts}\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
#define PARTS_DEFAULT \
/* Linux partitions */ \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
#ifdef CONFIG_SYS_K3_SPL_ATF
#if defined(CONFIG_TARGET_J721S2_R5_EVM)
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
"addr_mcur5f0_0load=0x89000000\0" \
"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
#elif defined(CONFIG_TARGET_J7200_R5_EVM)
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
"addr_mcur5f0_0load=0x89000000\0" \
"name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
#endif /* CONFIG_TARGET_J721S2_R5_EVM */
#else
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
#endif /* CONFIG_SYS_K3_SPL_ATF */
/* U-Boot MMC-specific configuration */
#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
"boot=mmc\0" \
"mmcdev=1\0" \
"bootpart=1:2\0" \
"bootdir=/boot\0" \
EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
"get_overlay_mmc=" \
"fdt address ${fdtaddr};" \
"fdt resize 0x100000;" \
"for overlay in $name_overlays;" \
"do;" \
"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
"fdt apply ${dtboaddr};" \
"done;\0" \
"partitions=" PARTS_DEFAULT \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_kern}\0" \
"get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
"${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
#endif
#ifdef CONFIG_TARGET_J721S2_A72_EVM
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j721s2-main-r5f0_0-fw " \
"3 /lib/firmware/j721s2-main-r5f0_1-fw " \
"4 /lib/firmware/j721s2-main-r5f1_0-fw " \
"5 /lib/firmware/j721s2-main-r5f1_1-fw " \
"6 /lib/firmware/j721s2-c71_0-fw " \
"7 /lib/firmware/j721s2-c71_1-fw "
#endif /* CONFIG_TARGET_J721S2_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
"do_main_cpsw0_qsgmii_phyinit=1\0" \
"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
"gpio clear gpio@22_16\0" \
"main_cpsw0_qsgmii_phyinit=" \
"if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
"test ${boot} = mmc; then " \
"run init_main_cpsw0_qsgmii_phy;" \
"fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
#endif
/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
#define EXTRA_ENV_DFUARGS \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_OSPI
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
#else
#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD
#endif
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_J721S2_BOARD_SETTINGS \
EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
EXTRA_ENV_RPROC_SETTINGS \
EXTRA_ENV_DFUARGS \
DEFAULT_UFS_TI_ARGS \
EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
/* MMC ENV related defines */
#endif /* __CONFIG_J721S2_EVM_H */

13
include/configs/nokia_rx51.h
View File

@ -77,21 +77,10 @@
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
/* functions for cfb_console */
#define VIDEO_KBD_INIT_FCT rx51_kp_init()
#define VIDEO_TSTC_FCT rx51_kp_tstc
#define VIDEO_GETC_FCT rx51_kp_getc
#ifndef __ASSEMBLY__
struct stdio_dev;
int rx51_kp_init(void);
int rx51_kp_tstc(struct stdio_dev *sdev);
int rx51_kp_getc(struct stdio_dev *sdev);
#endif
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
"stdin=usbtty,serial,vga\0" \
"stdin=usbtty,serial,keyboard\0" \
"stdout=usbtty,serial,vga\0" \
"stderr=usbtty,serial,vga\0" \
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \

22
include/dt-bindings/mux/ti-serdes.h
View File

@ -95,4 +95,26 @@
#define AM64_SERDES0_LANE0_PCIE0 0x0
#define AM64_SERDES0_LANE0_USB 0x1
/* J721S2 */
#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1
#define J721S2_SERDES0_LANE1_USB 0x2
#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1
#define J721S2_SERDES0_LANE3_USB 0x2
#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
#endif /* _DT_BINDINGS_MUX_TI_SERDES */

4
include/dt-bindings/phy/phy-cadence.h
View File

@ -17,4 +17,8 @@
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
#define SIERRA_SERDES_NO_SSC 0
#define SIERRA_SERDES_EXTERNAL_SSC 1
#define SIERRA_SERDES_INTERNAL_SSC 2
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */

3
include/dt-bindings/pinctrl/k3.h
View File

@ -38,4 +38,7 @@
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#endif

1
include/k3-clk.h
View File

@ -173,6 +173,7 @@ struct ti_k3_clk_platdata {
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);

1
include/k3-dev.h
View File

@ -77,6 +77,7 @@ struct ti_k3_pd_platdata {
extern const struct ti_k3_pd_platdata j721e_pd_platdata;
extern const struct ti_k3_pd_platdata j7200_pd_platdata;
extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);

26
include/linux/bitmap.h
View File

@ -159,6 +159,32 @@ static inline unsigned long find_first_bit(const unsigned long *addr, unsigned l
(bit) < (size); \
(bit) = find_next_bit((addr), (size), (bit) + 1))
static inline unsigned long
bitmap_find_next_zero_area(unsigned long *map,
unsigned long size,
unsigned long start,
unsigned int nr, unsigned long align_mask)
{
unsigned long index, end, i;
again:
index = find_next_zero_bit(map, size, start);
/*
* Align allocation
*/
index = (index + align_mask) & ~align_mask;
end = index + nr;
if (end > size)
return end;
i = find_next_bit(map, end, index);
if (i < end) {
start = i + 1;
goto again;
}
return index;
}
static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
{
if (small_const_nbits(nbits)) {

384
include/remoteproc.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015
* Texas Instruments Incorporated - http://www.ti.com/
@ -15,6 +15,375 @@
*/
#include <dm/platdata.h> /* For platform data support - non dt world */
/**
* struct fw_rsc_hdr - firmware resource entry header
* @type: resource type
* @data: resource data
*
* Every resource entry begins with a 'struct fw_rsc_hdr' header providing
* its @type. The content of the entry itself will immediately follow
* this header, and it should be parsed according to the resource type.
*/
struct fw_rsc_hdr {
u32 type;
u8 data[0];
};
/**
* enum fw_resource_type - types of resource entries
*
* @RSC_CARVEOUT: request for allocation of a physically contiguous
* memory region.
* @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
* @RSC_TRACE: announces the availability of a trace buffer into which
* the remote processor will be writing logs.
* @RSC_VDEV: declare support for a virtio device, and serve as its
* virtio header.
* @RSC_PRELOAD_VENDOR: a vendor resource type that needs to be handled by
* remoteproc implementations before loading
* @RSC_POSTLOAD_VENDOR: a vendor resource type that needs to be handled by
* remoteproc implementations after loading
* @RSC_LAST: just keep this one at the end
*
* For more details regarding a specific resource type, please see its
* dedicated structure below.
*
* Please note that these values are used as indices to the rproc_handle_rsc
* lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
* check the validity of an index before the lookup table is accessed, so
* please update it as needed.
*/
enum fw_resource_type {
RSC_CARVEOUT = 0,
RSC_DEVMEM = 1,
RSC_TRACE = 2,
RSC_VDEV = 3,
RSC_PRELOAD_VENDOR = 4,
RSC_POSTLOAD_VENDOR = 5,
RSC_LAST = 6,
};
#define FW_RSC_ADDR_ANY (-1)
/**
* struct fw_rsc_carveout - physically contiguous memory request
* @da: device address
* @pa: physical address
* @len: length (in bytes)
* @flags: iommu protection flags
* @reserved: reserved (must be zero)
* @name: human-readable name of the requested memory region
*
* This resource entry requests the host to allocate a physically contiguous
* memory region.
*
* These request entries should precede other firmware resource entries,
* as other entries might request placing other data objects inside
* these memory regions (e.g. data/code segments, trace resource entries, ...).
*
* Allocating memory this way helps utilizing the reserved physical memory
* (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
* needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
* pressure is important; it may have a substantial impact on performance.
*
* If the firmware is compiled with static addresses, then @da should specify
* the expected device address of this memory region. If @da is set to
* FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
* overwrite @da with the dynamically allocated address.
*
* We will always use @da to negotiate the device addresses, even if it
* isn't using an iommu. In that case, though, it will obviously contain
* physical addresses.
*
* Some remote processors needs to know the allocated physical address
* even if they do use an iommu. This is needed, e.g., if they control
* hardware accelerators which access the physical memory directly (this
* is the case with OMAP4 for instance). In that case, the host will
* overwrite @pa with the dynamically allocated physical address.
* Generally we don't want to expose physical addresses if we don't have to
* (remote processors are generally _not_ trusted), so we might want to
* change this to happen _only_ when explicitly required by the hardware.
*
* @flags is used to provide IOMMU protection flags, and @name should
* (optionally) contain a human readable name of this carveout region
* (mainly for debugging purposes).
*/
struct fw_rsc_carveout {
u32 da;
u32 pa;
u32 len;
u32 flags;
u32 reserved;
u8 name[32];
};
/**
* struct fw_rsc_devmem - iommu mapping request
* @da: device address
* @pa: physical address
* @len: length (in bytes)
* @flags: iommu protection flags
* @reserved: reserved (must be zero)
* @name: human-readable name of the requested region to be mapped
*
* This resource entry requests the host to iommu map a physically contiguous
* memory region. This is needed in case the remote processor requires
* access to certain memory-based peripherals; _never_ use it to access
* regular memory.
*
* This is obviously only needed if the remote processor is accessing memory
* via an iommu.
*
* @da should specify the required device address, @pa should specify
* the physical address we want to map, @len should specify the size of
* the mapping and @flags is the IOMMU protection flags. As always, @name may
* (optionally) contain a human readable name of this mapping (mainly for
* debugging purposes).
*
* Note: at this point we just "trust" those devmem entries to contain valid
* physical addresses, but this isn't safe and will be changed: eventually we
* want remoteproc implementations to provide us ranges of physical addresses
* the firmware is allowed to request, and not allow firmwares to request
* access to physical addresses that are outside those ranges.
*/
struct fw_rsc_devmem {
u32 da;
u32 pa;
u32 len;
u32 flags;
u32 reserved;
u8 name[32];
};
/**
* struct fw_rsc_trace - trace buffer declaration
* @da: device address
* @len: length (in bytes)
* @reserved: reserved (must be zero)
* @name: human-readable name of the trace buffer
*
* This resource entry provides the host information about a trace buffer
* into which the remote processor will write log messages.
*
* @da specifies the device address of the buffer, @len specifies
* its size, and @name may contain a human readable name of the trace buffer.
*
* After booting the remote processor, the trace buffers are exposed to the
* user via debugfs entries (called trace0, trace1, etc..).
*/
struct fw_rsc_trace {
u32 da;
u32 len;
u32 reserved;
u8 name[32];
};
/**
* struct fw_rsc_vdev_vring - vring descriptor entry
* @da: device address
* @align: the alignment between the consumer and producer parts of the vring
* @num: num of buffers supported by this vring (must be power of two)
* @notifyid is a unique rproc-wide notify index for this vring. This notify
* index is used when kicking a remote processor, to let it know that this
* vring is triggered.
* @pa: physical address
*
* This descriptor is not a resource entry by itself; it is part of the
* vdev resource type (see below).
*
* Note that @da should either contain the device address where
* the remote processor is expecting the vring, or indicate that
* dynamically allocation of the vring's device address is supported.
*/
struct fw_rsc_vdev_vring {
u32 da;
u32 align;
u32 num;
u32 notifyid;
u32 pa;
};
/**
* struct fw_rsc_vdev - virtio device header
* @id: virtio device id (as in virtio_ids.h)
* @notifyid is a unique rproc-wide notify index for this vdev. This notify
* index is used when kicking a remote processor, to let it know that the
* status/features of this vdev have changes.
* @dfeatures specifies the virtio device features supported by the firmware
* @gfeatures is a place holder used by the host to write back the
* negotiated features that are supported by both sides.
* @config_len is the size of the virtio config space of this vdev. The config
* space lies in the resource table immediate after this vdev header.
* @status is a place holder where the host will indicate its virtio progress.
* @num_of_vrings indicates how many vrings are described in this vdev header
* @reserved: reserved (must be zero)
* @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
*
* This resource is a virtio device header: it provides information about
* the vdev, and is then used by the host and its peer remote processors
* to negotiate and share certain virtio properties.
*
* By providing this resource entry, the firmware essentially asks remoteproc
* to statically allocate a vdev upon registration of the rproc (dynamic vdev
* allocation is not yet supported).
*
* Note: unlike virtualization systems, the term 'host' here means
* the Linux side which is running remoteproc to control the remote
* processors. We use the name 'gfeatures' to comply with virtio's terms,
* though there isn't really any virtualized guest OS here: it's the host
* which is responsible for negotiating the final features.
* Yeah, it's a bit confusing.
*
* Note: immediately following this structure is the virtio config space for
* this vdev (which is specific to the vdev; for more info, read the virtio
* spec). the size of the config space is specified by @config_len.
*/
struct fw_rsc_vdev {
u32 id;
u32 notifyid;
u32 dfeatures;
u32 gfeatures;
u32 config_len;
u8 status;
u8 num_of_vrings;
u8 reserved[2];
struct fw_rsc_vdev_vring vring[0];
};
/**
* struct rproc_mem_entry - memory entry descriptor
* @va: virtual address
* @dma: dma address
* @len: length, in bytes
* @da: device address
* @priv: associated data
* @name: associated memory region name (optional)
* @node: list node
*/
struct rproc_mem_entry {
void *va;
dma_addr_t dma;
int len;
u32 da;
void *priv;
char name[32];
struct list_head node;
};
struct rproc;
typedef u32(*init_func_proto) (u32 core_id, struct rproc *cfg);
struct l3_map {
u32 priv_addr;
u32 l3_addr;
u32 len;
};
struct rproc_intmem_to_l3_mapping {
u32 num_entries;
struct l3_map mappings[16];
};
/**
* enum rproc_crash_type - remote processor crash types
* @RPROC_MMUFAULT: iommu fault
* @RPROC_WATCHDOG: watchdog bite
* @RPROC_FATAL_ERROR fatal error
*
* Each element of the enum is used as an array index. So that, the value of
* the elements should be always something sane.
*
* Feel free to add more types when needed.
*/
enum rproc_crash_type {
RPROC_MMUFAULT,
RPROC_WATCHDOG,
RPROC_FATAL_ERROR,
};
/* we currently support only two vrings per rvdev */
#define RVDEV_NUM_VRINGS 2
#define RPMSG_NUM_BUFS (512)
#define RPMSG_BUF_SIZE (512)
#define RPMSG_TOTAL_BUF_SPACE (RPMSG_NUM_BUFS * RPMSG_BUF_SIZE)
/**
* struct rproc_vring - remoteproc vring state
* @va: virtual address
* @dma: dma address
* @len: length, in bytes
* @da: device address
* @align: vring alignment
* @notifyid: rproc-specific unique vring index
* @rvdev: remote vdev
* @vq: the virtqueue of this vring
*/
struct rproc_vring {
void *va;
dma_addr_t dma;
int len;
u32 da;
u32 align;
int notifyid;
struct rproc_vdev *rvdev;
struct virtqueue *vq;
};
/** struct rproc - structure with all processor specific information for
* loading remotecore from boot loader.
*
* @num_iommus: Number of IOMMUs for this remote core. Zero indicates that the
* processor does not have an IOMMU.
*
* @cma_base: Base address of the carveout for this remotecore.
*
* @cma_size: Length of the carveout in bytes.
*
* @page_table_addr: array with the physical address of the page table. We are
* using the same page table for both IOMMU's. There is currently no strong
* usecase for maintaining different page tables for different MMU's servicing
* the same CPU.
*
* @mmu_base_addr: base address of the MMU
*
* @entry_point: address that is the entry point for the remote core. This
* address is in the memory view of the remotecore.
*
* @load_addr: Address to which the bootloader loads the firmware from
* persistent storage before invoking the ELF loader. Keeping this address
* configurable allows future optimizations such as loading the firmware from
* storage for remotecore2 via EDMA while the CPU is processing the ELF image
* of remotecore1. This address is in the memory view of the A15.
*
* @firmware_name: Name of the file that is expected to contain the ELF image.
*
* @has_rsc_table: Flag populated after parsing the ELF binary on target.
*/
struct rproc {
u32 num_iommus;
unsigned long cma_base;
u32 cma_size;
unsigned long page_table_addr;
unsigned long mmu_base_addr[2];
unsigned long load_addr;
unsigned long entry_point;
char *core_name;
char *firmware_name;
char *ptn;
init_func_proto start_clocks;
init_func_proto config_mmu;
init_func_proto config_peripherals;
init_func_proto start_core;
u32 has_rsc_table;
struct rproc_intmem_to_l3_mapping *intmem_to_l3_mapping;
u32 trace_pa;
u32 trace_len;
};
extern struct rproc *rproc_cfg_arr[2];
/**
* enum rproc_mem_type - What type of memory model does the rproc use
* @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory
@ -126,6 +495,12 @@ struct dm_rproc_ops {
* @return virtual address.
*/
void * (*device_to_virt)(struct udevice *dev, ulong da, ulong size);
int (*add_res)(struct udevice *dev,
struct rproc_mem_entry *mapping);
void * (*alloc_mem)(struct udevice *dev, unsigned long len,
unsigned long align);
unsigned int (*config_pagetable)(struct udevice *dev, unsigned int virt,
unsigned int phys, unsigned int len);
};
/* Accessor */
@ -322,6 +697,13 @@ int rproc_elf64_load_rsc_table(struct udevice *dev, ulong fw_addr,
*/
int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr,
ulong fw_size, ulong *rsc_addr, ulong *rsc_size);
unsigned long rproc_parse_resource_table(struct udevice *dev,
struct rproc *cfg);
struct resource_table *rproc_find_resource_table(struct udevice *dev,
unsigned int addr,
int *tablesz);
#else
static inline int rproc_init(void) { return -ENOSYS; }
static inline int rproc_dev_init(int id) { return -ENOSYS; }